CXL5509P

CXL5509M/P CMOS-CCD 1H/2H Delay Line for NTSC Description The CXL5509M/P is a CMOS-CCD delay line developed for video signal processing. Usage in conjunction with an external low-pass filter provide 1H and 2H delay signals simultaneously (For NTSC signals). Features • Single power supply (5V) • Low power consumption 130mW (Typ.) • Built-in peripheral circuits • Built-in quadruple PLL circuit • For NTSC signals • 1 input and 2 outputs (Outputs for both 1H and 2H delays) Functions • 906-bit (1H) and 1816-bit (2H) CCD register • Clock driver • Auto-bias circuit • Sync tip clamp circuit • Sample-and-hold circuit • Quadruple PLL circuit Structure CMOS-CCD CXL5509M 16 pin SOP (Plastic) CXL5509P 16 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V • Supply voltage VDD • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5509M 400 mW CXL5509P 800 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform sine wave Input Signal Amplitude VSIG 571mVp-p (Max.) (at internal clamp condition) PC OUT Blook Diagram and Pin Configuration (Top View) VCO IN VDD VSS AB CLK 16 15 14 13 VSS 12 11 10 Auto-bias circuit PLL Driver Timing circuit Clamp circuit CCD (1816bit) 906bit Output circuit (S/H 1bit) 1816bit Output circuit (S/H 1bit) Bias circuit 1 2 3 4 5 6 7 IN Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– VSS (VCO OUT) VG1 VG2 OUT1 (1H) VSS OUT2 (2H) VSS VDD 9 8 E91401B7X-PS CXL5509M/P Pin Description Pin No. 1 2 3∗ 4 5 6 7 8 9 10 11 12 13 14 15 16 IN VG1 VG2 OUT1 VSS OUT2 VSS (VCO OUT) VSS VDD CLK VSS PC OUT VCO IN VDD AB VSS Symbol I/O I O I O — O (O) — — I — O I — O — Description Signal input (Non-inverted signal) Gate bias 1 DC output Gate bias 2 DC input 1H signal output (Inverted signal) GND 2H signal output (Inverted signal) GND or VCO output (4fsc) GND Power supply (5V) Clock input (fsc) GND Phase comparator output VCO input Power supply (5V) Autobias DC output GND 600 to 200kΩ > 10kΩ 40 to 500Ω 40 to 500Ω Impedance > 10kΩ (at no clamp) ∗ Description of Pin 3 (VG2) Control of input signal clamp condition 0V ........ Sync tip clamp condition 5V ........ Center bias condition The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is at 200mVp-p. –2– CXL5509M/P Electrical Characteristics (Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" Item Supply current Low frequency gain Frequency response Differential gain Differential phase S/N ratio Symbol IDD GL1 GL2 fR1 fR2 DG1 DG2 DP1 DP2 SN1 SN2 CP1 CP2 No signal input 5-staircase wave 50% white video signal 5-staircase wave Test conditions (Note 1) — 200kHz, 500mVp-p, sine wave 200kHz ← 3.58MHz, → 150mVp-p, sine wave SW conditions 1 a a a b← c → b← c → d d d d e e f f 2 b b b a a b b b b b b b b 3 a a b a b a b a b a b a b 4 a b b b b c c c c d d a a Min. Typ. Max. Unit Note 16 –2 –2 26 0 0 36 2 2 0 0 5 5 5 degree mA dB 2 3 –2.0 –1.0 –2.0 –1.0 — — — — 52 52 — — 3 3 3 3 56 56 — — dB 4 % 5 5 — — 350 350 dB 5 6 S/H pulse coupling mVp-p 7 –3– Electrical Characteristics Test Circuit 5V CLK fSC (3.579545MHz), 500mVp-p sine wave 0.1µ 3.3µ 120 3.3µ 82k 1µ 16 VSS AB CXL5509M/P IN 1 VG1 VG2 OUT1 VSS 5 2 3 4 SW4 b Note 1) c 1µ 1M LPF b a SW3 d BPF Note 2) ×3 Noise meter VDD VCO PC VSS IN OUT CLK VDD VSS (VCO OUT2 OUT) VSS 6 8 7 a 15 14 11 13 12 10 9 Oscilloscope 0.1µ 1000p 1000p 200kHz 500mVp-p sine wave a 200kHz 150mVp-p sine wave b Spectrum analyzer ×3 Vector scope SW1 5-staircase wave b d SW2 a 1000p 1000p –4– Note 1) 0 –3 –50 0 3.58MHz 150mVp-p sine wave c Note 2) [dB] LPF frequency response [dB] 0 –3 BPF frequency response 50% white video signal e f –50 6M 14.3M Frequency [Hz] 0 200 6M 14.3M Frequency [Hz] CXL5509M/P Application Circuit 5V CLK fSC (3.579545MHz), 500mVp-p sine wave 0.1µ 3.3µ 120 3.3µ 82k 1µ 16 14 11 10 15 12 13 9 0.1µ 1000p 1000p 1 1000p 1000p 330k 510 1k 30p V1 1µ (Inverted signal) 560k Transistor used PNP: 2SA1175 330k 510 1µ (Inverted signal) 560k 1k Transistor used PNP: 2SA1175 Delay time 170ns LPF 1k 30p 1k Delay time 170ns 2.2k 5V LPF 2 3 4 7 8 6 5 –5– 2.2k Signal input 1µ (Non-inverted signal) 2.2k 5V 2H Output 2.2k 2.2k (Non-inverted signal) Transistor used NPN: 2SC403 1M Note) When VCO OUT (Pin 7) is used the circuit below. When not used, GND. 5V 1.8k 7 1H Output 2.2k Transistor used NPN: 2SC403 (Non-inverted signal) 4fSC OUT 1.8k Transistor used NPN: 2SC403 CXL5509M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5509M/P Notes (1) By switching SW2, input condition turns out as follows. SW2 condition a b Input condition Center bias condition (approx. 2.1V) Approx. 2.1V bias is applied internally to the input signal Sync tip clamp conditions (2) This is the IC supply current value during clock and signal input. (3) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] (4) Indicates the dissipation at 3.58MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made according to the following formula. fR = 20 log OUT pin otuput voltage (3.58MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] (5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 143mV 285.5mV 500mV 143mV 1H 63.56µs (6) S/N ratio during 50% white video signal input shown in figure below is tested at video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µs –6– CXL5509M/P (7) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Test value (mVp-p) Clock fsc (3.579545MHz) sine wave 500mVp-p (Typ.) –7– CXL5509M/P Example of Representative Characteristics Supply current vs. Supply voltage 36 Supply current [mA] 26 16 4.75 5.0 Supply voltage [V] 5.25 Low frequency gain (1H) vs. Supply voltage 2 Low frequency gain (2H) vs. Supply voltage 2 Low frequency gain (1H) [dB] 1 Low frequency gain (2H) [dB] 5.0 Supply voltage [V] 5.25 1 0 0 –1 –1 –2 4.75 –2 4.75 5.0 Supply voltage [V] 5.25 Frequency response (1H) vs. Supply voltage 1 Frequency response (2H) vs. Supply voltage 1 Frequency response (1H) [dB] 0 Frequency response (2H) [dB] 5.0 Supply voltage [V] 5.25 0 –1 –1 –2 –2 –3 4.75 –3 4.75 5.0 Supply voltage [V] 5.25 –8– CXL5509M/P Differential gain (1H) vs. Supply voltage 5 5 Differential gain (2H) vs. Supply voltage Differential gain (1H) [%] 4 Differential gain (2H) [%] 5.0 Supply voltage [V] 5.25 4 3 3 2 2 1 4.75 1 4.75 5.0 Supply voltage [V] 5.25 Supply current vs. Ambient temperature 36 Supply current [mA] 26 16 –20 0 20 40 60 Ambient temperature [°C] 80 Low frequency gain (1H) vs. Ambient temperature 2 Low frequency gain (2H) vs. Ambient temperature 2 Low frequency gain (1H) [dB] 1 Low frequency gain (2H) [dB] 0 20 40 60 Ambient temperature [°C] 80 1 0 0 –1 –1 –2 –20 –2 –20 0 20 40 60 Ambient temperature [°C] 80 –9– CXL5509M/P Frequency response (1H) vs. Ambient temperature 1 Frequency response (2H) vs. Ambient temperature 1 Frequency response (1H) [dB] 0 Frequency response (2H) [dB] 0 20 40 60 Ambient temperature [°C] 80 0 –1 –1 –2 –2 –3 –20 –3 –20 0 20 40 60 Ambient temperature [°C] 80 Differential gain (1H) vs. Ambient temperature 8 Differential gain (2H) vs. Ambient temperature 8 Differential gain (1H) [%] 6 Differential gain (2H) [%] 0 20 40 60 Ambient temperature [°C] 80 6 4 4 2 2 0 –20 0 –20 0 20 40 60 Ambient temperature [°C] 80 – 10 – CXL5509M/P Frequency responses (1H) 2 0 Gian [dB] –2 –4 –6 10k 100k Frequency [Hz] 1M 10M Frequency responses (2H) 2 0 Gian [dB] –2 –4 –6 10k 100k Frequency [Hz] 1M 10M Note) 1H means 1H output; 2H means 2H output. – 11 – CXL5509M/P Package Outline CXL5509M Unit: mm 16PIN SOP (PLASTIC) + 0.4 9.9 – 0.1 + 0.4 1.85 – 0.15 16 9 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-16P-L01 SOP016-P-0300 LEAD MATERIAL COPPER ALLOY 0.2g LEAD TREATMENT EPOXY RESIN SOLDER PLATING CXL5509P 16PIN DIP (PLASTIC) + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.0 g 16 9 1 2.54 8 + 0.4 3.7 – 0.1 0.5 MIN 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-16P-01 DIP016-P-0300 Similar to MO-001-AE LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 12 – 7.62 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. + 0.3 6.4 – 0.1 + 0.4 19.2 – 0.1 0.5 ± 0.2 1 8 6.9