CXL5512P

CXL5512M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5512M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for NTSC signals including the external lowpass filter. Features • Single 5 V power supply • Low power consumption • Built-in peripheral circuit • Built-in tripling PLL circuit • Sync tip clamp mode Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD +6 • Operating temperature Topr –10 to +60 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD CXL5512M 350 CXL5512P 480 Recommended Operating Range (Ta=25 ˚C) VDD 5 V±5 % Recommended Clock Conditions (Ta=25 ˚C) • Input clock amplitude VCLK 400mVp-p (Typ.) • Clock frequency fCLK 3.579545 MHz • Input clock waveform Sine wave Block Diagram and Pin Configuration VDD VCO OUT VCO IN CLK CXL5512M 8 pin SOP (Plastic) CXL5512P 8 pin DIP (Plastic) Input Signal Amplitude VSIG 500mVp-p (typ.), 572 mVp-p (max.) (at internal clamp condition) Functions • 680-bit CCD register • Clock driver • Auto-bias circuit • Sync tip clamp circuit • Sample and hold circuit • Tripling PLL circuit • Inverted output Structure CMOS-CCD V °C °C mW mW 8 7 6 5 PLL Auto-bias circuit Timing circuit CCD (680bit) Output circuit (S/H 1 bit) Clamp circuit Clock driver Bias circuit A Bias circuit B 1 IN 2 AB 3 OUT 4 VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E93Y19-TE CXL5512M/P Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol IN AB OUT VSS CLK VCO IN VCO OUT VDD I/O I O O – I I O – Description Signal input Auto-bias DC output Signal output GND Clock input (fsc) VCO input VCO output (3fsc) 5 V power supply Impedance >10 KΩ 40 to 500 Ω >10 KΩ Electrical Characteristics (Ta=25°C, VDD=5 V, fCLK=3.579545 MHz, VCLK=400mVp-p, sine wave) See “Electrical Characteristics Test Circuit”. Item Symbol Conditions SW conditions Min. 1 2 a – 6 Typ. Max. Unit Note Supply current IDD ——— 200kHz 500mVp-p Sine wave 12 20 mA 1 Low frequency gain GL a b -2 0 2 dB 2 Frequency response fR 200kz ↔ 3.57 MHz b↔c 150mVp-p Sine wave 5-staircase wave (See Note 4.) 5-staircase wave (See Note 4.) b –2.5 –1.5 –0.5 dB 3 Differential gain DG d c 0 3 5 % 4 Differential phase DP d c 0 3 5 degree 4 S/H pulse coupling CP No signal input f a — — 350 mVp-p 5 S/N ratio SN 50 % white video signal (See Note 6.) e d 52 56 — dB 6 —2— CXL5512M/P NOTE 1 This is the IC supply current value during clock and signal input. 2 GL is the output gain of OUT pin when a 500 mVp-p, 200 kHz sine wave is fed to IN pin. OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] GL = 20 log 3 Indicates the dissipation at 3.58 MHz in relation to 200 kHz. From the output voltage at OUT pin when a 150 mVp-p, 200 kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150 mVp-p, 3.58 MHz sine wave is fed to the same, calculation is made according to the following formula. OUT pin output voltage (3.58 MHz) [mVp-p] [dB] OUT pin output voltage (200 kHz) [mVp-p] fR = 20 log 4 In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when the 5-staircase wave is fed. 143mV 357mV 500mV 143mV 1H 63.56µS 5 Leakage of internal clock components and related high frequency component to the output signal, during no signal input, is tested. Test value (mVp-p) —3— CXL5512M/P 6 S/N ratio during a 50 % white video signal input shown in Fig. below is tested at the video noise meter, in BPF 100 kHz to 4 MHz, Sub Carrier Trap mode. 178mV 321mV 143mV 1H 63.56µS CLOCK fSC (3.579545MHz) Sine wave 400mVp-p (Typ.) —4— Electrical Characteristics Test Circuit fSC (3.579545MHz) 400mVp-p Sine wave 2200p 6.8µ a A 5V 0.1µ 0.1µ 200kHz 500mVp-p Sine wave 8 7 VCO OUT VCO IN CLK 6 5 VDD b CXL5512M/P a VSS +15V IN AB OUT 200kHz 150mVp-p Sine wave Oscilloscop e b 1 3 4 2.2k 0.1µ 1µ 2 SW1 Spectrum analyzer SW2 Note 1) c LPF Note 2) d BPF ×3 Vector scope 3.57MHz 150mVp-p Sine wave 1M —5— Note 1) LPF frequency response [dB] 0 –3 0 –3 –50 5.8M Frequency 10.7M [Hz] –50 c d ×3 Noise meter 5-staircase wave Note 2) BPF frequency response [dB] 50 % white video signal e f CXL5512M/P 50 200 4.1M 10.7M Frequency [Hz] Application Circuit 5V fSC (3.579545MHz) 400mVp-p Sine wave 2200p 0.1µ 0.1µ 6.8µ 8 VDD VCO OUT VCO IN CLK 7 6 5 CXL5512M/P IN VSS AB OUT 1 2 3 33k 470 0.1µ 1M 4 5V Input —6— 1µ 1k 56k 5V Transistor used PNP: 2SA1175 3fSC OUT 1µ LPF Output 2.2k When VCO OUT (7 Pin) in use 1.8k Transistor used NPN: 2SC403 7 2SC403 2.2k CXL5512M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. CXL5512M/P Example of Representative Characteristics Supply current vs. Ambient temperature 20 1 Low frequency gain vs. Ambient temperature 18 16 Low frequency gain (dB) 0 Supply current (mA) –1 14 –2 12 10 –20 –3 0 20 40 60 80 –20 0 20 40 60 80 Ambient temperature (°C) Ambient temperature (°C) Frequency response vs. Ambient temperature 0 20 Supply current vs. Supply voltage 18 Frequency response (dB) –1 Supply current (mA) 0 20 40 60 80 16 14 –2 12 –3 –20 Ambient temperature (°C) 10 4.7 5 5 Supply voltage (V) 5.25 —7— CXL5512M/P Low frequency gain vs. Supply voltage 1 0 Frequency response vs. Supply voltage Frequency response (dB) Low frequency gain (dB) 0 –1 –1 –2 –2 –3 4.7 5 5 Supply voltage (V) 5.25 –3 4.7 5 5 Supply voltage (V) 5.25 Frequency response 0 –2 Gain (dB) –4 –6 –8 –10 10k 100k Frequency (Hz) 1M 10 M —8— CXL5512M/P Package Outline CXL5512M Unit : mm 8PIN SOP (PLASTIC) + 0.4 5.0 – 0.1 + 0.4 1.25 – 0.15 0.10 8 5 A 1 4 1.27 + 0.1 0.15 – 0.05 + 0.1 0.4 – 0.05 + 0.15 0.1 – 0.1 + 0.3 4.4 – 0.1 ± 0.12 M 0° to 10° DETAIL A PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L03 ∗SOP008-P-0225-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.1g CXL5512P 8PIN DIP (PLASTIC) 300mil 0.5 ± 0.2 8 5 7.62 + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 ∗DIP008-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT —9— 6.4 ± 0.4