CXL5515M

CXL5515M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5515M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for PAL chroma signals including the external lowpass filter. Features • Single 5V power supply • Low power consumption • Built-in peripheral circuit • Built-in tripling PLL circuit • Center bias mode Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD +6 • Operating temperature Topr –10 to +60 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD CXL5515M 350 CXL5515P 480 Recommended Operating Range (Ta = 25˚C) VDD 5V ± 5% Recommended Clock Conditions (Ta = 25˚C) • Input clock amplitude VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.) • Clock frequency fCLK 4.433619MHz • Input clock waveform Sine wave Block Diagram and Pin Configuration (Top View) CXL5515M 8 pin SOP (Plastic) CXL5515P 8 pin DIP (Plastic) Input Signal Amplitude VSIG 500mVp-p (Typ.), 575mVp-p (Max.) V °C °C Functions • 848-bit CCD register • Clock driver • Auto bias circuit • Input center bias circuit • Sample and hold circuit • Tripling PLL circuit • Inverted output Structure CMOS-CCD mW mW VDD 8 VCO OUT 7 VCO IN 6 CLK 5 PLL Auto-bias circuit Timing circuit Bias circuit CCD (848 bit) Output circuit (S/H 1 bit) Clock driver Bias circuit A Bias circuit B 1 IN 2 AB 3 OUT 4 VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94904-ST CXL5515M/P Pin Description Pin No. 1 2 3 4 5 6 7 8 IN AB OUT VSS CLK VCO IN VCO OUT VDD Symbol I/O I O O — I I O — Signal input Auto-bias DC output Signal output GND Clock input (fsc) VCO input VCO output (3fsc) 5V power supply >10KΩ 40 to 500Ω Description Impedance >10KΩ Electrical Characteristics (Ta = 25°C, VDD=5V, fCLK = 4.433619MHz, VCLK = 400mVp-p, sine wave) See “Electrical Characteristics Test Circuit”. Item Supply current Low frequency gain Symbol IDD GL Conditions — 200kHz 500mVp-p Sine wave SW conditions 1 a a 2 — b Min. 10 –2 Typ. 15 0 Max. 20 2 Unit NOTE mA dB 1 2 Frequency response Differential gain Differential phase S/H pulse coupling S/N ratio fR DG DP CP SN 200kHz ← 4.434MHz → b← c → 150mVp-p Sine wave 5-staircase wave (See Note 4.) 5-staircase wave (See Note 4.) No signal input 50% white video signal (See Note 6.) d d f e b c c a d –2.7 0 0 — 52 –1.7 3 3 — 56 2.7 5 5 350 — dB % degree mVp-p dB 3 4 4 5 6 –2– CXL5515M/P NOTE 1. This is the IC supply current value during clock and signal input. 2. GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. OUT pin output voltage [mVp-p] [dB] 500 [mVp-p] GL = 20 log 3. Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 4.434MHz sine wave is fed to the same, calculation is made according to the following formula. OUT pin output voltage (4.434MHz) [mVp-p] [dB] OUT pin output voltage (200kHz) [mVp-p] fR = 20 log 4. In Fig. below, the differential gain (DG) and the differential phase (DP), are tested with a vector scope when the 5-staircase wave is fed. 150mV 350mV 500mV 150mV 1H 64µs 5. Leakage of internal clock components and related high frequency component to the output signal, during no signal input, is tested. Test value [mVp-p] –3– CXL5515M/P 6. S/N ratio during a 50% white video signal input shown in Fig. below is tested at the video noise meter, in BPF 100kHz to 5MHz, Sub Carrier Trap mode. 175mV 325mV 150mV 1H 64µs CLOCK fSC (4.433619MHz) Sine wave 400mVp-p (Typ.) –4– Electrical Characteristics Test Circuit 2200p 5V 0.1µ 8 7 VCO OUT VCO IN CXL5515M/P a Oscilloscope IN +15V b 2.2k SW2 c Note1) LPF Note 2) d ×3 BPF Noise meter Spectrum analyzer 1 2 3 0.1µ 4 AB OUT VSS CLK VDD 6 5 0.1µ 6.8µ fsc (4.433619MHz) 400mVp-p Sine wave 200kHz 500mVp-p Sine wave a 200kHz 150mVp-p Sine wave b 4.434MHz 150mVp-p Sine wave c SW1 1µ –5– Note1) [dB] 0 –3 LPF frequency response [dB] 0 –3 Note 2) –50 6M 13.3M Frequency [Hz] –50 ×3 Vector scope 5-staircase wave d BPF frequency response 50% white video signal e f 50 200 6M 13.3M Frequency [Hz] CXL5515M/P Application Circuit 2200p 6.8µ fsc (4.433619MHz) 400mVp-p Sine wave 0.1µ 0.1µ 5 CLK 5V 8 7 VCO OUT CXL5515M/P IN 1 2 3 0.1µ 33k 470 4 5V AB OUT VSS VCO IN VDD 6 1µ 1µ –6– 56k 1k 1.8k 2SC403 3fsc OUT 2.2k 5V Transistor used NPN: 2SA403 Input LPF Output 2.2k When VCO OUT (7Pin) in use 7 Transistor used NPN: 2SC403 CXL5515M/P Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL5515M/P Example of Representative Characteristics Supply current vs. Supply voltage 20 1 Low frequency Gain vs. Supply voltage Low frequency Gain [dB] 5 Supply voltage [V] 5.25 Supply current [mA] 0 15 –1 10 4.75 –2 4.75 5 Supply voltage [V] 5.25 Frequency response vs. Supply voltage 0 10 Differential gain vs. Supply voltage 8 Frequency response [dB] –1 Differential gain [%] 5 Supply voltage [V] 5.25 6 4 –2 2 –3 4.75 0 4.75 5 Supply voltage [V] 5.25 Supply current vs. Ambient temperature 20 Low frequency Gain vs. Ambient temperature 1 18 Low frequency Gain [dB] 40 20 60 Ambient temperature [°C] 80 Supply current [mA] 0 16 14 –1 12 10 –20 0 –2 –20 0 20 40 60 Ambient temperature [°C] 80 –7– CXL5515M/P Frequency response vs. Ambient temperature 0 10 Differential gain vs. Ambient temperature 8 Frequency response [dB] –1 Differential gain [%] 0 20 40 60 Ambient temperature [°C] 80 6 4 –2 2 –3 –20 0 –20 0 20 40 60 Ambient temperature [°C] 80 Frequency response 2 0 –2 Gain [dB] –4 –6 –8 –10 10k 100k Frequency [Hz] 1M 10M –8– CXL5515M/P Package Outline CXL5515M Unit : mm 8PIN SOP (PLASTIC) + 0.4 5.0 – 0.1 + 0.4 1.25 – 0.15 0.10 8 5 A + 0.3 4.4 – 0.1 6.4 ± 0.4 + 0.1 0.15 – 0.05 + 0.15 0.1 – 0.1 0° to 10° DETAIL A 1 4 1.27 + 0.1 0.4 – 0.05 ± 0.12 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-8P-L03 ∗SOP008-P-0225-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.1g CXL5515P 8PIN DIP (PLASTIC) 300mil 0.5 ± 0.2 8 5 7.62 + 0.3 6.4 – 0.1 + 0.4 9.4 – 0.1 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.5g 1 2.54 4 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN 0.5 MIN + 0.4 3.7 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-8P-01 ∗DIP008-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT –9–