CXP5086

CXP5084/5086 CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP5084/5086 is a CMOS 4-bit microcomputer which consists of 4-bit CPU, ROM, RAM, I/O port, 8-bit timer, 8-bit timer/counter, 18-bit time base timer, 8-bit serial I/O, vector interruption, power on reset function and a liquid crystal displayer (LCD) controller/ driver. They are integrated into a single clip with the standby function etc. which are to be operated at low power consumption. Features • Instruction cycle 64 pin SDIP (Plastic) 64 pin QFP (Plastic) • • • • • • • • • • • • • • 3.8µs/4.19MHz 1.9µs/4.19MHz (High speed version) ROM capacity 4096 × 8 bits (CXP5084) 6144 × 8 bits (CXP5086) RAM capacity 400 × 4 bits (Including stack, display area) 32 general purpose I/O ports LCD controller/driver (Direct drive possible) — Optional specification of 24, 20 or 16 segment outputs — 1/2, 1/3, 1/4 duty selectable through program — 1/3 bias 2 external interruption input pins 8-bit/4-bit variable serial I/O 8-bit timer, 8-bit timer/event counter and 18-bit time base timer are independently controllable Arithmetic and logical operations possible between the entire RAM area, I/O area and the accumulator by means of memory mapped I/O Reference to the entire ROM area is possible with the table look-up instruction 2 types of power down modes: sleep and stop Power on reset circuit (Mask option) Available option of either crystal oscillation or CR oscillation (mask option) types for the oscillation circuit 64-pin plastic SDIP/QFP available Piggyback package (CXP5080) available Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E90377A7Z-PS CXP5084/5086 Block Diagram (Enables to specify the I/O with bit unit) (Enable to specify the I/O with port unit) 4 4 Port D (Combines use of mask with segment output, optional) 4 Port E 4 Port F Port A Port B Port C Register ALU Accumulator Program counter (13) Data memory 400 × 4 bits Stack Flag Program memory Timer (8) Timer/Counter (8) Serial I/O (8) 4096 × 8 bits (CXP5084) 6144 × 8 bits (CXP5086) Data memory Interrupt control Instruction control VL VLC1 VLC2 VLC3 LCD controller/driver Time base timer (18) EXTAL Port X 8 16 4 PX3/SI PX2/SOA PX1/SOB WP PX0/SC PY3/EC PY2/INT2 INT1 RST PY1 PY0 VDD VSS Port Y Clock contorl XTAL SEG16 SEG0 COM0 to to to SEG23 SEG15 COM3 (Common with Port E, Port F) (Common with serial I/O) –2– CXP5084/5086 Pin Assignment 1 (Top View) 64-pin SDIP Package VL XTAL EXTAL RST WP INT1 PY0 PY1 PY2/INT2 PY3/EC PX0/SC PX1/SOB PX2/SOA PX3/SI PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3 NC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD VLC3 VLC2 VLC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 SEG18/PF2 SEG19/PF3 SEG20/PE0 SEG21/PE1 SEG22/PE2 SEG23/PE3 Note) Do not make any connection to NC pin. –3– CXP5084/5086 Pin Assignment 2 (Top View) 64-pin QFP Package EXTAL COM0 COM1 64 63 62 61 60 59 58 57 56 55 54 53 52 PY0 PY1 PY2/INT2 PY3/EC PX0/SC PX1/SOB PX2/SOA PX3/SI PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 PB3 PA0 PA1 PA2 PA3 VSS NC SEG21/PE1 SEG20/PE0 SEG19/PF3 SEG23/PE3 Note) Do not make any connection to NC pin. –4– SEG22/PE2 SEG18/PF2 COM2 XTAL INT1 VLC3 VLC2 VLC1 RST VDD WP VL CXP5084/5086 Absolute Maximum Ratings Item Power supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VLC1, VLC2, VLC3 VIN VOUT IOH ∑IOH IOL ∑IOL Topr Tstg PD Symbol Ratings –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –5 –50 15 50 –20 to +75 –55 to +150 1000 600 (Ta = –20 to +75°C, VSS = 0V reference) Unit V V V V mA mA mA mA °C °C mW mW SDIP QFP General purpose port∗2 : per pin Entire pin total General purpose port∗2 : per pin Entire pin total Remarks ∗1 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. ∗2 The PE and PF are specified when PA to PD, PX0 to PX2, PY0, PY1 and mask option are selected as the port. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Power supply voltage Symbol VDD 3.5 VLC1, VLC2, VLC3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 5.5 V Min. 4.5 Max. 5.5 Unit V (VSS = 0V reference) Remarks Guaranteed range during operation Guaranteed data hold operation range during stop Liquid crystal power supply voltage∗1 LCD bias voltage VSS 0.7VDD 0.8VDD VDD – 0.4 0 0 –0.3 –20 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V °C Hysteresis input∗2 EXTAL pin∗3 Hysteresis input∗2 EXTAL pin∗3 ∗1 The optimum value is determined by the characteristics of the liquid crystal display element used. ∗2 They are the respective pins of INT1, WP, PX0, PX3, PY2, PY3 and RST. ∗3 Specified only during external clock input. –5– CXP5084/5086 Electrical Characteristics DC characteristics Item Symbol Pin PA to PF∗1, PX0 to PX2, PY0, PY1, VL (VOL only) RST (VOL only) Condition (Ta = –20 to +75°C, VSS = 0V reference) Min. 4.0 3.5 4.0 2.4 0.4 0.6 0.5 –0.5 RST∗5 PA to PF∗6, PX0 to PX2∗6, PX3∗8, PY0∗7, PY1∗7, PY2∗8, PY3∗8, INT1∗8, WP∗8, RST∗5 COM0 to COM3 SEG0 to SEG15 SEG16 to SEG23∗1 VDD = 5.5V, VIL = 0.4V –1.5 40 –40 –400 –2.0 VDD = 5.5V VI = 0, 5.5V Typ. Max. Unit V V V V V V µA µA µA mA VDD = 4.5V, IOH = –0.5mA∗2 VDD = 4.5V, IOH = –1.0mA∗2 VDD = 4.5V, IOH = –10µA∗3 VDD = 4.5V, IOH = –200µA∗3 VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA EXTAL∗4 VDD = 5.5V, VIH = 5.5V High level output voltage VOH Low level output voltage VOL IIH Input current IILE IILR IIL High impedance IIZ I/O leakage current Common output impedance Segment output impedance ±10 µA RCOM RSEG VDD = 5V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V VDD = 5.5V During external clock 1MHz operation Entire output pins open 3 5 1.3 (2)∗9 5 15 4 (6)∗9 kΩ kΩ IDD Current power supply IDDSP IDDS VDD mA Sleep mode Stop mode VLC1 to VLC3, COM0 to COM3, SEG0 to SEG15, Clock 1MHz SEG16 to SEG23∗1, 0V for no measured pins Other pins than VDD, VSS 0.4 1.2 (0.5)∗9 (2)∗9 10 mA µA Input capacitance CIN 10 20 pF ∗1 PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when the combined pins are selected as the segment output. ∗2 It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and PY1 are when the inverter output circuit is selected. ∗3 It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance. ∗4 It is when the crystal or ceramic oscillation circuit is selected. ∗5 The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. ∗6 The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during the 3-state output circuit or standby is selected at high impedance. ∗7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and specify the leakage current when the port state during standby is selected at high impedance. ∗8 The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current. ∗9 The value in parentheses shows the specification of the current power supply of the high speed version. –6– CXP5084/5086 AC characteristics (1) Clock timing Item System clock frequency System clock input pulse width Symbol fc (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Pin XTAL EXTAL EXTAL EXTAL EC EC Condition Fig. 1., Fig. 2. Fig. 1., Fig. 2.∗1 External clock drive Fig. 1., Fig. 2.∗1 External clock drive Fig. 3. Fig. 3. Min. 1 90 200 Max. Unit 5 MHz ns ns µs 20 ms tXL tXH System clock input rising and falling tCR times tCF tEL Event count clock input pulse width tEH Event count clock input rising and tER falling times tEF tsys∗2 + 0.05 ∗1 The external clock in Fig. 2. is specified only when the option is selected for crystal or ceramic oscillation. ∗2 In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc Note) When adjusting the frequency accurately, there may be cases in which they differ from Fig. 2. 1/fc EXTAL VDD – 0.4V 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation CR oscillation External clock∗1 EXTAL XTAL EXTAL R XTAL EXTAL XTAL OPEN C1 C2 C Fig. 2. Clock applying condition EC 0.8VDD 0.2V tEH tEF tEL tER Fig. 3. Event count clock timing –7– CXP5084/5086 (2) Serial transfer Item Serial transfer clock (SC) cycle time Serial transfer clock (SC) high and low level widths Serial data input setup time (against SC ↑) Serial data input hold time (against SC ↑) High data∗3 output delay time from the SC falling time Symbol Pin SC (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition Input mode Output mode Input mode Output mode∗1 Output mode∗2 SC input mode SC output mode SI SOA SOB SOA SOB SOA SOB SC input mode SC output mode Min. Max. Unit µs µs µs µs µs µs µs µs µs tKCY tKH tKL tSIK tKSI SC tsys/4 + 1.42 tsys tsys/8 + 0.7 tsys/2 – 0.1 tsys/2 – 1.6 0.1 0.2 SI tsys/8 + 0.5 0.1 tKSOA tKSOB High data∗4 output delay time tKSOA from the SC falling time tKSOB tKSOA Low data output delay time from the SC falling time tKSOB tsys/8 + 0.5 tsys/8 + 1.6 tsys/8 + 0.5 µs µs µs ∗1 It is specified when SC pin is selected to the 3-state output by the mask option. ∗2 It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. ∗3 It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option. ∗4 It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option. Note 1) In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc Note 2) The load of data output delay time is 50pF + 1TTL. –8– CXP5084/5086 tKCY tKL tKH SC 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSOA tKSOB 0.8VDD SOA SOB 0.2VDD Output data Fig. 4. Serial transfer timing (3) Others Item External interruption high and low level widths Reset input low level width Wake-up input high level width Symbol Pin INT1 INT2 RST WP (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition During edge detection mode Min. Max. Unit µs µs µs ns µs tI1H, tI1L tI2H, tI2L tRSL tWPH tsys + 0.05 tsys + 0.05 2tsys 500 Stop mode Sleep mode tsys + 0.05 Note) In the standard version, tsys = 16/fc In the high speed version, tsys = 8/fc –9– CXP5084/5086 tI1L tI1H 0.8VDD INT1 (Rising edge) 0.2VDD tI1H 0.8VDD INT1 (Falling edge) tI1L 0.2VDD tI2L tI2H 0.8VDD INT2 0.2VDD Fig. 5. Interruption input timing tRSL RST 0.2VDD Fig. 6. Reset input timing tWPH 0.8VDD WP Fig. 7. Wake-up input timing Power on reset∗ Item Power supply rising time Symbol Pin VDD (Ta = –20 to +75°C, VSS = 0V reference) Condition Power on reset Repectitive power on reset Min. 0.05 1 Max. 50 Unit ms ms tR Power supply cut-off time tOFF ∗ Specifies only when power on reset function is selected. VDD 4.5V 0.2V 0.2V tR Raise the power supply smoothly. tOFF Fig. 8. Power on reset – 10 – CXP5084/5086 Package Outline Unit: mm 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 33 19.05 + 0.3 17.1 – 0.1 + 0.1 0.05 0.25 – 0° to 15° 32 1.778 0.5 ± 0.1 0.9 ± 0.15 1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 + 0.35 2.75 – 0.15 0.2 M 0° to10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g – 11 – 0.8 ± 0.2 19 16.3