CXP740010

CXP740056/740096/740010 CMOS 8-bit Single Chip Microcomputer Description The CXP740056/740096/740010 is a CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, capture timer/counter, remote control receive circuit, PWM output, and the like besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP740056/740096/740010 also provides the sleep/stop functions that enables lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (211 instructions) which covers various types of data. — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 167ns at 24MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (2.7 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Incorporated ROM capacity 56K bytes (CXP740056) 96K bytes (CXP740096) 120K bytes (CXP740010) • Incorporated RAM capacity 4096 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time 10.3µs at 24MHz) — Serial interface Srart-stop synchronization (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels 8-bit clock syncronization (MSB/LSB first selectable), 1 channel — Timer 8-bit timer 2 channels, 8-bit timer/counter 2 channels, 19-bit time-base timer, 16-bit capture timer/counter 32kHz timer/counter — Remote control receive circuit Noise elimination circuit 8-bit pulse measuring counter, 6-stage FIFO — PWM output 12 bits, 2 channels • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP • Piggy/evaluation chip CXP740000 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98406-PS Block Diagram AVSS NMI INT0 INT1 INT2 INT3 INT4 TEX TX EXTAL XTAL RST VDD VSS AVDD AVREF AN0 to AN11 8 SPC 700αII CPU CORE 8 CLOCK GENERATOR/ SYSTEM CONTROL 12 A/D CONVERTER PA0 to PA7 RxD TxD UART RECEIVER UART TRANSMITTER PB0 to PB7 UART BAUD RATE GENERATOR PWM0 PWM1 FIFO ROM 56K/96K/120K BYTES RAM 4096 BYTES 12-BIT PWM GENERATOR 0 8 PC0 to PC7 12-BIT PWM GENERATOR 1 INTERRUPT CONTROLLER RMC REMOCON IN 8 PD0 to PD7 2 6 CS0 SI0 SO0 SCK0 SERIAL INTERFACE UNIT (CH0) BUFFER RAM PE0 to PE1 PE2 to PE7 8 PF0 to PF7 PORT K ADJ PK3 to PK7 5 PK1 to PK2 2 PORT J TO2 CINT EC2 2 16-BIT CAPTURE TIMER/COUNTER 4 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A –2– PRESCALER/ TIME-BASE TIMER 2 2 CS1 SI1 SO1 SCK1 SERIAL INTERFACE UNIT (CH1) BUFFER RAM SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) 32kHz TIMER-COUNTER 8 PG0 to PG7 EC0 8-BIT TIMER/COUNTER 0 TO0 8-BIT TIMER 1 8 PH0 to PH7 EC1 8-BIT TIMER/COUNTER 2 TO1 8-BIT TIMER 3 7 PI1 to PI7 CXP740056/740096/740010 8 PJ0 to PJ7 CXP740056/740096/740010 Pin Assignment (Top View) 100-pin QFP package PI4/INT1/CS1 PI3/TO0/ADJ PI1/RMC PA3 PA6 PA7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PC5 PC4 PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 VDD EXTAL RST PH6 PH2 PI2/NMI PA5 PF7/AN11 PF6/AN10 PK7/TO1 PK6/CS0 PK5/SI0 PH7 PH5 PH4 PH3 PH0 PH1 VSS PK4/SO0 Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. –3– PK3/SCK0 PF5/AN9 XTAL PI5/SCK1 PC6 PA1 PA2 NC PK1/TX PA4 PK2/TEX PC7 PA0 VSS CXP740056/740096/740010 Pin Assignment (Top View) 100-pin LQFP package PI4/INT1/CS1 PI3/TO0/ADJ PI5/SCK1 PI2/NMI PA1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF PD1 PH4 PH0 PK3/SCK0 PK4/SO0 PF6/AN10 PK6/CS0 PH3 PK7/TO1 XTAL PF7/AN11 PF5/AN9 EXTAL PK5/SI0 Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. –4– PF4/AN8 AVSS PD0 PH5 PH2 RST PH7 PD2 PH6 PH1 VSS PE0/INT0 PK2/TEX PI1/RMC PK1/TX PI6/SO1 PC4 PC7 PC5 PA2 PC6 PA5 PA0 PA3 PA4 PA6 PA7 VDD VSS NC PI7/SI1 CXP740056/740096/740010 Pin Description Symbol I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) PA0 to PA7 I/O PB0 to PB3 PB4/TO2 PB5/SCK2 PB6/SO2 PB7/SI2 I/O I/O/Output I/O/I/O I/O/Output I/O/Input 16-bit timer/counter rectangular wave output. Serial clock I/O (CH2). Serial data output (CH2). Serial data input (CH2). PC0 to PC7 I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins) (Port F) 8-bit I/O port. PF4 to PF7 can be set in a unit of single bits as standby release inputs. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) External interrupt inputs. (2 pins) 12-bit PWM outputs. (2 pins) PD0 to PD7 I/O PE0/INT0 PE1/INT1 PE2/PWM0 PE3/PWM1 PE4 to PE7 Input/Input Input/Input Output/Output Output/Output Output PF0/AN4 to PF7/AN11 I/O Analog inputs to A/D converter. (8 pins) –5– CXP740056/740096/740010 Symbol PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) Description UART transmission data output. UART reception data input. External event input for 8-bit timer/counter 0. External event input for 8-bit timer/counter 2. External event input for 16-bit timer/counter. External interrupt inputs. (2 pins) External capture input to 16-bit timer/counter. (Port H) 8-bit I/O port. Operated as N-ch open drain output for medium voltage drive (12V) and large current (12mA). (8 pins) Remote control receiver circuit input. Non-maskable interrupt input. (Port I) 7-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (7 pins) Output for the 8-bit timer/counter 1 rectanguler waves and 32-kHz oscillation frequency demultiplication. External interrupt input. Chip select input for serial interface (CH1). PH0 to PH7 Output PI1/RMC PI2/NMI PI3/TO0/ ADJ PI4/INT1/ CS1 PI5/SCK1 PI6/SO1 PI7/SI1 I/O/Input I/O/Input I/O/Output/ Output I/O/Input/ Input I/O/I/O I/O/Output I/O/Input Serial clock I/O (CH1). Serial data output (CH1). Serial data input (CH1). PJ0 to PJ7 I/O (Port J) 8-bit I/O port. I/O can be set in a unit of single bits. Standby release input can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) Crystal connectors for 32-kHz timer/counter clock oscillation circuit. (Port K) 7-bit port. lower 2 bits are for For usage as event count, connect clock input; upper 5 bits are for I/O. oscillation source to TEX, and leave TX open. I/O can be set in a unit of single bits. Serial clock I/O (CH0). For PK3 to PK7, incorporation of pull-up resistor can be set Serial data output (CH0). through the program in a unit Serial data input (CH0). of single bits. Chip select input for serial inteface (CH0). (7 pins) 8-bit timer/counter 3 rectangular wave output. PK1/TX PK2/TEX PK3/SCK0 PK4/SO0 PK5/SI0 PK6/CS0 PK7/TO1 Input Input/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Output –6– CXP740056/740096/740010 Symbol AN0 to AN3 EXTAL XTAL RST NC AVDD AVREF AVSS VDD VSS Input Input Input Input I/O Analog inputs to A/D converter. (4 pins) Description Connects a crystal for system clock oscillation. When a clock is supplied externally, input it to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. Not connected. Leave this pin open for normal operation. Positive power supply of A/D converter. Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. GND. Connect both VSS pins to GND. –7– CXP740056/740096/740010 I/O Circuit Format for Pins Pin Port A Port B Port C PA0 to PA7 PB0 PB2 PC0 to PC7 Pull-up resistor “0” after a reset Ports A, B, C data ∗ Circuit format After a reset Ports A, B, C direction “0” after a reset Internal data bus RD (Ports A, B, C) ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) IP Hi-Z 18 pins Port B Pull-up resistor “0” after a reset Port B data ∗ PB1 PB3 Port B direction “0” after a reset Internal data bus RD (Port B) Schmitt input IP Hi-Z 2 pins Port I Port K Pull-up resistor “0” after a reset TO0/ADJ, TO1 Ports I, K function select ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) ∗ PB4/TO2 PI3/TO0/ADJ PK7/TO1 “0” after a reset Ports I, K data Ports I, K direction IP “0” after a reset Internal data bus RD (Ports B, I, K) ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) Hi-Z 3 pins –8– CXP740056/740096/740010 Pin Port B Port I Port K Pull-up resistor “0” after a reset Output buffer capability “0” after a reset Output enable Circuit format After a reset ∗ PB5/SCK2 PI5/SCK1 PK3/SCK0 SCK2, SCK1, SCK0 Ports B, I, K function select “0” after a reset Ports B, I, K data Ports B, I, K direction “0” after a reset Internal data bus RD (Ports B, I, K) SCK2, SCK1, SCK0 ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) Schmitt input IP Hi-Z 3 pins Port B Port G Port I Port K Pull-up resistor “0” after a reset Output buffer capability ∗ PB6/SO2 PG0/TxD PI6/SO1 PK4/SO0 “0” after a reset Output enable TO2, SO2, TxD, SO1, SO0 Hi-Z Ports B, G, I, K function select “0” after a reset Ports B, G, I, K data Ports B, G, I, K direction “0” after a reset Internal data bus RD (Ports B, G, I, K) ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) IP 4 pins –9– CXP740056/740096/740010 Pin Port B Port G PB7/SI2 PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT PI1/RMC PI2/NMI PI4/INT1/CS1 PI7/SI1 PK5/SI0 PK6/CS0 Port I Port K Pull-up resistor “0” after a reset Circuit format After a reset ∗ Ports B, G, I, K data Ports B, G, I, K direction “0” after a reset Internal data bus RD (Ports B, G, I, K) Schmitt input IP Hi-Z SI2, RxD, EC0, EC1, EC2, INT3, INT4, CINT, RMC, MNI, INT1/CS1, SI1, SI0, CS0 ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) 14 pins Port D Pull-up resistor “0” after a reset Port D data ∗2 PD0 to PD7 Internal data bus Port D direction ∗1 IP Hi-Z RD (Port D) 8 pins Port E Schmitt input ∗1 Large current 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 2.7 to 3.3V) ∗2 Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) PE0/INT0 PE1/INT2 IP INT0, INT2 Internal data bus Hi-Z 2 pins RD (Port E) – 10 – CXP740056/740096/740010 Pin Port E PWM0, PWM1 Circuit format After a reset PE2/PWM0 PE3/PWM1 Port E function select “0” after a reset Port E data Hi-Z by writing to Port E data register or Port E function select register → Output active Internal data bus Hi-Z 2 pins Port E RD (Port E) Port E data PE4 PE5 Internal data bus RD (Port E) Hi-Z 2 pins Port E Port E data “1” after a reset Internal data bus Hi-Z by writing to Port E data register → Output active PE6 High level 1 pin Port E RD (Port E) Internal reset signal ∗ PE7 Port E data “1” after a reset Internal data bus RD (Port E) ∗ Pull-up transistors approx. 150kΩ (VDD = 4.5 to 5.5V) approx. 200kΩ (VDD = 2.7 to 3.3V) )) Hi-Z "H" level "H"level at ON resistance of pull-up transistor during a reset. 1 pin AN0 to AN3 IP Input multiplexer A/D converter 4 pins – 11 – CXP740056/740096/740010 Pin Port F Pull-up resistor “0” after a reset Port F data Circuit format After a reset ∗ PF0/AN4 to PF3/AN7 Internal data bus Port F direction “0” after a reset IP Hi-Z RD (Port F) Port F function select “0” after a reset A/D converter ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) Input multiplexer 4 pins Port F Pull-up resistor “0” after a reset Port F data ∗ Port F direction “0” after a reset Internal data bus IP PF4/AN8 to PF7/AN11 RD (Port F) Port F function select “0” after a reset Standby release Edge detection Hi-Z Polarity select “0” after a reset Input multiplexer A/D converter ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) 4 pins – 12 – CXP740056/740096/740010 Pin Port H Circuit format After a reset Port H data ∗ PH0 to PH7 “1” after a reset Internal data bus RD (Port H) ∗ High tension proof 12V Large current 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 2.7 to 3.3V) Hi-Z 8 pins Port J Pull-up resistor “0” after a reset Port J data ∗ Port J direction PJ0 to PJ7 Internal data bus “0” after a reset IP Hi-Z RD (PortJ) Standby release Edge detection Polarity select “0” after a reset 8 pins Port K ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 150kΩ (VDD = 2.7 to 3.3V) TEX oscillation circuit control “1” after a reset Internal data bus RD (Port K) PK1/TX PK2/TEX Internal data bus RD (Port K) Schmitt input PK2/TEX IP IP Clock input Oscillation stop port input 2 pins PK1/TX – 13 – CXP740056/740096/740010 Pin Circuit format After a reset EXTAL XTAL EXTAL IP IP • Diagram shows circuit configuration during oscillation. • When program stops the oscillation, the feedback registor disconnects, and XTAL is driven at "H" level. Oscillation 2 pins XTAL Pull-up resistor RST Mask option OP IP Schmitt input "L" level (during a reset) 1 pin – 14 – CXP740056/740096/740010 Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS AVREF Input voltagte Output voltage High level output current VIN VOUT IOH Rating –0.3 to +7.0 AVSS to +7.0∗1 –0.3 to +0.3 AVSS to +7.0 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –5 –50 15 20 100 –20 to +75 –55 to +150 600 Allowable power dissipation PD 380 Unit V V V V V V mA mA mA mA mA °C °C mW QFP package LQFP package (Vss = 0V reference) Remarks Output (value per pin) Total for all output pins All pins excluding large current outputs (value per pin) Large current outputs (value per pin) ∗3 Total for all output pins High level total output current ∑IOH Low level output current Low level total output current Operating temperature Storage temperature IOL IOLC ∑IOL Topr Tstg ∗1 AVDD and VDD must be set to the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 The large current output pins are Port D and H (PD, PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 15 – CXP740056/740096/740010 Recommended Operating Conditions Item Symbol Min. 4.5 2.7 Supply voltage VDD 2.7 2.7 2.5 Analog voltage AVDD VIH High level input voltage VIHS VIHEX 2.7 0.7VDD 0.8VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V V V V °C (Vss = 0V reference) Remarks fc = 24MHz or less Guaranteed operation range for 1/2 and 1/4 fc = 12MHz or less frequency dividing clock. Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed operation range for TEX Guaranteed data hold operation range during stop mode ∗1 ∗2, ∗6 ∗2, ∗7 Hysteresis input∗3 EXTAL pin∗4, ∗6, TEX pin∗5, ∗6 EXTAL pin∗4, ∗7, TEX pin∗5, ∗7 ∗2, ∗6 ∗2, ∗7 Hysteresis input∗3 EXTAL pin∗4, ∗6, TEX pin∗5, ∗6 EXTAL pin∗4, ∗7, TEX pin∗5, ∗7 VDD – 0.4 VDD + 0.3 VDD – 0.2 VDD + 0.2 VIL Low level input voltage VILS VILEX Operating temperature Topr 0 0 0 –0.3 –0.3 –20 0.3VDD 0.2VDD 0.2VDD 0.4 0.2 +75 ∗1 AVDD and VDD must be set to the same voltage. ∗2 Normal input port (PA, PB0, PB2, PB4, PB6, PC, PD, PF, PG0, PI3, PI6, PJ, PK1, PK2, PK4, PK7) ∗3 RST, PB1, PB3, PB5/SCK2, PB7/SI2, PE0/INT0, PE1/INT2, PG1/RxD, PG2/EC0, PG3/EC1, PG4/EC2, PG5/INT3, PG6/INT4, PG7/CINT, PI1/RMC, PI2/NMI, PI4/INT1/CS1, PI5/SCK1, PI7/SI1, PK3/SCK0, PK5/SI0, PK6/CS0 ∗4 Specifies only when the external clock is input. ∗5 Specifies only when the external event count is input. ∗6 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). ∗7 This case applies to the range of 2.7 to 5.5V supply voltage (VDD). – 16 – CXP740056/740096/740010 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item Symbol Pins PA to PD, PE2 to PE7, PF to PG, PI to PJ, PK3 to PK7 PB5, PB6∗1, PG0∗1, PI5, PI6∗1, PK3, PK4∗1 Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOH = –1.0mA VDD = 4.5V, IOH = –2.4mA (Ta = –20 to +75°C, VSS = 0V reference) Min. 4.0 3.5 4.0 3.5 0.4 0.6 1.5 0.5 –0.5 0.1 –0.1 –1.5 40 –40 10 –10 –400 –45 VDD = 4.5V, VIL = 4.0V –2.78 Typ. Max. Unit V High level VOH output voltage V V V V Low level output voltage VOL PA to PD, VDD = 4.5V, IOL = 1.8mA PE2 to PE7, PF to PG, PI to PJ, VDD = 4.5V, IOL = 3.6mA PK3 to PK7 PD, PH VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V EXTAL VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V V V µA µA µA µA µA µA µA IIHE IILE IIHT Input current IILT IILR IIL TEX RST∗2 PA to PD∗3, PF to PG∗3, PI to PK∗3 PA to PD∗3, PF to PG∗3, PI to PK∗3, PE, AN0 to AN3 RST∗2 I/O leakage current IIZ VDD = 5.5V VI = 0, 5.5V ±10 µA Open drain output leakage current LLOH (N-ch Tr off state) PH VDD = 5.5V VOH = 12V 50 µA – 17 – CXP740056/740096/740010 Item Symbol IDD1 Pins Conditions 24MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5V ± 0.5V Min. Typ. 27 Max. 47 Unit mA IDDS1 Sleep mode 1.0 VDD = 5V ± 0.5V 32kHz crystal oscillation (C1 = C2 = 47pF) VDD VDD = 3V ± 0.3V Sleep mode 5.0 mA Supply current∗4 IDD2 30 75 µA IDDS2 VDD = 3V ± 0.3V Stop mode (Termination of EXTAL and TEX pins crystal oscillation) VDD = 5V ± 0.5V PA to PD, PE0 to PE1, PF to PG, Clock 1MHz PI to PK, 0V for all pins excluding measured AN0 to AN3, pins EXTAL, RST 12 40 µA IDDS3 10 µA Input capacity CIN 10 20 pF ∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0= "1, 1, 1, 1, 1") are ON. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. ∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. ∗4 When all pins are open. – 18 – CXP740056/740096/740010 Electrical Characteristics DC Characteristics (VDD = 2.7 to 3.3V) Item Symbol Pins PA to PD, PE2 to PE7, PF to PG, PI to PJ, PK3 to PK7 PB5, PB6∗1, PG0∗1, PI5, PI6∗1, PK3, PK4∗1 Conditions VDD = 2.7V, IOH = –0.12mA VDD = 2.7V, IOH = –0.45mA VDD = 2.7V, IOH = –0.24mA VDD = 2.7V, IOH = –0.9mA (Ta = –20 to +75°C, VSS = 0V reference) Min. 2.5 2.1 2.5 2.1 0.25 0.4 0.9 0.3 –0.3 0.1 –0.1 –0.9 20 –20 10 –10 –200 –20 VDD = 3.3V, VIL = 2.7V –1.0 Typ. Max. Unit V High level VOH output voltage V V V V V V µA µA µA µA µA µA µA Low level output voltage VOL PA to PD, VDD = 2.7V, IOL = 1.0mA PE2 to PE7, PF to PG, PI to PJ, VDD = 2.7V, IOL = 1.4mA PK3 to PK7 PD, PH VDD = 2.7V, IOL = 4.5mA VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL = 0.3V VDD = 3.3V, VIL = 3.3V VDD = 3.3V, VIL = 0.4V RST∗2 PA to PD∗3, PF to PG∗3, PI to PK∗3 PA to PD∗3, PF to PG∗3, PI to PK∗3, PE, AN0 to AN3 RST∗2 VDD = 3.3V, VIL = 0.3V IIHE IILE IIHT Input current IILT IILR IIL TEX EXTAL I/O leakage current IIZ VDD = 3.3V VI = 0, 3.3V ±10 µA Open drain output leakage current LLOH (N-ch Tr off state) PH VDD = 3.3V VOH = 12V 50 µA – 19 – CXP740056/740096/740010 Item Symbol IDD1 Pins Conditions 12MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.0V ± 0.3V∗3 Sleep mode Min. Typ. 8 Max. 20 Unit mA Supply current∗4 IDDS1 VDD 0.3 VDD = 3.0V ± 0.3V Stop mode (Termination of EXTAL and TEX pins crystal oscillation) VDD = 3.0V ± 0.3V 1.5 mA IDDS3 10 µA Input capacity CIN PA to PD, PE0 to PE1, PF to PG, Clock 1MHz PI to PK, 0V for all pins excluding measured AN0 to AN3, pins EXTAL, RST 10 20 pF ∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0 = "1, 1, 1, 1, 1") are ON. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. ∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. ∗4 When all pins are open. – 20 – CXP740056/740096/740010 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock pulse width Event count input clock rise time, fall time Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 VDD = 4.5 to 5.5V Min. 1 1 28 37.5 200 ns ns 20 ms Typ. Max. 24 12 ns Unit MHz tXL, tXH tCR, tCF tEH, tEL tER, tEF fC Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 tsys + 50∗1 32.768 kHz tTL, tTH tTR, tTF 10 20 µs ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 000FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) 1/fc EXTAL VDD – 0.4V (VDD = 4.5 to 5.5V) VDD – 0.3V 0.4V (VDD = 4.5 to 5.5V) 0.3V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condetions crystal oscillation EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HC04 C1 C2 Fig. 2. Clock applied conditions TEX EC0 EC1 EC2 tEH tTH tEF tTF tEL tTL tER tTR 0.8VDD 0.2VDD Fig. 3. Event count clock timing – 21 – CXP740056/740096/740010 (2) Serial transfer (CH0, CH1) Item CS↓ → SCK delay time CS↑ → SCK floating delay time CS↓ → SO delay time CS↑ → SO floating delay time CS High level width SCK cycle time SCK High and Low level width SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK0 SCK1 SCK0 SCK1 SO0 SO1 SO0 SO1 CS0 CS1 SCK0 SCK1 SCK0 SCK1 SI0 SI1 SI0 SI1 SO0 SO1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 8000/fc tsys + 100 4000/fc – 50 –tsys + 100 200 2tsys + 200 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1 and SO1 for CH1, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. Note 4) This case applies that Port I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4 and 3 = "0, 0, 0, 0") is OFF. – 22 – CXP740056/740096/740010 Serial transfer (CH0, CH1) Item CS↓ → SCK delay time CS↑ → SCK floating delay time CS↓ → SO delay time CS↑ → SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK0 SCK1 SCK0 SCK1 SO0 SO1 SO0 SO1 CS0 CS1 SCK0 SCK1 SCK0 SCK1 SI0 SI1 SI0 SI1 SO0 SO1 (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. 1.5tsys + 250 1.5tsys + 250 1.5tsys + 250 1.5tsys + 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 8000/fc tsys + 100 4000/fc – 100 –tsys + 100 200 2tsys + 200 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1 and SO1 for CH1, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. Note 4) This case applies that Port G/I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4 and 3 = "1, 1, 1, 1") is ON. – 23 – CXP740056/740096/740010 tWHCS CS0 CS1 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 SCK1 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 SI1 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 SO1 Output data 0.2VDD Fig. 4. Serial transfer CH0, CH1 timing – 24 – CXP740056/740096/740010 Serial transfer (CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK2 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK2 SI2 SI2 SO2 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively. Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL. Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = “0, 0”) is OFF. Serial transfer (CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK2 (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 100 100 200 200 100 250 125 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK2 SI2 SI2 SO2 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively. Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF. Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = “1, 1”) is ON. – 25 – CXP740056/740096/740010 tKCY tKL tKH 0.8VDD SCK2 0.2VDD tSIK tKSI 0.8VDD SI2 Input data 0.2VDD tKSO 0.8VDD SO2 0.2VDD Output data Fig. 5. Serial transfer CH2 timing – 26 – CXP740056/740096/740010 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity errror Absolute error Conversion time Sampling time Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pin Conditions Min. Typ. Max. 8 ±2 ±3 31/fADC∗3, ∗4 10/fADC∗3, ∗4 AVREF AN0 to AN11 Operation mode AVREF Sleep mode Stop mode 32kHz operation mode VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 0 0.6 1.0 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS (Ta = –20 to +75°C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity errror Absolute error Conversion time Sampling time Ta = 25°C VDD = AVDD = AVREF = 3.0V VSS = AVSS = 0V Symbol Pin Conditions Min. Typ. Max. 8 ±2 ±3 31/fADC∗3, ∗4 10/fADC∗3, ∗4 AVREF AN0 to AN11 Operation mode AVREF Sleep mode Stop mode 32kHz operation mode VDD = AVDD = 2.7 to 3.3V AVDD – 0.3 0 0.4 0.7 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS FFh FEh Linearity error 01h 00h VZT Analog input VFT ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 000F9h). PS3 selected fADC = fc/4 PS4 selected fADC = fc/8 However, when PS3 is selected, fc is 12MHz or less. ∗4 Sub clock operated tCONV = 34/fTEX tSAMP = 10/fTEX Fig. 6. Definition of A/D converter terms – 27 – Digital conversion value CXP740056/740096/740010 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference) Item Symbol Pin INT0 INT1 INT2 INT3 INT4 NMI RST tIH Conditions Min. Max. Unit External interruption High and Low level widths tIH tIL 1 µs Reset input Low level width tRSL 32/fc µs tIL INT0 INT1 INT2 INT3 INT4 NMI (NMI is specified only for the falling edge) 0.8VDD 0.2VDD tIL tIH Fig. 7. Interruption input timing tRSL RST 0.2VDD Fig. 8. RST input timing – 28 – CXP740056/740096/740010 Appendix Fig. 9. Recommended oscillation circuit (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL Rd EXTAL XTAL Rd C1 TEX TX Rd C2 C1 C2 C1 C2 Manufacturer Model CSA10.0MTZ CSA12.0MTZ fc (MHz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 C1 (pF) 30 5 30 5 18 12 10 10 5 Open 30 18 C2 (pF) 30 5 30 5 18 12 10 10 5 Open 33 18 Rd (Ω) Circuit example Remarks (i) 0 ∗1 (ii) MURATA MFG CO., LTD. CSA16.00MXZ040 CST10.0MTW∗ CST12.0MTW∗ CST16.00MXW0C1∗ RIVER ELETEC CO., LTD. HC-49/U03 12.0 16.0 8.0 330 ∗1 (i) 0 ∗1 KINSEKI LTD. HC-49/U (-S) 12.0 16.0 P3 Seiko Instruments Inc. VTC-200 SP-T 32.768kHz 32.768kHz 120k 330k (iii) (iii) CL = 12.5pF ∗ Indicates types with on-chip grounding capacitor (C1, C2). ∗1 XTAL series resistor (Rd = 500Ω or less) is hard to affect noise by ESD. – 29 – CXP740056/740096/740010 Characteristics Curve IDD vs. VDD (fc = 24MHz, Ta = 25°C, Typical) 1/2 dividing mode 20.0 10.0 1/16 dividing mode 1/4 dividing mode 30 IDD vs. fc (VDD = 5.0V, Ta = 25°C, Typical) IDD – Supply current [mA] Sleep mode 1.0 0.5 IDD – Supply current [mA] 5.0 1/2 dividing mode 20 1/4 dividing mode 0.1 (100µA) 0.05 (50µA) 32kHz operation mode 32kHz sleep mode 10 1/16 dividing mode 0.01 (10µA) 2 3 4 5 6 Sleep mode 0 10 20 24 fc – System clock [MHz] 0 VDD – Supply voltage [V] IDD vs. VDD (fc = 12MHz, Ta = 25°C, Typical) 1/2 dividing mode 1/4 dividing mode 30 1/16 dividing mode Sleep mode 1.0 0.5 IDD vs. fc (VDD = 3.0V, Ta = 25°C, Typical) 20.0 10.0 IDD – Supply current [mA] 5.0 IDD – Supply current [mA] 20 1/2 dividing mode 0.1 (100µA) 0.05 (50µA) 10 1/4 dividing mode 0.01 (10µA) 2 3 4 5 6 0 0 1/16 dividing mode Sleep mode 10 20 24 fc – System clock [MHz] VDD – Supply voltage [V] – 30 – CXP740056/740096/740010 Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 80 51 + 0.1 0.15 – 0.05 81 50 + 0.4 14.0 – 0.1 17.9 ± 0.4 15.8 ± 0.4 A 100 31 1 0.65 + 0.15 0.3 – 0.1 30 0.13 M + 0.35 2.75 – 0.15 + 0.2 0.1 – 0.05 0.15 DETAIL A 0.8 ± 0.2 0° to 10° (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 + 0.08 0.18 – 0.03 25 26 (0.22) 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.8g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 LQFP100-P-1414 – 31 – 0.5 ± 0.2 A (15.0)