CXP750097

CXP750096/750010 CXP750097/750011 CMOS 8-bit Single Chip Microcomputer Description The CXP750096/750010, CXP750097/750011 are the CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/ counter, time-base timer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter, watchdog timer, 32kHz timer/ counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP750096/750010, CXP750097/750011 also provide a sleep function that enables to lower the power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) 52 pin SDIP (Plastic) Features • A wide instruction set (213 instructions) which covers various types of data – 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 167ns at 24MHz operation 122µs at 32kHz operation • Incorporated ROM 96K bytes (CXP750096/750097) 120K bytes (CXP750010/750011) • Incorporated RAM 2496 bytes (Excludes VRAM for on-screen display) • Peripheral functions Structure – A/D converter 8-bit 6-channel successive approximation method Silicon gate CMOS IC (Conversion time of 3.25µs at 16MHz) – Serial interface 8-bit clock sync type, 1 channel – Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32 kHz timer/counter – On-screen display (OSD) function 24 × 32 dots, 512 character types, 15 character colors, 2 lines × 32 characters, frame background 8 colors/ half blanking, background on full screen 15 colors/ half blanking edging/ shadowing/ rounding for every line, background with shadow for every character, double scanning, sprite OSD, 24 × 32 dots, 1 screen, 8 colors for every dot – I2C bus interface – PWM output 8 bits, 8 channels 14 bits, 1 channel – Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO – HSYNC counter 2 channels – Watchdog timer • Interruption 13 factors, 13 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP, 52-pin plastic SDIP • Piggyback/evaluator CXP750000 64-pin ceramic PQFP/PSDIP (Supports custom font) Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98767-PS EXTAL XTAL RST VDD VSS INT0 INT1 INT2 Block Diagram TEX SPC700 CPU CORE 8 PA0 to PA7 CLOCK GENERATOR /SYSTEM CONTROL PORT B RMC ROM 96K/120K BYTES 8 RAM 2496 BYTES REMOCON FIFO PORT A AN0 to AN5 6 A/D CONVERTER 6CH TX PB0 to PB7 PORT C SI SO SCK 2 SERIAL INTERFACE UNIT INTERRUPT CONTROLLER 6 2 PC0 to PC5∗ PC6, PC7∗ EC 8-BIT TIMER/ COUNTER 0 PORT E XLC EXLC R G B I YS YM HSYNC VSYNC 2 PRESCALER/ TIME-BASE TIMER WATCHDOG TIMER 32kHz TIMER/COUNTER PORT D TO 8-BIT TIMER 1 8 PD0 to PD7 PORT F 2 I2C BUS INTERFACE UNIT 8 BITS PWM 8CH (6CH) 8 (6) 14 BITS PWM 1CH HS1 HSYNC COUNTER 1 ADJ SDA0 SDA1 SCL0 SCL1 PWM PWM0 to PWM7 CXP750096/750010, CXP750097/750011 Asterisks indicate pins missing from 52-pin models.Parentheses indicate configurations for 52-pin models. PORT G –2– 2 2 3 PE0, PE1 PE2, PE3 PE4 to PE6 ON SCREEN DISPLAY 8 PF0 to PF7 HS0 HSYNC COUNTER 0 5 PG3 to PG6∗, PG7 CXP750096/750010, CXP750097/750011 Pin Assignment (Top View) 64-pin SDIP PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 PB6 PB5 PB4 PB3 INT1/PG7 PG6 PG5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PC4 PC5 PC6/PWM6 PC7/PWM7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 PE3/TX VSS VDD NC EXLC XLC PE4/YM PE5/YS PE6/I B G R PB0 PB1 PB2 PG3 PG4 Note) 1. NC (Pin 46) is left open. 2. Vss (Pins 16 and 48) are both connected to GND. –3– CXP750096/750010, CXP750097/750011 Pin Assignment (Top View) 64-pin QFP PC6/PWM6 PC7/PWM7 64 63 62 61 60 59 58 57 56 55 54 53 52 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 PE3/TX VSS VDD NC EXLC XLC PE4/YM PE5/YS PE6/I B G PC2 PB3 PG4 PG3 PB5 PB4 PB2 PF0/PWM0 PC3 PF1/PWM1 PB0 PD6/RMC PC4 PG6 PG5 PB6 Note) 1. NC (Pin 40) is left open. 2. Vss (Pins 10 and 42) are both connected to GND. INT1/PG7 –4– PB1 R PF2/PWM2 PD7/EC PC0 PC1 PC5 CXP750096/750010, CXP750097/750011 Pin Assignment (Top View) 52-pin SDIP EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 PB6 PB5 PB4 PB3 INT1/PG7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 PE3/TX VSS VDD NC EXLC XLC PE4/YM PE5/YS PE6/I B G R PB0 PB1 PB2 Note) 1. NC (Pin 38) is left open. 2. Vss (Pins 12 and 40) are both connected to GND. –5– CXP750096/750010, CXP750097/750011 Pin Description Symbol PA0/AN0 to PA5/AN5 PA6/VSYNC PA7/HSYNC PB0 to PB7 I/O I/O/ Analog input I/O/Input I/O/Input I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Description Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper 2 bits are output port and large current (12mA) N-channel open drain output. Upper 2 bits are medium drive voltage (12V); lower 6 bits are 5V drive. (8 pins) 8-bit PWM output. (2 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control reception circuit input. External event input for timer/counter. Rectangular wave output for 8-bit timer/counter. (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins) 14-bit PWM output. External interruption Connects a crystal for request input. Active at 32kHz timer/counter the falling edge. clock oscillation. When used as an event counter, input to TEX pin and leave TX pin open. TEX oscillation frequency dividing output. PC0 to PC5∗ I/O PC6/PWM6∗ to PC7/PWM7∗ PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 Output/Output I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output/ Output I/O/Output Input/Input/ Input Input/Output Output/Output Output/Output Output/Output Output Output Output PE3/TX PE4/YM PE5/YS PE6/I B G R OSD display 6-bit output. (6 pins) ∗ Not incorporated for Pin 52 package. –6– CXP750096/750010, CXP750097/750011 Symbol PF0/PWM0 to PF3/PWM3 PF4/SCL0 PF5/SCL1/ PWM4 PF6/SDA0 PF7/SDA1/ PWM5 PG3 to PG6∗ PG7/INT1 EXTAL XTAL RST EXLC XLC NC VDD Vss I/O Output/Output Output/I/O Output/I/O/ Output Output/I/O Output/I/O/ Output I/O I/O/Input Input Output Input Input Output (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium drive voltage (12V); upper 4 bits are 5V drive. (8 pins) Description 8-bit PWM output. (4 pins) I2C bus interface transfer clock I/O. (2 pins) 8-bit PWM output. I2C bus interface transfer data I/O. (2 pins) 8-bit PWM output. (Port G) 5-bit I/O port. I/O can be set in a unit of single bits. (5 pins) External interruption request input. Active at the falling edge. Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. OSD display clock oscillation I/O. Oscillation frequency is determined by the external L and C. No connected. Positive power supply. GND. Connect two Vss pins to GND. ∗ Not incorporated for Pin 52 package. –7– CXP750096/750010, CXP750097/750011 Input/Output Circuit Formats for Pins Pin Port A Circuit format Port A data Port A direction After a reset PA0/AN0 to PA5/AN5 “0” after a reset IP RD (Port A) Port A function selection Input protection circuit Internal data bus Hi-Z 6 pins “0” after a reset A/D converter Input multiplexer Port A Port A data Port A direction PA6/VSYNC PA7/HSYNC Internal data bus RD (Port A) HSYNC, VSYNC “0” after a reset Schmitt input IP Hi-Z 2 pins Port B Port C PB0 to PB7 PC0 to PC5∗2 PG3 to PG6∗2 PG7/INT1 Port G Ports B, C, G data Ports B, C, G direction “0” after a reset Input polarity “0” after a reset Internal data bus RD (Ports B, C, G) PB0 to PB2 Schmitt input only for PG7 Hi-Z IP 19 pins Port C PC6/PWM6∗2 PC7/PWM7∗2 PF0/PWM0 to PF3/PWM3 Port F INT1 PWM0 to PWM3 PWM6, PWM7 Ports C and F function selection “0” after a reset Ports C and F data “1” after a reset Internal data bus ∗1 12V drive voltage Large current 12mA ∗1 Hi-Z 6 pins ∗2 Not incorporated for Pin 52 package. RD (Ports C, F) –8– CXP750096/750010, CXP750097/750011 Pin Port D Circuit format After a reset Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction “0” after a reset Schmitt input RD (Port D) INT2, SI, HS0, HS1, RMC, EC ∗ Large current 12mA ∗ Hi-Z Internal data bus IP 6 pins Port D SCK, SO SIO output enable Port D data PD1/SCK PD2/SO Port D direction “0” after a reset Internal data bus RD (Port D) Schmitt input only for PD1 ∗ Hi-Z IP 2 pins Port E SCK only ∗ Large current 12mA Internal reset signal Port E data “1” after a reset TO ADJ16K∗1 ADJ2K∗1 00 01 10 11 MPX ∗2 PE0/TO/ADJ Port E function selection (Upper) Port E function selection (Lower) “00” after a reset Port E direction “1” after a reset Internal data bus ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up resistors approx. 150kΩ () High level H level at ON resistance of pull-up transistor during a reset 1 pin RD (Port E) –9– CXP750096/750010, CXP750097/750011 Pin Port E Circuit format PWM Port E function selection “0” after a reset Port E data After a reset PE1/PWM “1” after a reset High level Port E direction “1” after a reset IP Internal data bus 1 pin Port E RD (Port E) TEX oscillation circuit control “1” after a reset Schmitt input INT0 Intrenal data bus PE2/TEX/INT0 PE3/TX PE2/ TEX/ INT0 IP IP RD (Port E) Internal data bus RD (Port E) Schmitt input Clock input Oscillation halted Port input 2 pins PE3/ TX Port E YM, YS, I Output polarity “0” after a reset PE4/YM PE5/YS PE6/I Port E function selection “1” after a reset Port E data Internal data bus Writing data to output polarity register and port data register brings output to active. RD (Port E) Hi-Z 3 pins – 10 – CXP750096/750010, CXP750097/750011 Pin Port F SCL, SDA I2C bus enable Circuit format After a reset ∗ PWM4, PWM5 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 Port F function selection “0” after a reset Port F data “1” after a reset Internal data bus RD (Port F) SCL, SDA (I2C bus circuit) Schmitt input IP BUS SW Hi-Z 4 pins ∗ Large current 12mA To internal I2C pins (SCL1 for SCL0) R, G, B R G B Output polarity “0” after a reset Hi-Z Writing data to output polarity register brings output to active. 3 pins Oscillation control EXLC XLC EXLC IP IP OSD display clock Oscillation halted XLC 2 pins EXTAL XTAL EXTAL IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed and XTAL is driven at "H" level driving stop. (This device does not enter the stop mode.) Oscillation XTAL 2 pins Pull-up resistor RST OP Mask option Schmitt input Low level (during a reset) 1 pin – 11 – CXP750096/750010, CXP750097/750011 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Symbol VDD VIN VOUT VOUTP IOH ∑IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD 20 130 –20 to +75 –55 to +150 1000 600 mA mA °C °C mW mW SDIP-64P-01 QFP-64P-L01 Ratings –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +15.0 –5 –50 15 Unit V V V V mA mA mA (Vss = 0V reference) Remarks Total of all output pins Ports excluding large current output (value per pin) Large current output ports (value per pin∗2) Total of all output pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP750096/750010, CXP750097/750011 Recommended Operating Conditions Item Symbol Min. 4.5 VDD 3.5 2.7 — VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 ∗5 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 — VDD VDD Unit V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes Guaranteed operation range for 1/16 frequency dividing mode or sleep Guaranteed operation range for TEX mode Guaranteed data hold range for stop∗5 ∗1 ∗2 EXTAL pin∗3, TEX pin∗4 ∗1 ∗2 EXTAL pin∗3, TEX pin∗4 Supply voltage VDD – 0.4 VDD + 0.3 0 0 –0.3 –20 0.3VDD 0.2VDD 0.4 +75 This device does not enter the stop mode. PA0 to PA5, PB3 to PB7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0, SCL1, SDA0, SDA1 pins VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST pins Specifies only during external clock input. Specifies only during external event count input. – 13 – CXP750096/750010, CXP750097/750011 Electrical Characteristics DC characteristics Item High level output voltage Symbol Pins (Ta = –20 to +75°C, Vss = 0V reference) Conditions Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 –0.5 0.1 –0.1 –1.5 40 –40 10 –10 –400 ±10 50 10 120 Typ. Max. Unit V V V V V V V µA µA µA µA µA µA µA µA Ω VOH PA, PB, PC0 to PC5, VDD = 4.5V, IOH = –0.5mA PD, PE0 to PE1, PE4 to PE6, PG, R, VDD = 4.5V, IOH = –1.2mA G, B PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA PE4 to PE6, PF0 to VDD = 4.5V, IOL = 3.6mA PF3, PG, R, G, B Low level output voltage VOL PC6, PC7, PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V IIHE IILE Input current IIHT IILT IILR I/O leakage current Open drain I/O leakage current (in N-ch Tr off state) I2C bus switch connection impedance (in output Tr off state) IIZ EXTAL VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V TEX RST∗1 PA, PB, PC0 to PC5,PD, VDD = 5.5V, PE, PG, R, G, B, RST∗1 VI = 0, 5.5V PC6, PC7, PF0 to PF3 VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing mode VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5.5V, 24MHz crystal oscillation 20 ILOH PF4 to PF7 RBS SCL0: SCL1 SDA0: SDA1 30 mA IDD1 29 33 45 IDD2 Supply current∗2 IDDS1 VDD VDD = 3.3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Sleep mode VDD = 5.5V, 24MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode∗3 VDD = 5.5V, termination of 24MHz and 32kHz oscillation – 14 – — 82 µA 2.2 3.8 mA IDDS2 12 35 µA IDDS3 — — µA CXP750096/750010, CXP750097/750011 Item Symbol Pins PA, PB,PC0 to PC5, PD,PE0 to PE3, PF4 to PF7, PG, EXTAL, EXLC, RST Conditions Clock 1 MHz 0V other than the measured pins Min. Typ. Max. Unit Input capacitance CIN 10 20 pF ∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistor is selected. ∗2 When all output pins are left open. Specifies only when the OSD oscillation is halted. ∗3 This device does not enter the stop mode. – 15 – CXP750096/750010, CXP750097/750011 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times System clock frequency Event count input clock input pulse width Event count input clock rise and fall times Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig.2 Fig. 1, Fig.2 External clock drive Fig. 1, Fig.2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5 V Fig. 2 (32kHz clock applied conditions) Fig. 3 Fig. 3 10 20 4tsys∗1 20 Min. 8 17 200 Typ. Max 24 Unit MHz ns ns ns ms tXL, tXH tCR, tCF tEH, tEL tER, tEF fC 32.768 kHz tTL, tTH tTR, tTF µs ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 000FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) 1/fc VDD – 0.4V EXTAL 0.4V tXH Crystal oscillation Ceramic oscillation tCF tXL tCR Fig. 1. Clock timing External clock 32kHz clock applied condition Crystal oscillation EXTAL C1 XTAL C2 EXTAL XTAL TEX TX 74HC04 C1 C2 Fig.2. Clock applied conditions 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR TEX EC Fig. 3. Event count clock timing – 16 – CXP750096/750010, CXP750097/750011 (2) Serial transfer Item SCK cycle time SCK High and Low level width SI input setup time (for SCK ↑) SI hold time (for SCK ↑) SCK ↓ → SO delay time Symbol Pins SCK (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSO 0.8VDD SO 0.2VDD Output data Fig. 4. Serial transfer timing – 17 – CXP750096/750010, CXP750097/750011 (3) A/D converter Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT∗1 VFT∗2 Symbol Pins (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. Typ. Max. 8 ±3 Ta = 25°C VDD = 5.0V Vss = 0V –10 4910 26/fADC∗3 6/fADC∗3 AN0 to AN5 0 VDD 10 4970 70 5030 Unit Bits LSB mV mV µs µs V tCONV tSAMP VIAN FFh FEh Digital conversion value Linearity error ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 000F6h): fADC = fc (CKS = “0”), fc/2 (CKS = “1”) 01h 00h VZT Analog input VFT Fig. 5. Definitions for A/D converter terms – 18 – CXP750096/750010, CXP750097/750011 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption High, Low level width Reset input Low level width Symbol Pins INT0 INT1 INT2 RST Conditions Min. 1 32/fc Max. Unit µs µs tIH tIL tRSL tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 6. Interruption input timing tRSL RST 0.2VDD Fig. 7. RST input timing – 19 – CXP750096/750010, CXP750097/750011 (5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion Symbol fSLC (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Conditions Min. 0 4.7 4.0 4.7 4.0 4.7 0∗1 250 1 300 Max. 100 Unit kHz µs µs µs µs µs µs ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P Fig. 8. I2C bus transfer timing I2C bus device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C bus device R S RP RP Fig. 9. I2C bus device recommended circuit • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 20 – CXP750096/750010, CXP750097/750011 (6) OSD timing Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC afterwrite rise and fall times VSYNC beforewrite rise and fall times (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fOSC Pins EXLC XLC HSYNC VSYNC HSYNC VSYNC Conditions Fig. 11 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Min. 4 30/fc 1 200 1.0 Max 40.8 Unit MHz µs H∗2 ns µs tHWD tVWD tHCG tVCG ∗1 The maximum value of fosc is specified with the following equation. fosc [max] ≤ fc × 1.7 ∗2 H indicates 1HSYNC period. tHCG tHWD HSYNC For OSD I/O polarity register (OPOL: 001FEh) bit 7 at “0” 0.8VDD 0.2VDD tVCG tVWD 0.8VDD VSYNC For OSD I/O polarity register (OPOL: 001FEh) bit 6 at “0” 0.2VDD Fig. 10. OSD timing EXLC XLC R∗3 L C1 C2 Fig. 11. LC oscillation circuit connection ∗3 The series resistor for XLC (R = 1kΩ or less) can reduce the frequency of occurrence of the undesired radiation. – 21 – CXP750096/750010, CXP750097/750011 Appendix (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL Rd EXTAL XTAL Rd C1 TEX TX Rd C2 C1 C2 C1 C2 Fig. 12. Recommended oscillation circuit Manufacture Model CSA10.0MTZ CSA12.0MTZ CSA16.00MXZ040 fc (MHz) 10.0 12.0 16.0 24.0 10.0 12.0 16.0 8.0 C1 (pF) 30 5 OPEN 30 5 18 12 10 10 5 OPEN 3 30 18 C2 (pF) 30 5 OPEN 30 Rd (Ω) Circuit example Remarks (i) 0 ∗1 MURATA MFG CO., LTD. CSA24.00MXZ040 CST10.0MTW∗ CST12.0MTW∗ CST16.00MXW0C1∗ (ii) 5 18 12 10 10 5 OPEN 3 33 18 120k 330k (iii) (iii) CL = 12.5pF 0 ∗1 (i) 330 ∗1 RIVER ELETEC HC-49/U03 CO., LTD. 12.0 16.0 8.0 KINSEKI LTD. HC-49/U (-S) 12.0 16.0 24.0 P3 VTC-200 SEIKO Instruments Inc. SP-T 32.768kHz 32.768kHz ∗ Models with an astarisk (∗) have the built-in ground capacitance (C1, C2). ∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Reset pin pull-up resistor Non-existent – 22 – Content Existent CXP750096/750010, CXP750097/750011 IDD vs. VDD (Ta = 25°C, Typical) 100 fc = 24MHz fc = 16MHz 1/2 dividing mode fc = 24MHz fc = 16MHz 1/4 dividing mode fc = 24MHz fc = 16MHz 1/16 dividing mode 30 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 25 1/2 dividing mode 10 IDD – Supply current [mA] 1 IDD – Supply current [mA] fc = 24MHz Sleep mode fc = 16MHz 20 15 1/4 dividing mode 10 0.1 32kHz operation mode 32kHz sleep mode 0.01 0 1 2 3 4 5 6 7 5 1/16 dividing mode Sleep mode 0 0 5 10 15 20 25 Frequency [MHz] VDD – Supply voltage [V] Parameter curve for OSD oscillator L vs. C (Analytically calculated value) 100 10 L – Inductance [µH] 16MHz 1 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz 0.1 0.01 0 10 20 30 40 50 60 70 80 90 100 C1, C2 – Capacitance [pF] Fig. 13. Characteristic curves – 23 – CXP750096/750010, CXP750097/750011 Package Outline Unit: mm 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 33 19.05 + 0.3 17.1 – 0.1 + 0.1 0.05 0.25 – 0° to 15° 32 1.778 0.5 ± 0.1 0.9 ± 0.15 1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 + 0.35 2.75 – 0.15 0.2 M 0° to10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g – 24 – 0.8 ± 0.2 19 16.3 CXP750096/750010, CXP750097/750011 52PIN SDIP (PLASTIC) + 0.4 47.0 – 0.1 52 27 + 0.3 13.5 – 0.1 + 0.1 .05 0.25 – 0 1 1.778 26 15.24 0° to 15° 0.5 ± 0.1 + 0.1 0.9 – 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-52P-01 SDIP052-P-0600 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 5.6g – 25 – 2.8 MIN 0.51 MIN 5.0 MIN