CXP823P24

CXP823P24 CMOS 8-bit Single Chip Microcomputer Description The CXP823P24 is a highly integrated CMOS 8-bit single-chip microcomputer which is mainly composed of an 8-bit CPU, PROM, RAM and I/O ports. This microcomputer features many other high-performance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, timebase timer, capture timer/counter, fluorescent display tube controller/driver, and remote control receiver. Also, the CXP823P24 provides the power-on reset function as well as the sleep/stop function which assures reduced power consumption. Being a PROM-incorporated version of the CXP82324 which has on-chip mask ROM, the CXP823P24 permits program writing. Therefore, it is ideally suited for use in system development stage evaluation and job lot production. 80 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Instruction set which supports a wide array of data types 213 types — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 400ns/10MHz • Incorporated PROM capacity 24K bytes • Incorporated RAM capacity 704 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive comparison type (conversion time: 32µs at 10MHz) — Serial interface 1 channel data interface with an 8-bit, 8-stage FIFO (1 to 8 byte automatic transfer) 1-channel, 8-bit clock synchronized interface — Timers 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture timer/counter — Fluorescent display tube controller/driver Display of up to 336 segments 1 to 16 digit dynamic display Dimmer function High voltage tolerance output (40V) Built-in pull-down resistor — Remote control receiver Built-in noise suppressor circuit Built-in 8-bit pulse counter and 6-stage FIFO • Interrupts 14 factors, 15 vectors, multiple interrupt pocessing • Standby mode Sleep/stop • Package 80-pin plastic QFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92Y35A78-PS Block Diagram SPC700 CPU CORE T0 to T7 RAM 80 BYTES 8 CLOCK GENERATOR/ SYSTEM CONTROL PORT A PA0/AN0 to PA7/AN7 8 A/D CONVERTER PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3 EXTAL XTAL RST VDD Vpp VSS 8 PA0 to PA7 S0 to S20 21 FDP CONTROLLER/ DRIVER VFDP FIFO PROM 24K BYTES PORT B T8/S28 to T15/S21 8 7 PB0 to PB6 PB7 8 PC0 to PC7 REMOCON RAM 704 BYTES PORT C PE4/RMC INTERRUPT CONTROLLER PB6/SI1 PB7/SO1 PB5/SCK1 2 PE0/INT0/EC0 8 BIT TIMER 1 2 PORT F 8 BIT TIMER/COUNTER 0 PORT E PE7/TO PB0/CINT PE1/INT1/EC1 16 BIT CAPTURE TIMER/COUNTER 2 PORT G –2– FIFO PRESCALER/ TIME BASE TIMER PB1/CS0 PB3/SI0 PB0/SO0 PB2/SCK0 SERIAL INTERFACE UNIT 0 PORT D 8 PD0 to PD7 6 2 PE0 to PE5 PE6 to PE7 SERIAL INTERFACE UNIT 1 8 PF0 to PF7 4 PG0 to PG3 CXP823P24 CXP823P24 Pin Assignment (Top View) PE1/EC1/INT1 PE0/EC0/INT0 PE2/IN2 PG3 Vpp VDD VFDP PG2 PG1 PG0 T0 T1 T2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE3/INT3 PE4/RMC PE5 PE6 PE7/TO PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 T6 T7 T8/S28 T9/S27 T10/S26 T11/S25 T12/S24 T13/S23 T14/S22 T15/S21 S20 S19 S18 S17 S16 PF7/S15 PF6/S14 PF5/S13 PF4/S12 PF3/S11 PF2/S10 PF1/S9 PF0/S8 PD7/S7 PA4/AN4 PA3/AN3 PA7/AN7 PD1/S1 PD2/S2 PD3/S3 PD4/S4 EXTAL XTAL RST T3 T4 PD5/S5 PA6/AN6 Note) Vpp (Pin 73) is always connected to VDD. PA5/AN5 –3– PD0/S0 PD6/S6 VSS T5 CXP823P24 Pin Description Symbol PA0/AN0 to PA7/AN7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 to PC7/KR7 I/O (Port A) 8-bit port; single bit addressable. (8 pins) Description Analog input to A/D converter. (8 pins) External capture input for 16-bit timer/counter. Chip select input for serial interface (CH0). (Port B) Single bit addressable from amongst lower 7 bits; highest bit (PB7) dedicated to output. (8 pins) Serial clock (CH0) input/output. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH1) input/output. Serial data (CH1) input. Serial data (CH1) output. (Port C) 8-bit port; single bit addressable. Can provide 12mA sink current. (8 pins) I/O/Analog input I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output I/O/Input Key return input for FDP segment signal which performs key scanning. PE0/INT0/EC0 Input/Input/Input PE1/INT1/EC1 Input/Input/Input PE2/INT2 PE3/INT3 PE4/RMC PE5 PE6 PE7/TO Input/Input Input/Input Input/Input Input Output Output/Output (Port E) 8-bit port with lower 6 bits dedicated to input and upper 2 bits dedicated to output. (8 pins) Input for external interrupt requests. (4 pins) External event input to timer/counter. (2 pins) Input for remote control receiving circuit. Output pin for 16-bit timer/counter rectangular waveform. (Port G) 4-bit input/output port; single bit addressable. (4 pins) (Port F) 8-bit dedicated output port. (8 pins) Segment signal output for FDP. Dual purpose output for FDP timing and segment signals. Timing signal output for FDP. (Port D) 8-bit dedicated output port. Segment signal output for FDP. (8 pins) –4– Segment signal output for FDP. PG0 to PG3 PF0/S8 to PF7/S15 S16 to S20 T8/S28 to T15/S21 T0 to T7 PD0/S0 to PD7/S7 I/O Output/Output Output Output/Output Output Output/Output CXP823P24 Symbol VFDP EXTAL XTAL RST Input I/O Provides voltage for FDP. Description Output I/O Connection for system clock oscillation crystal. When using an external clock, input normal signal to EXTAL and reverse phase signal to the XTAL pin. System reset, active "L". The RST pin is an input/output pin which outputs a "L" level from the on-chip power on reset circuit when the power is turned on. Positive power supply for the programmable on-chip PROM; connect to VDD for nomal operation. Positive power supply pin. GND Vpp VDD VSS –5– CXP823P24 Input/Output Circuit Formats for Pins Pin Port A Port A data Circuit format When reset PA0/AN0 to PA7/AN7 Port A direction "0" when reset Data bus RD (Port A) Port A input select "0" when reset Input multiplexer A/D converter IP Input protection circuit Hi-Z 8 pins Port B Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Port B direction "0" when reset Data bus RD (Port B) CINT CS0 SI0 SI1 Schmitt input IP Hi-Z 4 pins Port B SCK OUT Output enable Port B output select "0" when reset PB2/SCK0 PB5/SCK1 Port B data Port B direction "0" when reset Data bus Schmitt input IP Hi-Z RD (Port B) 2 pins SCK in –6– CXP823P24 Pin Port B SO Output enable Port B output select "0" when reset Circuit format When reset PB4/SO0 Port B data Port B direction "0" when reset Data bus IP Hi-Z 1 pin Port B RD (Port B) Internal reset signal SO Output enable Port B output select ∗ PB7/SO1 "0" when reset Port B data "1" when reset Data bus High level ∗Pull-up transistor approx. 200kΩ 1 pin Port C RD (Port B) Port C data PC0/KR0 to PC7/KR7 Data bus Port C direction "0" when reset ∗ IP Hi-Z RD (Port C) 8 pins Port E PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3 PE4/RMC 5 pins Key input signal ∗Capable of driving 12mA large current Schmitt input IP EC0/INT0 EC1/INT1 INT2 INT3 RMC Data bus RD (Port E) Hi-Z –7– CXP823P24 Pin Port E PE5 Circuit format When reset IP Data bus Hi-Z RD (Port E) 1 pin Port E PE6 Port E data "1" when reset High level 1 pin Port E TO Output enable (T2OE) Port E output select PE7/TO "0" when reset Port E data "1" when reset Data bus High level 1 pin RD (Port E) Port G Port G data PG0 to PG3 Port G direction "0" when reset Data bus RD (Port G) IP Hi-Z 4 pins –8– CXP823P24 Pin Port D PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 16 pins Port F Segment output data Circuit format ∗High voltage tolerance transistor ∗ When reset Output selection control signal ("0" when reset) Port D data or Port F data "0" when reset Data bus Pull-down resistor OP Mask option Hi-Z or Low level (when pulldown resistor is connected) VFDP RD (Port D or Port F) ∗High voltage tolerance transistor S16 to S20 T15/S21 to T8/S28 T0 to T7 Segment output data Output selection control signal ("0" when reset) ∗ OP Pull-down resistor Mask option Hi-Z or Low level (when pulldown resistor is connected) VFDP 21 pins ∗Diagram shows EXTAL XTAL circuit construction for oscillation. EXTAL IP IP ∗During stop feedback resistor is disconnected. XTAL Oscillation 2 pins Pull-up resistor RST OP Mask option IP Schmitt input Low level 1 pin From power on reset circuit (Mask option) –9– CXP823P24 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Display output voltage Symbol VDD Vpp VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current ∑IOH ∑IODH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD Rating –0.3 to +7.0 –0.3 to +13.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 VDD – 40 to VDD + 0.3 –5 –15 –35 –40 –100 15 20 100 –10 to +75 –55 to +150 600 Unit V V V V V mA mA mA mA mA mA mA mA °C °C mW Incorporated PROM Remarks (Vss = 0V) As P channel transistor is open drain, VDD voltage is determined as standerd. Other than display output pins∗2 : per pin Display outputs S0 to S20: per pin Display outputs T0 to T7, T8/S28 to T15/S21: per pin Total of other than display output pins Total of display output pins Port 1 pin Large current port pin ∗3 Entire pin total Low level output current ∗1 VIN and VOUT cannot exceed VDD + 0.3V. ∗2 Rating for output current of general input/output port. ∗3 The large current drive transistor is an N-channel transistor of Port C. Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected. – 10 – CXP823P24 Recommended Operating Conditions Item Symbol Min. 4.5 VDD Supply voltage 3.5 2.5 Vpp VIH High level input voltage VIHS Max. 5.5 5.5 5.5 V V V V V V V °C V Unit Remarks (Vss = 0V) High-speed mode (1/2, 1/4 clock) guaranteed range during operation Low-speed mode (1/16 clock) guaranteed range during operation Guaranteed data hold operation range during stop ∗4 ∗1 Hysteresis input∗2 EXTAL pin∗3 ∗1 Hysteresis input EXTAL pin∗3 Vpp = VDD 0.7VDD 0.8VDD VDD VDD VIHEX VDD – 0.4 VDD + 0.3 VIL Low level input voltage VILS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 0 0 –0.3 –10 0.3VDD 0.2VDD 0.4 +75 All regular input ports (PA, PB3, PB4, PB6, PC, PE5, PG). For pins RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3, RMC. Rating only for external clock input. Vpp and VDD should be set to the same voltage. – 11 – CXP823P24 Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage Symbol VOH Pins PA, PB, PC, PE6, PE7, PG, RST (for VOL only) PC IIHE Input current IILE IILR Display output current Open drain output leak current (P-CH Tr off state) Pull-down resistor Input/output leak current IOH EXTAL RST S0 to S20 S21/T15 to S28/T8 T0 to T7 S0 to S20 S21/T15 to S28/T8 T0 to T7 S0 to S20 S21/T15 to S28/T8 T0 to T7 PA to PC, PE, PG VDD = 4.5V VOH = VDD – 2.5V VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V VDD = 5V VOD – VFDP = 30V VDD = 5.5V VI = 0, 5.5V VDD = 5.5V High-speed mode (1/2 clock) operation IDD1 Supply current∗ IDDSL IDDST For pins other than S0 to S28, T0 to T7, PB7, PE6, PE7, VDD, VSS, VFDP VDD 10MHz crystal oscillator (C1 = C2 = 15pF) Sleep mode Stop mode Condition VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V (Ta = –10 to +75°C, Vss = 0V) Min. Typ. Max. Unit 4.0 3.5 0.4 0.6 1.5 0.5 –0.5 –1.5 –8 –20 40 V V V V V µA VOL –40 µA –400 µA mA mA ILOL –20 µA RL 60 100 270 kΩ ±10 µA IIZ 25 40 mA 3 8 30 mA µA Input capacitance CIN 1MHz clock 0V other than the measured 10 20 pF ∗ All output pins are left open. – 12 – CXP823P24 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rising and falling times Event count input clock pulse width Event count input clock rising and falling times ∗1 Symbol fC Pins (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Min. 1 45 200 Max. 10 Unit MHz ns ns ns 20 ms XTAL Fig. 1, Fig. 2 EXTAL Fig. 1, Fig. 2 EXTAL External clock driver Fig. 1, Fig. 2 EXTAL External clock driver EC0, EC1 EC0, EC1 Fig. 3 Fig. 3 tXL, tXH tCR, tCF tEH, tEL tER, tEF tsys + 50∗1 tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits= "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applying condition Crystal oscillation Ceramic oscillation External clock EXTAL C1 XTAL C2 EXTAL XTAL 74HC04 Fig. 3. Event count clock timing 0.8VDD EC0 EC1 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR – 13 – CXP823P24 (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 float delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 float delay time CS0 high level width SCK0 cycle time SCK0 high and low level width SI0 input setup time (against SCK0 ↑) SI0 input hold time (against SCK0 ↑) SCK0 ↓ → SO0 delay time Note 1) Symbol Pin SCK0 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 tsys + 100 8000/fc – 50 100 200 SI0 SI0 tsys + 200 100 SO0 tsys + 200 100 ns ns tsys is determind by the upper two bits of the clock control resister (Address: 00FEH; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 14 – CXP823P24 Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 15 – CXP823P24 Serial transfer (CH1) Item SCK1 cycle time SCK1 high and low level width SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Input mode Output mode SCK1 Input mode Output mode SI1 SCK1 input mode SCK1 output mode SI1 SCK1 input mode SCK1 output mode SO1 SCK1 input mode SCK1 output mode Min. 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 16 – CXP823P24 (3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT∗1 VFT∗2 Symbol Pin (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Min. Typ. Max. 8 A/D converter operation only Ta = 25°C VDD = 5.0V VSS = 0V ±3 –10 4930 160/fADC ∗3 12/fADC ∗3 70 5050 150 5120 Unit Bits LSB mV mV µs µs VDD V tCONV tSAMP VIAN AN0 to AN7 0 Fig. 6. Definition of A/D converter terms FFH FEH Digital conversion value ∗1 VZT : Digital Value converted between 00H to 01H. ∗2 VFT : Digital Value converted between FEH and FFH. ∗3 fADC : ADC operation clock selection (MSC: Bit 0 of address 01FFH) and assumes following values: fADC = fc/2 when PS2 is selected. fADC = fc when PS1 is selected. Linearity error 01H 00H VZT Analog input VFT – 17 – CXP823P24 (4) Interrupts, reset inputs Item External interrupt High and Low level widths Reset input Low level width Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 INT3 RST Condition Min. Max. Unit tIH tIL tRSL 1 µs 8/fc µs Fig. 7. Interrupt input timing tIH tIL 0.8VDD INT0 INT1 INT2 INT3 0.2VDD 0.2VDD tIL tIH 0.8VDD Fig. 8. RST input timing tRSL RST 0.2VDD (5) Power-on reset Power-on reset Item Power supply rising time Symbol Pin VDD (Ta = –10 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V) Condition Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR Power supply cut-off time tOFF Fig. 9. Power-on reset 4.5V VDD 0.2V 0.2V tR The power supply should rise smoothly. tOFF – 18 – CXP823P24 Supplement Fig. 10. Recommended Oscillation Circuit (i) (ii) EXTAL XTAL EXTAL XTAL C1 C2 C1 C2 Manufacturer Model CSA4.19MG CSA8.00MTZ fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 C1 (pF) C2 (pF) Circuit Example (i) 30 30 (ii) MURATA MFG CO., LTD CSA10.0MTZ CST4.19MGW∗ CST8.00MTW∗ CST10.0MTW∗ RIVER HC-49/U03 ELETEC CORPORATION 15 15 (i) KINSEKI LTD. HC-49/U (-S) 8.00 10.00 27 27 ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Product List Optional item Package ROM capacity Reset pin pull-up resistor Power-on reset circuit High voltage tolerance pin pull-down resistor Mask 80 pin plastic QFP 20K bytes/24K bytes Existent/Non-existent Existent/Non-existent Existent/Non-existent CXP823P24Q-180 pin plastic QFP PROM 24K bytes Existent Existent Non-existent (S0/PD0 to S15/PF7) Existent (T0 to S16) – 19 – CXP823P24Q-280 pin plastic QFP PROM 24K bytes Existent Existent Existent (High voltage tolerance pin) CXP823P24 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 – 20 – 0.8 ± 0.2 1 24 16.3