CXP82800

CXP82800 CMOS 8-bit Single Chip Microcomputer Description The CXP82800 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP82832/82840/82852/82860. Piggyback/evaluator 100 pin PQFP (Ceramic) Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit operation/multiplication and division/ Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation • Applicable EPROM LCC type 27C512 (Maximum 60K bytes are available.) • Incorporated RAM capacity 1536 bytes (Including fluorescent display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel — Timers 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter — Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel. High voltage drive output port of 56 pins (40V) Maximum of 640 segments display possible Display timing number of 1 to 20 Dimmer function Incorporated pull-down resistor (Mask option) Hardware key scan function (Maximum 16 × 8 key matrix compatible) — Remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — PWM output 14 bits, 1 channel • Interruption 16 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP82800. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96529-ST CXP82800 Pin Configuration in Piggyback Mode G10/A10 G11/A11 G12/A12 G13/A13 G14/A14 G15/A15 G2/A2 G3/A3 G4/A4 G5/A5 G6/A6 G7/A7 G8/A8 G9/A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 G1/A1 G0/A0 NC PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5 PE6/PWM PE7/TO/ADJ PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 AVREF PA0/AN0 PA1/AN1 1 2 3 4 5 6 80 79 78 77 76 75 A21 A22 A23 PH7/A24 PH6/A25 PH5/A26 PH4/A27 PH3/A28 PH2/A29 PH1/A30 PH0/A31 PG7/A32 PG6/A33 PG5/A34 PG4/A35 PG3/A36 PG2/A37 PG1/A38 PG0/A39 PF7/A40 PF6/A41 PF5/A42 PF4/A43 PF3/A44 PF2/A45 PF1/A46 PF0/A47 PD7/A48 PD6/A49 PD5/A50 A12 A15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 A7 NC VDD A14 A13 7 VDD A16 A17 A18 A19 A20 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 14 15 16 17 18 19 20 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC D1 D2 D3 D4 D5 PA2/AN2 PA3/AN3 PA4/AN4 Note) 1. NC (Pin 3) is always connected to VDD. 2. VDD (Pins 44 and 89) are both connected to VDD. PA5/AN5 PA6/AN6 PA7/AN7 –2– PD0/A55 PD1/A54 PD2/A53 PD3/A52 PD4/A51 EXTAL XTAL AVSS VFDP TEX RST VDD Vss TX CXP82800 Pin Configuration in Evaluator Mode G12/A12 G2/A2 G3/A3 G4/A4 G5/A5 G6/A6 G7/A7 G8/A8 G9/A9 G10/A10 G11/A11 G13/A13 G14/A14 G15/A15 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 G1/A1 G0/A0 NC PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/NT3/NMI PE4/RMC PE5 PE6/PWM PE7/TO/ADJ PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/ SO0 PB5/SCK1 PB6/SI1 PB7/SO1 AVREF PA0/AN0 PA1/AN1 1 2 3 4 5 80 79 78 77 76 A21 A22 A23 PH7/A24 PH6/A25 PH5/A26 PH4/A27 PH3/A28 PH2/A29 PH1/A30 PH0/A31 PG7/A32 PG6/A33 PG5/A34 PG4/A35 PG3/A36 PG2/A37 PG1/A38 PG0/A39 PF7/A40 PF6/A41 PF5/A42 PF4/A43 PF3/A44 PF2/A45 PF1/A46 PF0/A47 PD7/A48 PD6/A49 PD5/A50 A7/D7 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD A16 A17 A18 A19 A20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A12 A15 NC 4 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYNC GND RST WR NC C2 C1 21 A14 VDD A13 PA2/AN2 PA3/AN3 Note) 1. NC (Pin 3) is always connected to VDD. 2. VDD (Pins 44 and 89) are both connected to VDD. –3– PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 PD0/A55 PD1/A54 PD2/A53 PD3/A52 PD4/A51 EXTAL XTAL AVSS VFDP TEX RST VDD Vss TX CXP82800 EPROM Read Timing (Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference) Item Address → Data input delay time Address → Data hold time Symbol Pins A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 120 Unit ns ns tACC tIH 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Mask CXP82832 CXP82840 CXP82852 CXP82860 Package ROM capacitance Pull-up resistance for reset pin Pull-down resistance for high voltage drive pin 100-pin plastic QFP 32K bytes 40K bytes 52K bytes 60K bytes Existent/Non-existent Existent/Non-existent Piggyback/evaluator CXP82800-U01Q 100-pin ceramic PQFP EPROM 60K bytes Existent Existent: G0/A0 to A23 Non-existent: PD0/A55 to PH7/A24 –4– CXP82800 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU Probe Note) Evaluation cap should be connected to CPU probe. –5– Package Outline 100PIN PQFP (CERAMIC) Unit: mm PIN NO. 1 INDEX 18.7 INDEX 81 81 PIN No. 1 INDEX 100 16.3 ± 0.2 100 1 80 80 1 6.0 24.7 1.27 ± 0.13 12.02 14.22 22.3 ± 0.25 18.12 ± 0.2 0.3 1.0 0.7 30 51 51 30 31 50 50 0.45 31 11.66 15.58 ± 0.2 1.3 ± 0.3 9.48 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 3.57 ± 0.36 + 0.05 0.15 – 0.02 0.50 ± 0.25 10.44 MAX 0.3 ± 0.08 0.65 ± 0.05 4.5 –6– CXP82800