CXP82960

CXP82940/82948/82952/82960 CMOS 8-bit Single Chip Microcomputer Description The CXP82940/82948/82952/82960 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, fluorescent display panel controller/driver, I2C bus interface, remote control transmission circuit, remote control reception circuit, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. 80 pin QFP (Plastic) Structure Features1 Silicon gate CMOS IC • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (122µs at 32kHz operation) • Incorporated ROM capacity 40K bytes (CXP82940) 48K bytes (CXP82948) 52K bytes (CXP82952) 60K bytes (CXP82960) • Incorporated RAM capacity 2048 bytes (including fluorescent display area) • Periphera; functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 20µs/16MHz) — Serial interface Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel — Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer 32kHz timer/counter — Fluorescent display panel controller/driver Maximum of 196 segments display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) Incorporated pull-down resistor (Mask option) Hardware key scan function Maximum of 12 × 8 key matrix supportable 2C bus interface —I — Remote control transmission circuit Auto transmission for 1 to 32 bytes, restart function, carrier output function — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO • Interruption 16 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 80-pin plastic QFP • Piggyback/evaluation chip CXP82900 80-pin ceramic QFP Perchase of Sony’s I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95130-PK Block Diagram AVSS AVREF AVDD INT0 INT1 INT2 INT3/NMI TEX TX EXTAL XTAL 2 T0 to T7 RAM 8 SPC 700 CPU CORE 8 CLOCK GENERATOR SYSTEM CONTROL 8 T8/S19 to T15/S12 8 PORT A AN0 to AN7 8 A/D CONVERTER RST VDD VSS PA0 to PA7 S0 to S11 VFDP KR0 to KR7 RAM ROM 40K/48K/52K/60K BYTES RAM 2048 BYTES 8 KEY SCAN PORT B 12 FDP CONTROLLER/ DRIVER PB0 to PB7 RMCO BUFFER REMOCON OUT RAM FIFO PORT C 8 PC0 to PC7 PORT D CS0 SI0 SO0 SCK0 BUFFER RAM FIFO PRESCALER/ TIME BASE TIMER 2 SERIAL INTERFACE UNIT (CH0) PORT E SI1 SO1 SCK1 EC 8 BIT TIMER/COUNTER 0 PORT F SCL0 SCL1 SDA0 SDA1 2 I2C BUS INTERFACE UNIT CXP82940/82948/82952/82960 ADJ PORT G –2– RMC REMOCON IN INTERRUPT CONTROLLER 8 PD0 to PD7 6 2 PE0 to PE5 PE6 to PE7 SERIAL INTERFACE UNIT (CH1) 32KHz TIMER/COUNTER 4 PF0 to PF3 TO 8 BIT TIMER 1 4 PG0 to PG3 CXP82940/82948/82952/82960 Pin Assignment (Top View) PE0/EC/INT0 PG3 PG2 PG1 PG0 TEX VDD NC TX T0 T1 T2 T3 T4 T5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5 PE6/RMCO PE7/TO/ADJ PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 T7 T8/S19 T9/S18 T10/S17 T11/S16 T12/S15 T13/S14 T14/S13 T15/S12 S11 S10 S9 S8 PD7/S7 PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 PD0/S0 VFDP PC7/KR7 PC6/KR6 PF1/SCL1 PF2/SDA0 PF3/SDA1 EXTAL PC1/KR1 AVSS XTAL VSS PC0/KR0 PC3/KR3 PF0/SCL0 Note) NC (Pin 75) must be connected to VDD. –3– PC2/KR2 PC4/KR4 PC5/KR5 AVREF RST T6 CXP82940/82948/82952/82960 Pin Description Pin code I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions PA0/AN0 to PA7/AN7 I/O/ Analog input Analog inputs to A/D converter. (8 pins) PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving Serves as key return inputs when operating 12mA sync current. key scan with fluorescent display panel (FDP) Incorporation of pull-up segment signal (8 pins). resistor can be set through the software in a unit of 4 bits. (8 pins) Inputs for external interruption request. (4 pins) External event inputs for timer/counter. PC0/KR0 to PC7/KR7 I/O/Input PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5 PE6/RMCO PE7/TO/ADJ PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1 Input/Input/Input Input/Input Input/Input Input/Input/Input Input/Input Input Output/Output Output/Output/ Output Output/I/O (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Non-maskable interruption request input. Remote control reception circuit input. Carrier output of remote control transmission circuit. Output for the timer/counter rectangular waves, and 32kHz oscillation dividing frequency. (Port F) Transfer clock I/Os for I2C bus interface. 4-bit output port, operating as N-ch open drain output for large current (12mA). Transfer data I/Os for I2C bus interface. (4 pins) Output/I/O –4– CXP82940/82948/82952/82960 Pin code I/O Functions (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (4 pins) (Port D) 8-bit output ports. (8 pins) FDP segment signal outputs. (8 pins) PG0 to PG3 I/O PD0/S0 to PD7/S7 S8 to S11 T8/S12 to T15/S19 T0 to T7 VFDP EXTAL XTAL TEX TX RST NC AVDD AVREF AVSS VDD VSS Output/Output Output Output/Output Output FDP segment signal outputs. (4 pins) Outputs for FDP timing signals/segment signals. (8 pins) FDP timing signal outputs. FDP voltage supply when incorporated resistor is set by mask option. Input Output Input Output Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz crystal oscillator between TEX and TX. For usage as event input, attach clock source to TEX, and open TX. Low-level active, system reset. NC. Under normal operation, connect to VDD. Positive power supply for A/D converter. Input Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND. –5– CXP82940/82948/82952/82960 I/O Circuit Format for Pins Pin Port A Pull-up resistor "0" when reset Port A data Circuit format ∗ When reset PA0/AN0 to PA7/AN7 Port A direction "0" when reset Data bus RD (Port A) Port A input selection "0" when reset A/D converter IP Input protection circuit Hi-Z Input multiplexer ∗ Pull-up transistor approx. 100kΩ 8 pins Port B Pull-up resistor "0" when reset Port B data ∗ PB1/CS0 PB3/SI0 PB6/SI1 Port B direction "0" when reset Data bus RD (Port B) CS0 SI0 SI1 Schmitt input IP Hi-Z ∗ Pull-up transistor approx. 100kΩ 3 pins Port B Not Schmitt input for SI0 and SI1. ∗ Pull-up resistor "0" when reset SCK OUT Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Schmitt input IP PB2/SCK0 PB5/SCK1 Hi-Z 2 pins SCK in ∗ Pull-up transistor approx. 100kΩ –6– CXP82940/82948/82952/82960 Pin Port B Circuit format ∗ Pull-up resistor "0" when reset SO Output enable When reset PB4/SO0 PB7/SO1 Port B output selection "0" when reset Port B data Port B direction “0” when reset Data bus IP Hi-Z 2 pins Port C RD (Port B) ∗ Pull-up transistor approx. 100kΩ ∗2 Pull-up resistor "0" when reset Port C data PC0/KR0 to PC7/KR7 Port C direction "0" when reset Data bus RD (Port C) ∗1 IP Hi-Z 8 pins PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC 5 pins PE5 1 pin Port E Port E Port E Key input signal ∗1 Large current 12mA ∗2 Pull-up transistor approx. 100kΩ EC/INT0 INT1 INT2 INT3/NMI RMC Data bus RD (Port E) Schmitt input IP Hi-Z IP RD (Port E) Remote control transmission circuit Data bus Hi-Z Port E output selection "0" when reset PE6/RMCO Reset E data "1" when reset Data bus Output enable High level 1 pin RD (Port E) –7– CXP82940/82948/82952/82960 Pin Port E Circuit format Internal reset signal Port E data "1" when reset TO ADJ16K∗1 00 01 10 11 MPX ∗2 When reset PE7/TO/ADJ ADJ2K∗1 Port E output selection (upper) Port E output selection (lower) High level (with approx. 150kΩ resistor when reset) "00" when reset TO output enable 1 pin Port F ∗1 ADJ signal is a frequency dividing output for 32kHz oscillation frequency adjustment. ADJ2 can be used for buzzer output. ∗2 Pull-up transistor approx. 150k Ω. SCL, SDA PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1 I2C output enable ("0" when reset) Port F data "1" when reset Schmitt input SCL, SDA (I2C circuit) IP Large current 12mA Hi-Z BUS SW To internal I2C pin (to SCL1 for SCL0) 4 pins Port B Port G Pull-up resistor "0" when reset Port B data or Port G data ∗ PB0 PG0 to PG3 Port B direction or Port G direction "0" when reset Data bus RD (Port B or Port G) Hi-Z IP 5 pins ∗ Pull-up transistor approx. 100kΩ –8– CXP82940/82948/82952/82960 Pin Port D Circuit format ∗ High voltage drive transistor Segment output data ∗ When reset PD0/S0 to PD7/S7 Output selection control signal ("0" when reset) Port D data OP Mask option Pull-down transistor Data bus VFDP RD (Port D) Hi-Z or Low level (when PD resistor is connected) 8 pins ∗ High voltage drive transistor S8 to S11 T15/S12 to T8/S19 T0 to T7 Segment output data Timing output data Output selection control signal ("0" when reset) ∗ OP Pull-down resistor Mask option Hi-Z or Low level (when PD resistor is connected) 20 pins VFDP EXTAL XTAL EXTAL IP IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop, and XTAL becomes High. Oscillation 2 pins XTAL TEX TX TEX IP IP •Diagram shows circuit composition during oscillation. 2 pins TX •When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX becomes Low level and TX becomes High level. Oscillation Pull-up resistor RST OP Mask option IP Low level Schmitt input 1 pin –9– CXP82940/82948/82952/82960 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Display output voltage Symbol VDD VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current ∑IOH ∑IODH IOL IOLC Rating –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 VDD – 40 to VDD + 0.3 –5 –15 –35 –40 –100 15 20 100 –20 to +75 –55 to +150 600 Unit V V V V mA mA mA mA mA mA mA mA °C °C mW (Vss = 0V reference) Remarks As P channel transistor is open drain, VDD is reference. All pins excluding outputs∗2 (value per pin) Display outputs S0 to S11 (value per pin) Display outputs T0 to T7, and T8/S19 to T15/S12 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port (value per pin) Large current Port (value per pin)∗3 Total for all output pins Low level total output current ∑IOL Operating temperature Storage temperature Topr Tstg Allowable power dissipation PD ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 Specifies output current of general-purpose I/O ports. ∗3 The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 10 – CXP82940/82948/82952/82960 Recommended Operating Conditions Item Symbol Min. 4.5 Max. 5.5 Unit V (Vss = 0V reference) Remarks Guaranteed operation range for high-speed mode (1/2, 1/4 frequency dividing clock) Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) or SLEEP mode Guaranteed operation range with TEX clock Guaranteed data hold range during STOP ∗1 Hysteresis input∗2 EXTAL∗3 ∗1 Hysteresis input∗2 EXTAL∗3 Supply voltage VDD 3.5 5.5 V 2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD 5.5 5.5 VDD VDD V V V V V V V V °C VDD – 0.4 VDD + 0.3 0 0 –0.3 –20 0.3VDD 0.2VDD 0.4 +75 ∗1 Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG). ∗2 Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1, SDA0, SDA1. ∗3 Specifies only during external clock input. – 11 – CXP82940/82948/82952/82960 Electrical Characteristics DC Characteristics Item High level output current Symbol VOH Pins PA, PB, PC, PE6, PE7, PG PC, PF Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA Low level output current VOL VDD = 4.5V, IOL = 12.0mA (Ta = –20 to +75°C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 –0.5 0.1 –0.1 –1.5 40 –40 10 –10 –400 –50 VDD = 4.5V, VIL = 4.0V VDD = 4.5V VOH = VDD – 2.5V –3.3 –8 –20 Typ. Max. Unit V V V V V V V µA µA µA µA µA µA µA mA mA PF VDD = 4.5V, IOL = 3.0mA (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA IIHE IILE IIHT EXTAL VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V TEX RST∗1 PA to PC∗2, PG∗2 S0 to S11 VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V Input current IILT IILR IIL Display output current IOH S12/T15 to S19/T8, T0 to T7 S0 to S11, S12/T15 to S19/T8, T0 to T7 S0 to S11, S12/T15 to S19/T8, T0 to T7 PA to PC∗2, PG∗2, RST∗1 Open drain output ILOL leakage current (P-CH Tr off state) VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V –20 µA Pull-down resistance∗3 RL VDD = 5V VOD – VFDP = 30V 60 100 270 kΩ I/O leakage current Open drain output leakage current (N-ch Tr off state) I2C bus switch connection impedance (Output Tr off state) IIZ VDD = 5.5V VI = 0, 5.5V ±10 µA ILOH PF VDD = 5.5V, VOH = 5.5V 10 µA RBS SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω – 12 – CXP82940/82948/82952/82960 Item Symbol Pins Conditions High speed mode operation (1/2 frequency dividing clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32MHz crystal oscillation (C1 = C2 = 47pF) Min. Typ. Max. Unit IDD1 31 50 mA IDD2 Power supply current∗4 VDD 40 100 µA SLEEP mode VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation 2.5 10 mA IDDS1 IDDS2 8 30 µA IDDS3 10 µA Input capacity CIN PA to PC, PE0 to PE5, Clock 1MHz PF, PG, 0V for all pins excluding EXTAL, measured pins XTAL, TEX, TX, RST 10 20 pF ∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗2 PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current when no resistance has been selected. ∗3 When incorporated pull-down resistance has been selected through mask option. ∗4 When all pins are open. – 13 – CXP82940/82948/82952/82960 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input pulse width Event count input rise time, fall time Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 4tsys∗ Min. 1 28 Typ. Max. 16 Unit MHz ns tXL tXH tCR tCF tEH tEL tER tEF fC 200 ns ns 20 ms 32.768 kHz tTL tTH tTR tTF µs ms ∗ tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control clock registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc EXTAL VDD – 0.4V 0.4V tXH tCF tXL tCR 32kHz clock applied condition Crystal oscillation Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation External clock EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HC04 C1 C2 Fig. 3. Event count clock timing TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR – 14 – CXP82940/82948/82952/82960 (2) Serial transfer (CH0) Item CS ↓ → SCK delay time CS ↑ → SCK float delay time CS ↓ → SO delay time CS ↑ → SO float delay time CS High level width SCK cycle time SCK High, Low level width SI input setup time (for SCK ↑) SI input hold time (for SCK ↑) SCK ↓ → SO delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 tsys + 200 2tsys + 200 8000/fc SCK0 tsys + 100 8000/fc – 100 –tsys + 100 200 2tsys + 100 100 SI0 SI0 SO0 Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control clock registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) CS, SCK, SI and SO correspond to each pin of CS0, SCK0, SI0 and SO0. Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. – 15 – CXP82940/82948/82952/82960 Fig. 4. Serial transfer CH0 timing (CH0) tWHCS CSO 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 16 – CXP82940/82948/82952/82960 Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Ouput mode SCK1 Input mode Ouput mode SI1 SCK1 input mode SCK1 ouput mode SCK1 input mode SI1 SCK1 ouput mode SCK1 input mode SO1 SCK1 ouput mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 50 100 200 tsys + 200 100 tsys + 200 100 ns ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control clock registor (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing (SIO mode) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 17 – CXP82940/82948/82952/82960 Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin SO1 SI1 SI1 SI1 2 2 Condition Min. Typ. 104 Max. Unit µs µs µs tLCY∗ tLSU tLHD ∗ tLCY is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1) (SIOM1: address 01E2H) is set to 104µs. Note) The load condition for SO1 is 50pF + 1TTL. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY tLCY SO1 Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD 0.8VDD SI1 Input data bit 0.2VDD – 18 – CXP82940/82948/82952/82960 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage VZT∗1 VFT∗2 Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V –10 4910 160/fADC∗3 12/fADC∗3 AVREF AN0 to AN7 Operation mode AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 0 0.6 AVDD AVREF 1.0 10 10 4970 Symbol Pin Condition Min. Typ. Max. 8 ±3 70 5030 Unit Bits LSB mV mV µs µs V V mA µA tCONV tSAMP VREF VIAN IREF AVREF current Fig. 7. Definition of A/D converter terms FFH FEH Linearity error 01H 00H VZT Analog input VFT ∗1 VZT: Value at which the digital conversion value change from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (address: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (address: 00FEH). CKS PCK1, PCK0 Digital conversion value 0 (φ /2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 (φ selection) fADC = fC fADC = fC/2 fADC = fC/8 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16) – 19 – CXP82940/82948/82952/82960 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit External interruption High, Low level width tIH tIL tRSL 1 µs Reset input Low level width 32/fc µs Fig. 8. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only the falling edge.) 0.2VDD tIL tIH Fig. 9. RST input timing tRSL RST 0.2VDD – 20 – CXP82940/82948/82952/82960 (5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 0∗ 250 1 300 Max. 100 Unit kHz µs µs µs µs µs µs ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗ The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration. Fig.10. I2C bus transfer timing SDA tBUF tR SCL tHD ; STA tSU ; STA P S tLOW tHD ; DAT tHIGH tSU ; DAT St tSU ; STO P tF tHD ; STA Fig.11. Recommended circuit example for I2C device I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C device R S RP RP • Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by CRT flash-over. – 21 – CXP82940/82948/82952/82960 Appendix Fig. 12. Recommended oscillation circuit (i) (ii) EXTAL XTAL Rd TEX TX Rd C1 C2 C1 C2 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd (Ω) Circuit example RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 10.00 12.00 16.00 5 5 0 (i) 0 (i) 0 0 470k (ii) KINSEKI LTD. HC-49/U (-S) P3 32.768kHz Mask Option Table Item Reset pin pull-up resistance High voltage drive output port pull-down resistance Non-existent Non-existent Content Existent Existent (Selectable for each pin) – 22 – CXP82940/82948/82952/82960 Characteristics Curve IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 50 30 20 10 5 1/2 dividing mode 1/4 dividing mode 30 1/2 dividing mode 1/16 dividing mode SLEEP mode IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) IDD – Supply current [mA] IDD – Supply current [mA] 1 0.5 (500µA) 20 1/4 dividing mode 32kHz mode (instruction) 0.1 (100µA) 0.05 (50µA) 0.01 (10µA) 0 1 2 3 4 5 6 7 32kHz SLEEP mode 10 1/16 dividing mode SLEEP mode 0 5 10 15 VDD – Supply voltage [ V ] Frequency [MHz] – 23 – CXP82940/82948/82952/82960 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE ∗QFP080-P-1420-A – 24 – 0.8 ± 0.2 1 24 16.3