CXP832P40A

CXP832P40A CMOS 8-bit Single Chip Microcomputer Description The CXP832P40A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, capture timer counter, LCD controller/driver, remote control reception circuit and 14-bit PWM output besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. Also the CXP832P40A provides sleep/stop function which enables to lower power consumption. The CXP832P40A is the PROM-incorporated version of the CXP83240A with built-in mask ROM. This provides the additional feature of being able to write directry into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) tructure Silicon gate CMOS IC Features • Wide-range instruction system (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 8µs at 500kHz operation 122µs at 32kHz operation • Incorporated PROM capacity 40K bytes • Incorporated RAM capacity 1120 bytes (includes LCD display data area) • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronized type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32kHz timer/counter — LCD controller/driver Maximum 160 segment display possible (during 1/4 duty) 4 common output, 40 segment output Display method static, 1/2, 1/3, 1/4 duty Bias method 1/2, 1/3 bias — Remote control reception circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO — PWM output circuit 14 bits, 1 channel • Interruption 15 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94X39-PP Block Diagram AVSS AVREF INT0 INT1 INT2 NMI/INT3 SEG0 to SEG39 SPC 700 CPU CORE CLOCK GEN/ SYSTEM CONTROL 40 COM0 to COM3 VL VLC1 VLC2 VLC3 PROM 40K BYTES RAM 1120 BYTES LCD CONTROLLER/ DRIVER PORT B 4 PORT A AN0 to AN7 8 A/D CONVERTER TEX TX EXTAL2 XTAL2 EXTAL1 XTAL1 RST VDD VSS 8 PA0 to PA7 8 PB0 to PB7 PWM 14 BIT PWM GENERATOR PORT C 8 PC0 to PC7 PORT D RMC REMOCON FIFO INTERRUPT CONTROLLER CS0 SI0 SO0 SCK0 FIFO 22 PRESCALER/ TIME BASE TIMER SERIAL INTERFACE UNIT 0 PORT E SI1 SO1 SCK1 32KHz TIMER/COUNTER EC0 8 BIT TIMER/COUNTER 0 PORT F ADJ 2 PORT H TO CINT EC1 2 16 BIT CAPTURE TIMER/COUNTER 2 PORT G –2– 8 PD0 to PD7 5 2 PE0 to PE4 PE5 to PE6 SERIAL INTERFACE UNIT 1 8 PF0 to PF7 8 BIT TIMER 1 8 PG0 to PG7 8 PH0 to PH7 CXP832P40A CXP832P40A Pin Assignment (Top View) (QFP package) PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 TEX Vpp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/ CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PA0/AN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG26/PF2 SEG25/PF1 SEG24/PF0 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 TX Vss VDD SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 VLC1 EXTAL2 XTAL2 Note) PA1/AN1 PA2/AN2 1. Vpp (Pin 90) is always connected to VDD. 2. VSS (Pin 41 and 91) are both connected to GND. PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL1 –3– XTAL1 COM0 AVREF AVss VLC3 VLC2 RST Vss VL SEG27/PF3 CXP832P40A Pin Assignment (Top View) (LQFP package) PE3/INT3/NMI PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 PE2/INT2 TEX Vpp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 TX Vss VDD SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 SEG27/PF3 SEG26/PF2 SEG25/PF1 COM1 EXTAL2 XTAL2 Note) PA0/AN0 PA1/AN1 1. Vpp (Pin 88) is always connected to VDD. 2. VSS (Pin 39 and 89) are both connected to GND. PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 –4– EXTAL1 XTAL1 COM0 COM2 AVss AVREF VLC3 VLC2 VLC1 RST PH6 PH7 Vss VL SEG24/PF0 CXP832P40A Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions PA0/AN0 to PA7/AN7 I/O/Analog input Analog inputs to A/D converter. (8 pins) PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/input I/O/Output External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a single bit unit. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) External interruption request inputs. (4 pins) Non-maskable interruption request input. Remote control reception circuit input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter (duty output 50%). Output for 32kHz oscillation frequency division. PC0 to PC7 I/O PE0/INT0/ EC0 PE1/INT1/ EC1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5/PWM PE6/TO/ ADJ Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Output/Output Output/Output/ Output PH0 to PH7 I/O (Port H) 8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) –5– CXP832P40A Symbol PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 PG0/SEG32 to PG7/SEG39 I/O Output/Output (Port D) 8-bit output port. (8 pins) (Port F) 8-bit output port. (8 pins) (port G) 8-bit output port. (8 pins) LCD segment signal output. LCD common signal output. LCD bias power supply. Output Input Functions Output/Output LCD segment signal output. Output/Output SEG0 to SEG15 Output COM0 to COM3 Output VLC1 to VLC3 VL EXTAL1 XTAL1 EXTAL2 XTAL2 TEX TX RST Vpp AVREF AVSS VDD VSS Input Input Output Input Input Control pin to cut off the current flowing to external LCD bias resistor during standby. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL1; opposite phase clock should be input to XTAL1. System clock oscillation of EXTAL1 and XTAL1 is used for normal operation mode (Max. 10MHz). Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL2; opposite phase clock should be input to XTAL2. System clock oscillation of EXTAL2 and XTAL2 is used for sub clock mode (Typ. 500kHz). Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32.768kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and leave TX open. Low-level active system reset. Positive power supply for built-in PROM writing. Under normal operating conditions, connect to VDD. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND. Two VSS are connected to GND. –6– CXP832P40A I/O Circuit Format for Pins Pin Port A Pull-up resistor "0" when reset Port A data Circuit format ∗ When reset PA0/AN0 to PA7/AN7 Data bus Port A direction "0" when reset IP Input protection circuit Hi-Z RD (Port A) Port A input selection "0" when reset Input multiplexer A/D converter 8 pins Port B Pull-up resistor "0" when reset Port B data ∗ Pull-up transistors approx. 100kΩ ∗ PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Data bus Port B direction "0" when reset Schmitt input RD (Port B) CINT CS0 SI0 SI1 IP Hi-Z 4 pins Port B Pull-up resistor "0" when reset SCK OUT Output enable ∗ Pull-up transistors approx. 100kΩ ∗ PB2/SCK0 PB5/SCK1 Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Schmitt input IP Hi-Z 2 pins SCK in ∗ Pull-up transistors approx. 100kΩ –7– CXP832P40A Pin Port B Pull-up resistor "0" when reset SO Output enable Circuit format When reset ∗ PB4/SO0 PB7/SO1 Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) IP Hi-Z 2 pins Port C Pull-up resistor "0" when reset Port C data ∗ Pull-up transistors approx. 100kΩ ∗2 PC0 to PC7 Port C direction "0" when reset Data bus RD (Port C) ∗1 IP Hi-Z 8 pins Port E PE0/INT0/EC0 PE1/INT1/EC1 PE2/INT2 PE3/INT3/NMI PE4/RMC Schmitt input IP ∗1 Large currentt drive of 12mA possible ∗2 Pull-up transistors approx. 100kΩ INT0/EC0 INT1/EC1 INT2 INT3/NMI RMC Data bus Hi-Z RD (Port E) 5 pins –8– CXP832P40A P in Port E Circuit format When reset PWM Port E output selection PE5/PWM "0" when reset Reset E data Data bus RD (Port E) "1" when reset High level 1 pin Port E Internal reset signal MPX ∗1 Port E data "1" when reset TO ∗2 ADJ16K ADJ2K Port E output selection Port E output selection "00" when reset TO Output enable PE6/TO/ADJ High level (High level with 150kΩ resistor when reset) ∗1 Pull-up transistors approx. 150kΩ. ∗2 ADJ signals are frequency divider outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. 1 pin Port H Pull-up resistor "0" when reset Port H data ∗ PH0 to PH7 Hi-Z Port H direction "0" when reset Data bus RD (Port H) IP 8 pins ∗ Pull-up transistors approx. 100kΩ –9– CXP832P40A Pin Port D Port F PD0 to PD7 PF0 to PF7 PG0 to PG7 Port G PD7 to PD4 by a single bit unit PD3 to PD0 by 4-bit unit PF7 to PF0 PG7 to PG0 by 8-bit unit Circuit format When reset Port data Port/segment output selection "0" when reset Segment driver Segment output (VDD level) 24 pins Segment SEG0 to SEG15 VCH Segment data VDD level VCL 16 pins Common VDD COM0 to COM3 VLC1 VDD level VLC2 4 pins VLC3 VL LCD control (DSP bit) Hi-Z 1 pin "0" when reset – 10 – CXP832P40A Pin Circuit format When reset EXTAL1 XTAL1 EXTAL1 IP IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop. XTAL1 becomes "High" level. Oscillation 2 pins XTAL1 EXTAL2 XTAL2 IP EXTAL2 IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop. XTAL2 becomes "High" level. EXTAL2 Hi-Z XTAL2 High level 2 pins XTAL2 TEX TX TEX IP IP • Diagram shows circuit composition during oscillation. 2 pins TX • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and TEX and TX become "Low" level and "High" level respectively. Oscillation Pull-up resistor RST OP Mask option IP Low level Schmitt input 1 pin – 11 – CXP832P40A Absolute Maximum Ratings Iem VDD Supply voltage Vpp AVSS LCD bias voltage Input voltage Output voltage High level output current VLC1, VLC2, VLC3 VIN VOUT IOH Symbol Rating –0.3 to +7.0 –0.3 to +13.0 –0.3 to +0.3 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –5 –50 15 20 100 –10 to +75 –55 to +150 600 Unit V V V V V V mA mA mA mA mA °C °C mW QFP package Output per pin Total for all output pins Incorporated PROM Remarks (Vss = 0V) High level total output current ∑IOH Low level output current IOL IOLC Value per pin, excluding large current outputs Value per pin∗2 for large current outputs Total for all output pins Low level total output current ∑IOL Operating temperature Storage temperature Topr Tstg Allowable power dissipation PD 380 LQFP package ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 12 – CXP832P40A Recommended Operating Conditions Item Symbol Min. 4.5 3.5 VDD Supply voltage 3.0 2.7 2.5 Vpp VLC1 LCD bias voltage VLC2 VLC3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD VDD VDD V V V V V V °C ∗2 Hysteresis input∗3 EXTAL∗4 ∗2 Hysteresis input∗3 EXTAL∗4 Vss VDD V LCD power supply range∗5 Max. 5.5 5.5 5.5 5.5 5.5 V V Unit Remarks (Vss = 0V) High-speed mode guaranteed operation range∗1 Low-speed mode guaranteed operation range∗1 Guaranteed operation range during EXTAL2 clock (sub clock mode) Guaranteed operation range with TEX clock Guaranteed data hold range during STOP ∗6 Vpp = VDD VDD – 0.4 VDD + 0.3 0 0 –0.3 –10 0.3VDD 0.2VDD 0.4 +75 ∗1 During EXTAL1 clock (main clock mode), high-speed mode is 1/2 frequency division clock selection; lowspeed mode is 1/16 frequency division clock selection. ∗2 Value for each pin of normal input ports (PA, PB4, PB7, PC and PH). ∗3 Value of the following pins; RST, CINT CS0, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, NMI/INT3, and RMC. ∗4 Specifies only during external clock input. ∗5 Optimal values are determined by LCD used. ∗6 Vpp and VDD should be set to same voltage. – 13 – CXP832P40A Electrical Characteristics DC Characteristics Item High level output voltage Symbol VOH Pins PA, PB, PC, PD∗1, PE5, PE6 PF to PG∗1 VL (VOL only) PC IIHE1 IILE1 IIHE2 IILE2 Input current IIHT IILT IILR IIH IIL I/O leakage current Common output impedance Segment output impedance IIZ TEX RST∗2 PA to PC∗3, PH∗3 PE0 to PE4, RST∗2 COM0 to COM3 SEG0 to SEG15 SEG16 to SEG39∗1 EXTAL2 EXTAL1 Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V 3 VDD = 5V, VLC1 = 3.75V, VLC2 = 2.5V, VLC3 = 1.25V 0.5 –0.5 0.3 –0.3 0.1 –0.1 –1.5 –3.33 –50 ±10 (Ta = –10 to +75°C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 30 –30 10 –10 –400 Typ. Max. Unit V V V V V µA µA µA µA µA µA µA µA µA µA kΩ Low level VOL output voltage RCOM 5 RSEG 5 15 kΩ IDD1 High-speed mode operation (1/2 frequency division clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) 20 45 mA IDD2 IDD3 Supply current∗4 VDD = 3.5V, 500kHz crystal oscillation (C1 = C2 = 22pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) SLEEP mode VDD 2.0 0.6 3.8 1.3 mA mA IDDS1 VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.5V, 500kHz crystal oscillation (C1 = C2 = 22pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode VDD = 5.5V, 10MHz, 500kHz crystal oscillation and termination of 32kHz oscillation – 14 – 1.5 8 mA IDDS2 IDDS3 0.5 9 1.0 30 mA µA IDDSS 30 µA CXP832P40A Item Symbol Pins Pins other than PB7, PE5, PE6 VLC1 to VLC3 COM0 to COM3 SEG0 to SEG15 PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 PG0/SEG32 to PG7/SEG39 AVREF, AVSS, VDD, VSS Conditions Min. Typ. Max. Unit Input capacity CIN Clock 1MHz 0V for all pins excluding measured pins 10 20 pF ∗1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PG0/SEG32 to PG7/SEG39, PD, PF and PG are the case when the common pin is selected as port; SEG16 to SEG39 are when the common pin is selected as segment output. ∗2 RST specifies the input current when pull-up resitor has been selected; leakage current when no resistor has been selected. ∗3 PA to PC, and PH specify the input current when a pull-up resistor has been selected; leakage current when no resistor has been selected. (PE0 to PE4 specify the leakage current.) ∗4 When all output pins are left open. – 15 – CXP832P40A AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall time System clock frequency Symbol fC Pin XTAL1 EXTAL1 EXTAL1 EXTAL1 XTAL2 EXTAL2 EXTAL2 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 external clock drive Fig. 1, Fig. 2 external clock drive VDD = 3.0 to 5.5V Fig. 1, Fig. 2 VDD = 3.0 to 5.5V Fig. 1, Fig. 2 external clock drive VDD = 3.0 to 5.5V Fig. 1, Fig. 2 external clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 0.3 0.5 Min. 1 37.5 200 0.7 Typ. Max. 10 Unit MHz ns ns MHz tXL, tXH tCR, tCF fC System clock input pulse width tXL, tXH tCR, tCF tEH, tEL tER, tEF fC 450 ns System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time EXTAL2 EC0 EC1 EC0 EC1 TEX TX TEX TEX 200 ns tsys + 50∗ 20 ns ms 32.768 kHz tTL, tTH tTR, tTF µs ms ∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”). Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL1 EXTAL2 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HC04 C1 C2 – 16 – CXP832P40A Fig. 3. Event count clock timing TEX EC0 EC1 tEH tTH tEF tTF tEL tTL tER tTR 0.8VDD 0.2VDD (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 float delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 float delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input setup time (for SCK0 ↑) SI0 input hold time (for SCK0 ↑) SCK0 ↓ → SO0 delay time Symbol Pin SCK0 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 tsys + 100 8000/fc – 50 100 200 SI0 SI0 tsys + 200 100 tsys + 200 100 ns ns SO0 Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 17 – CXP832P40A Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 18 – CXP832P40A Serial Transfer (CH1) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode SCK1 input mode Output mode SI1 SCK1 input mode SCK1 output mode SI1 SCK1 input mode SCK1 output mode SO1 SCK1 input mode SCK1 output mode Min. 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load condition for the SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 19 – CXP832P40A (3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT∗1 VFT∗2 Symbol Pin (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = AVSS = 0V) Conditions Min. Typ. Max. 8 ±3 Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V –10 4910 160/fADC∗3 12/fADC∗3 10 4970 70 5030 Unit Bits LSB mV mV µs µs VDD AVREF 0.6 1.0 10 V V mA µA tCONV tSAMP AVREF AN0 to AN7 Operation mode AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VIAN IREF Reference input voltage VREF Analog input voltage VDD – 0.5 0 AVREF current Fig. 6. Definition of A/D converter terms FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to the Bit 6 (CKS) of A/D control register (address: 00F9H) and the Bit 7 (PCK1) and Bit 6 (PCK0) of clock control register (address: 00FFH). CKS PCK1, PCK0 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16) 0 (φ/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 (φ selection) fADC = fC fADC = fC/2 fADC = fC/8 – 20 – CXP832P40A (4) Interruption, reset input Item External interruption high and low level widths Reset input low level width Syymbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 NMI/INT3 RST Conditions Min. Max. Unit tIH tIL tRSL 1 µs 32/fc µs Fig. 7. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI specifies only for the falling edge) 0.2VDD tIL tIH Fig. 8. RST input timing tRSL RST 0.2VDD – 21 – CXP832P40A Appendix Fig. 9. SPC700 series recommended oscillation circuit (i) Main clock 500kHz sub clock (ii) Main clock 500kHz sub clock (iii) 32kHz sub clock EXTAL XTAL Rd EXTAL XTAL Rd ETEX XTAL XTAL TX Rd C1 C2 C 1 C2 C1 C2 Manufacturer Model CSA4.19MG CSA8.00MG fc (MHz) 4.19 8.00 10.00 C1 (pF) C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 (ii) MURATA MFG CO., LTD. CSA10.0MT CST4.19MGW∗ CST8.00MTW∗ CST10.00MTW∗ 4.19 8.00 10.00 4.19 2.2k 470 22 18 22 18 560 0 (i) RIVER ELETEC CO., LTD. HC-49/U03 8.00 10.00 4.19 15 15 KINSEKI LTD. HC-49/U (-S) 8.00 10.00 Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Selection Guide Option item Product name Package Mask product CXP83120A CXP83124A CXP83232A CXP83240A Incorporated PROM product CXP832P40AQ1CXP832P40AR1- 100-pin plastic QFP/LQFP 100-pin plastic QFP 100-pin plastic LQFP PROM 40K bytes Existent Existent ROM capacitance 20K bytes 24K bytes 32K bytes 40K bytes Reset pin pull-up resistor Existent/Non-existent – 22 – CXP832P40A Characteristics Curves IDD vs. VDD (Ta = 25°C, typical) 20.0 10.0 5.0 32kHz mode (Instruction) fc = 10MHz main clock 1/2 frequency dividing mode fc = 500kHz sub clock 1/2 frequency dividing mode 20 IDD vs. fc (VDD = 5V, Ta = 25°C, typical) Main clock 1/2 frequency dividing mode IDD – Supply current [mA] IDD – Supply current [mA] fc = 10MHz main clock SLEEP mode 1.0 0.5 fc = 500kHz sub clock SLEEP mode 15 10 0.1 (100µA) 0.05 (50µA) 32kHz SLEEP mode 5 Main clock SLEEP mode 2 3 4 5 6 7 0 5 10 1 5 0.01 (10µA) VDD – Supply voltage [V] fc – System clock [MHz] – 23 – CXP832P40A Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 26 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 ∗QFP100-P-1414-A – 24 – 0.5 ± 0.2 A (15.0)