CXP84540

CXP84540/84548 CMOS 8-bit Single Chip Microcomputer Description The CXP84540/84548 is a CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, capture timer/counter, PWM output and the like besides the basic configurations of 8-bit CPU, ROM, RAM and I/O port. The CXP84540/84548 also provide a sleep/stop functions that enable to execute the power-on reset function or lower the power consumption. 80 pin QFP (Plastic) 80 pin LQFP (Plastic) 80 pin LFLGA (Plastic) Features • Wide range instruction system (213 instructions) which covers various of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) 200ns at 20kHz operation (3.0 to 5.5V) • Incorporated ROM capacity 40K bytes (CXP84540) 48K bytes (CXP84548) • Incorporated RAM capacity 1472 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93µs / at 28MHz, 2.7µs / at 20MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes, latch output function, MSB/LSB first selectable), 1 channel 8-bit clock syncronization, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture time/counter — PWM output 8 bits, 2 channels • Interruption 14 factors, 14 vectors, multi-interruption possible • Standby mode Sleep/Stop • Package 80-pin plastic QFP/LQFP 80-pin plastic LFLGA • Piggyback/evaluator CXP84500 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96528B9X-PS Block Diagram AVREF NMI EXTAL XTAL RST VDD Vss AVss INT0 INT1 INT2 INT3 AN0 to AN7 SPC700 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROL 8 A/D CONVERTER 8 PA0 to PA7 PWM0 8-BIT PWM GENERATOR 0 8 PB0 to PB7 PWM1 8-BIT PWM GENERATOR 1 8 PC0 to PC7 INTERRUPT CONTROLLER ROM 40K/48K BYTES RAM 1472 BYTES 8 4 4 PD0 to PD7 PE0 to PE3 PE4 to PE7 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A –2– FIFO PRESCALER/ TIME BASE TIMER 2 2 CS0 SI0 SO0 SCK0 LAT0 SERIAL INTERFACE UNIT (CH0) SI1 SO1 SCK1 SERIAL INTERFACE UNIT (CH1) 8 PF0 to PF7 8 PG0 to PG7 EC0 8-BIT TIMER/COUNTER 0 8-BIT TIMER 1 8 PH0 to PH7 TO CINT EC1 16-BIT CAPTURE TIMER/COUNTER 2 8 PI0 to PI7 CXP84540/84548 CXP84540/84548 Pin Assignment (Top View) 80-pin QFP package PG7 PG6 PG5 PG4 PG3 PG2 PG1 PF2 PF1 PG0 PF0 VDD PI7 PI6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/PWM1 PE4/PWM0 PE3/NMI PE2/CINT PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/LAT0 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA0/AN0 Note) NC (Pin 73) is left open. However, this pin is used for the Flash EEPROM incorporated version (CXP845F60). –3– PA1/AN1 PA2/AN2 PH3 PH4 PH5 PH6 PH7 RST EXTAL XTAL VSS PE6 PE7 AVSS AVREF PI5 NC CXP84540/84548 Pin Assignment (Top View) 80-pin LQFP package PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 VDD PG3 PG2 PG1 PG0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC PI7 PI6 PI5 PI4 PI3/INT3 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/PWM1 PE4/PWM0 PE3/NMI PE2/CINT PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/LAT0 PA7/AN7 PA6/AN6 PA5/AN5 Note) NC (Pin 73) is left open. –4– PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 EXTAL AVREF XTAL AVSS RST PH1 PH2 PH3 PH4 PH5 PH6 PH7 PE6 PE7 VSS CXP84540/84548 Pin Assignment (Top View) 80-pin LFLGA package 80 PF4 78 PF2 75 PG7 72 PG4 69 PG3 67 PG1 65 PI7 62 PI4 2 PF6 1 PF5 79 PF3 76 PF0 73 PG5 70 VDD 66 PG0 63 PI5 61 PI3 60 PI2 5 PD1 3 PF7 4 PD0 77 PF1 74 PG6 71 NC 68 PG2 64 PI6 59 PI1 58 PI0 7 PD3 6 PD2 8 PD4 57 PE5 56 PE4 55 PE3 9 PD5 10 PD6 11 PD7 54 PE2 53 PE1 52 PE0 12 PC0 13 PC1 14 PC2 51 PB7 50 PB6 49 PB5 15 PC3 16 PC4 17 PC5 48 PB4 46 PB2 47 PB3 18 PC6 19 PC7 24 PH4 28 RST 31 VSS 34 AVSS 37 PA1 44 PB0 43 PA7 45 PB1 20 PH0 21 PH1 23 PH3 26 PH6 30 XTAL 33 PE7 36 PA0 39 PA3 41 PA5 42 PA6 22 PH2 25 PH5 27 PH7 29 32 35 38 40 PA4 EXTAL PE6 AVREF PA2 Note) NC (Pin 71) is left open. –5– CXP84540/84548 Pin Description Symbol I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the Analog inputs to A/D converter. pull-up resistance can be (8 pins) set through the software in a unit of 4 bits. (8 pins) Latch output for serial interface (CH0). (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) Capture trigger input. Non-maskable interruption request input. 8-bit PWM0 output. Rectangular wave output for 16-bit timer/ counter and 8-bit PWM1 output. PA0/AN0 to PA7/AN7 I/O/Analog input PB0/LAT0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/Output I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PC0 to PC7 I/O PD0 to PD7 I/O PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI PE4/PWM0 PE5/TO/ PWM1 PE6 PE7 Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output/ Output Output Output PF0 to PF7 I/O (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) –6– CXP84540/84548 Symbol I/O Description (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins) PG0 to PG7 I/O PH0 to PH7 I/O PI0/INT0 to PI3/INT3 PI4 to PI7 EXTAL XTAL RST I/O/Input I/O Input Output I/O Crystal connectors for system clock oscillation. When the clock is supplied externally, input it to EXTAL; opposite phase clock should be input to XTAL. System reset for active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. (Mask option) No connected. Leave this pin open. However, this is used for the Flash EEPROM incorporated version (CXP845F60). NC AVREF AVss VDD Vss Input Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND –7– CXP84540/84548 Input/Output Circuit Formats for Pins Pin Port A Pull-up resistor "0" when reset Port A data Circuit format ∗ When reset PA0/AN0 to PA7/AN7 Port A direction "0" when reset Data bus RD (Port A) Port A function selection "0" when reset A/D converter IP Input protection circuit Hi-Z Input multiplexer ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 8 pins Port B Pull-up resistor "0" when reset LAT0 Latch output enable ∗ PB0/LAT0 Port B data IP Port B direction "0" when reset Data bus RD (Port B) ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) Hi-Z 1 pin Port B Pull-up resistor "0" when reset Port B data ∗ PB1/CS0 PB3/SI0 PB6/SI1 Port B direction "0" when reset Data bus RD (Port B) CS0 SI0 SI1 Schmitt input IP Hi-Z 3 pins ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) –8– CXP84540/84548 Pin Port B Pull-up resistor "0" when reset SCK OUT Serial clock output enable Port B function selection "0" when reset Port B data Port B direction "0" when reset Circuit format ∗ When reset PB2/SCK0 PB5/SCK1 IP Hi-Z Data bus RD (Port B) Schmitt input 2 pins Port B SCK0, SCK1 in ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) Pull-up resistor SO Serial data output enable Port B function selection ∗ PB4/SO0 PB7/SO1 "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) IP Hi-Z 2 pins Port C Pull-up resistor "0" when reset Port C data ∗2 PC0 to PC7 Port C direction "0" when reset Data bus RD (Port C) ∗1 IP Hi-Z 8 pins –9– ∗1 Large current drive (12mA: VDD = 4.5 to 5.5V) ( 5mA: VDD = 3.0 to 3.6V) ∗2 Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) CXP84540/84548 Pin Port E PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI 4 pins Port E Circuit format When reset Schmitt input IP EC0, EC1 CINT, NMI Data bus RD (Port E) Hi-Z PWM0 Port E function selection "0" when reset Port E data "1" when reset PE4/PWM0 High level 1 pin Port E Data bus RD (Port E) Internal reset signal Port E data "1" when reset TO PWM1 00 MPX 01 1x ∗ PE5/TO/ PWM1 Port E function selection (upper) Port E function selection (lower) "00" when reset TO output enable ∗ Pull-up transistor approx. 150kΩ (VDD = 4.5 to 5.5V) approx. 400kΩ (VDD = 3.0 to 3.6V) ( High level with resistor of pull-up transistor ON for reset ) 1 pin Port E Port E data PE6, PE7 "0" when reset Low level Data bus 2 pins RD (Port E) – 10 – CXP84540/84548 Pin Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 Port I Pull-up resistor "0" when reset Circuit format ∗ When reset Ports D, F, G, I data Ports D, F, G, I direction "0" when reset Data bus RD IP Hi-Z 28 pins Port H ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) Pull-up resistor "0" when reset Port H data ∗ PH0 to PH7 Port H direction "0" when reset Data bus RD (Port H) Standby release Edge detection ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) IP Hi-Z 8 pins Port I Pull-up resistor "0" when reset Port I data ∗ PI0/INT0 to PI3/INT3 Data bus Port I direction "0" when reset Schmitt input RD INT0 INT1 INT2 INT3 IP Hi-Z 4 pins – 11 – ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) CXP84540/84548 Pin Circuit format When reset EXTAL XTAL • Diagram shows the circuit composition during oscillation. EXTAL IP IP • Feedback resistor is removed during stop mode and XTAL becomes High level. Oscillation 2 pins XTAL Pull-up resistor RST Mask option OP IP Schmitt input Low level From power-on reset circuit (Mask option) 1 pin – 12 – CXP84540/84548 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage High level output current High level total output current Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg Symbol VDD AVSS VIN VOUT IOH ∑IOH IOL Ratings –0.3 to +7.0 –0.3 to +0.3 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –5 –50 15 20 100 –20 to +75 –55 to +150 600 PD 380 500 Unit V V V V mA mA mA mA mA °C °C mW mW mW QFP-80P-L01 LQFP-80P-L01 LFLGA-80P-02 Output (value per pin) (Vss = 0V reference) Remarks Total of all output pins Pins excluding large current outputs (value per pin) Large current outputs (value per pin∗2) Total of all output pins ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 (3.0) Supply voltage∗1 VDD 3.5 (2.7) 2.0 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature ∗1 ∗2 ∗3 ∗4 VILS VILEX Topr 0.7VDD 0.8VDD 0.9VDD 0 0 –0.3 –20 Max. 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.1VDD +75 V V V V V V °C V Unit (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock and sleep mode Guaranteed data hold range during stop mode ∗2 Hysteresis input∗3 EXTAL∗4 ∗2 Hysteresis input∗3 EXTAL∗4 Specifies values in parenthesis for 1 to 20MHz system clock operation. Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7) RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3 Specifies only during external clock input. – 13 – CXP84540/84548 Electrical Characteristics DC Characteristics (VDD 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins Conditions (Ta = –20 to +75°C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.1 –0.1 –1.5 VDD = 5.5V, VIL = 4.0V VDD = 4.5V, VIL = 4.0V VDD = 5.5V, VI = 0, 5.5V 1/2 frequency dividing clock operation VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) Sleep mode VDD IDDS2 VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) Stop mode IDDS3 PA to PD, PE0 to PE3, PF to PI, EXTAL, RST VDD = 5.5V, termination of 28MHz crystal oscillation 10 µA 4.0 10 mA 28 58 mA –2.78 25 –25 –400 –50 Typ. Max. Unit V V V V V µA µA µA µA µA VOL VDD = 4.5V, IOH = –0.5mA PA to PD, VDD = 4.5V, IOH = –1.2mA PE4 to PE7, PF to PI, VDD = 4.5V, IOL = 1.8mA RST (only VOL)∗1 VDD = 4.5V, IOL = 3.6mA PC VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V EXTAL RST∗2 PA to PD∗3 PF to PI∗3 PA to PD∗3 PF to PI∗3 PE0 to PE3, RST∗2 VDD = 5.5V, VIL = 0.4V IIHE IILE Input current IILR IIL I/O leakage current IIZ ±10 µA IDD1 IDD2 Supply current ∗4 IDDS1 Input capacity CIN Clock 1MHz 0V for no-measured pins 10 20 pF ∗1 Specifies RST pin when the power-on reset circuit is selected with mask option. ∗2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗4 When all pins are open. – 14 – CXP84540/84548 DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH Pins Conditions (Ta = –20 to +75°C, VSS = 0V reference) Min. 2.7 2.3 0.3 0.5 1.0 0.05 –0.05 –0.7 VDD = 3.6V, VIL = 2.7V VDD = 3.0V, VIL = 2.7V VDD = 3.6V, VI = 0, 3.6V 1/2 frequency dividing clock operation VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Sleep mode 13.5 30 mA –1.0 15 –15 –200 –30 Typ. Max. Unit V V V V V µA µA µA µA µA VOL VDD = 3.0V, IOH = –0.15mA PA to PD, VDD = 3.0V, IOH = –0.5mA PE4 to PE7, PF to PI, VDD = 3.0V, IOL = 1.2mA RST (only VOL)∗1 VDD = 3.0V, IOL = 1.6mA PC VDD = 3.0V, IOL = 5mA VDD = 3.6V, VIH = 3.6V EXTAL RST∗2 PA to PD∗3 PF to PI∗3 PA to PD∗3 PF to PI∗3 PE0 to PE3, RST∗2 VDD = 3.6V, VIL = 0.3V IIHE IILE Input current IILR IIL I/O leakage current IIZ ±5 µA IDD1 IDD2 Supply current∗4 IDDS1 VDD IDDS2 VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Stop mode 1.2 4.0 mA IDDS3 VDD = 3.6V, termination of 20MHz crystal oscillation 5 µA ∗1 Specifies RST pin when the power-on reset circuit is selected with mask option. ∗2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗4 When all pins are open. – 15 – CXP84540/84548 AC Characteristics (1) Clock timing Item System clock frequency Symbol fC Pin (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Conditions Min. 1 1 15.6 23 100 ns ns ns 20 ns Typ. Max. Unit 28 20 MHz VDD = 4.5 to 5.5V XTAL Fig. 1, Fig. 2 EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time tXL, tXH tCR, tCF tEH, tEL tER, tEF tsys + 50∗1 ∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation External clock EXTAL XTAL EXTAL XTAL C1 C2 74HC04 Fig. 2. Clock applied conditions 0.8VDD EC0 EC1 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR Fig. 3. Event count clock timing – 16 – CXP84540/84548 (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 float delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level widths SI0 input setup time (for SCK0 ↑) SI0 input hold time (for SCK0 ↑) SCK0 ↓ → SO0 delay time SCK0 ↓ → LAT0 output delay time LAT0 data pulse width Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Latch output mode (SCK0 = output mode) Latch output mode (SCK0 = output mode) Min. Max. 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 tsys + 150 2tsys + 200 8000/fc SCK0 tsys + 90 4000/fc – 25 50 100 SI0 SI0 tsys + 100 50 SO0 tsys + 100 50 ns ns ns ns tLADLY LAT0 tLAPLS LAT0 tKCY tKCY – 10 tKCY + 50 tKCY + 50 Note 1) tsys indicates three values according to the ccontents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 17 – CXP84540/84548 Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 float delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level widths SI0 input setup time (for SCK0 ↑) SI0 input hold time (for SCK0 ↑) SCK0 ↓ → SO0 delay time SCK0 ↓ → LAT0 output delay time LAT0 data pulse width Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Latch output mode (SCK0 = output mode) Latch output mode (SCK0 = output mode) Min. Max. 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 8000/fc tsys + 80 4000/fc – 50 80 150 tsys + 120 70 tsys + 200 80 ns ns ns ns tLADLY LAT0 tLAPLS LAT0 tKCY tKCY – 10 tKCY + 100 tKCY + 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 18 – CXP84540/84548 tWHCS 0.8VDD CS0 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD tLADLY tLAPLS 0.8VDD 0.8VDD LAT0 Fig. 4. Serial transfer CH0 timing – 19 – CXP84540/84548 (3) Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level widths SI1 input set-up time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode Min. 500 8000/fc 200 4000/fc – 25 50 100 100 50 100 50 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK1 SI1 SI1 SO1 Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference) Item SCK1 cycle time SCK1 High, Low level widths SI1 input set-up time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 Condition Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode Min. 700 8000/fc 300 4000/fc – 50 70 150 150 70 150 80 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK1 SI1 SI1 SO1 Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF. – 20 – CXP84540/84548 tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data Fig. 5. Serial transfer CH1 timing – 21 – CXP84540/84548 (4) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT∗1 VFT∗2 Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V –10 4910 27/fADC∗3 6/fADC∗3 AVREF AN0 to AN7 Operation mode AVREF Sleep mode Stop mode VDD – 0.5 0 0.6 VDD AVREF 1.0 10 10 4970 Symbol Pin Condition Min. Typ. Max. 8 ±4 70 5030 Unit Bits LSB mV mV µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT∗1 VFT∗2 Ta = 25°C VDD = AVREF = 3.3V VSS = AVSS = 0V –10 3216 27/fADC∗3 6/fADC∗3 AVREF AN0 to AN7 Operation mode AVREF Sleep mode Stop mode VDD – 0.3 0 0.4 VDD AVREF 0.7 5 6.5 3280.5 Symbol Pin Condition Min. Typ. Max. 8 ±5 70 3345 Unit Bits LSB mV mV µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS FFh FEh Linearity error 01h 00h VZT Analog input VFT ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h). fADC = fc (CKS = "0"), fc/2 (CKS = "1") However, the selection for fADC = fc (CKS = "0") is limited in the clock range of fc = 1 to 14MHz (VDD 4.5 to 5.5V) and fc = 1 to 10MHz (VDD = 3.0 to 4.5V). – 22 – Fig. 6. Definition of A/D converter terms Digital conversion value CXP84540/84548 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST tIH Condition Min. Max. Unit External interruption High, Low level widths tIH tIL tRSL 1 µs Reset input Low level width 32/fc tIL µs INT0 INT1 INT2 INT3 NMI (Specifies NMI only for the falling edge.) 0.8VDD 0.2VDD tIL tIH 0.8VDD 0.2VDD Fig 7. Interruption input timing tRSL RST 0.2VDD Fig. 8. RST input timing (5) Power-on reset∗1 Item Power supply rise time Power supply cut-off time Symbol Pin VDD (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Condition Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF ∗1 Specifies only when the power-on reset function is selected. Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V. 4.5V VDD 0.2V 0.2V tR Take care when turning the power on. tOFF Fig. 9. Power-on reset – 23 – CXP84540/84548 Appendix (i) Main clock (ii) Main clock EXTAL XTAL Rd EXTAL XTAL Rd C1 C2 C1 C2 Fig. 10. SPC700 Series recommended oscillation circuit Manufacturer Model CSA8.00MTZ CSA10.0MTZ CSA12.00MTZ CST8.00MTW∗ fc (MHz) 8.00 10.00 12.00 8.00 10.00 12.00 16.00 16.00 20.00 24.00 28.00 20.00 24.00 28.00 28.00 C1 (pF) C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 (ii) MURATA MFG CO., LTD. CST10.0MT∗ CST12.0MTW∗ CSA16.00MXZ040 CST16.00MXZ0C1∗ CSA20.00MXZ040 CSA24.00MXZ040 CSA28.00MXZ040 CCR20.0MC6∗ 5 5 OPEN 3 3 16 16 1 1 5 5 OPEN 3 3 16 16 1 1 0 0 0 0 0 0 0 220 220 (i) (ii) (i) TDK CORPORATION. CCR24.0MC6∗ KINSEKI LTD. HC49/U-S CX-11F (ii) (i) Models with an asterisk (∗) have the built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistor Power-on reset circuit ∗1 Contents Non-existent Non-existent Existent Existent ∗1 "Existent" for power-on reset circuit cannot be selected when the supply voltage VDD of 3.0 to 4.5V. – 24 – CXP84540/84548 Characteristics Curves IDD vs. VDD (fc = 28MHz, Ta = 25°C, Typical) 20.0 10.0 5.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode Sleep mode 20 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode IDD – Supply current [mA] 1.0 0.5 IDD – Supply current [mA] 15 1/4 dividing mode 10 0.1 (100µA) 0.05 (50µA) Stop mode 1/16 dividing mode 5 0.01 (10µA) 2 3 4 5 6 7 0 10 20 fc – System clock [MHz] Sleep mode 30 VDD – Supply voltage [V] IDD vs. VDD (fc = 20MHz, Ta = 25°C, Typical) 20.0 10.0 5.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20 IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) IDD – Supply current [mA] 1.0 0.5 IDD – Supply current [mA] Sleep mode 15 1/2 dividing mode 10 0.1 (100µA) 0.05 (50µA) 1/4 dividing mode 5 0.01 (10µA) 2 3 4 5 6 7 0 1/16 dividing mode Sleep mode 10 20 fc – System clock [MHz] 30 VDD – Supply voltage [V] – 25 – CXP84540/84548 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 80PIN LQFP (PLASTIC) 14.0 ± 0.2 ∗ 60 61 12.0 ± 0.1 41 40 A 80 1 + 0.08 0.18 – 0.03 20 21 (0.22) 0.5 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0.5 ± 0.2 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 LQFP080-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g – 26 – 0.5 ± 0.2 (13.0) 0.8 ± 0.2 1 24 16.3 CXP84540/84548 Package Outline Unit: mm 80PIN LFLGA 0.2 SA 9.0 PIN 1 INDEX 1.4MAX 0.10MAX 9.0 x4 0.15 S 3 – φ0.50 80 – φ0.40 ± 0.05 A φ0.08 M S A B 0.2 0.2 S SB 0.3 0.8 DETAIL X 0.3 K J H G F E D C B A B 0.4 0.3 0.5 0.5 0.3 0.9 0.4 0.9 1 2 3 4 5 6 7 8 9 10 0.8 PAC KAGE STRUC TURE PA CKA GE MA TERIA L ORGA NIC SUBSTRA TE GOLD PLA TING NICKEL PLA TING 0.3g SONY CODE EIA J CODE JEDEC CODE LFLGA -80P-02 P-LFLGA 80-9x9-0.8 TERMINA L TREA TMENT TERMINA L MA TERIA L PA CKA GE MA SS – 27 – 0.10 S X