CXP847P60

CXP847P60 CMOS 8-bit Single Chip Microcomputer Description The CXP847P60 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, FRC capture unit, highprecision timing pattern generation circuit, PWM output, and the like besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O ports. The CXP847P60 also provides the sleep/stop functions that enable to execute the power-on reset function and lower the power consumption. The CXP847P60 is the PROM-incorporated version of the CXP84716/84720/84724 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluaiton use during system development and for small-quantity production. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data. — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (3.0 to 5.5V) • Incorporated PROM capacity 60K bytes • Incorporated RAM capacity 2144 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.6µs at 16MHz) — Serial interface Srart-stop synchronization (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels 8-bit clock syncronization (MSB/LSB first selectable), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter — FRC capture unit Incorporated 24-bit and 6-stage FIFO — High-precision timing pattern generation circuit PPG: maximum of 11 pins, 16 stages programmable, 2 channels — PWM output 8 bits, 8 channels • Interruption 19 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97119-PS Block Diagram AVDD NMI INT0 INT1 INT2 INT3 INT4 EXTAL XTAL RST VDD VSS AVSS AVREF AN0 to AN7 8 SPC 700 CPU CORE 8 CLOCK GENERATOR/ SYSTEM CONTROL 8 A/D CONVERTER NMI PA0 to PA7 RxD TxD UART RECEIVER UART TRANSMITTER PB0 to PB7 UART BAUD RATE GENERATOR PWM0 PWM1 PROM 60K BYTES RAM 2144 BYTES 8 BIT PWM GENERATOR 0 8 PC0 to PC7 8 BIT PWM GENERATOR 1 PWM2 PWM3 8 BIT PWM GENERATOR 2 8 BIT PWM GENERATOR 3 8 PD0 to PD7 PWM4 8 BIT PWM GENERATOR 4 PWM5 8 BIT PWM GENERATOR 5 6 2 6 PE0 to PE5 PE6 to PE7 PF0 to PF5 PF6 PF7 8 FIFO 2 8 BIT TIMER 1 2 11 TO CINT EC1 16 BIT CAPTURE TIMER/COUNTER 2 11 4 PPO0 to PPO10 PPO11 to PPO21 EXI0 to EXI3 PORT J PROGRAMMABLE PATTERN BUFFER GENERATOR RAM (CH0) PROGRAMMABLE PATTERN BUFFER GENERATOR RAM (CH1) PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A –2– PRESCALER/ TIME BASE TIMER PWM7 8 BIT PWM GENERATOR 7 CS0 SI0 SO0 SCK0 SERIAL INTERFACE UNIT (CH0) BUFFER RAM FRC CAPTURE UNIT INTERRUPT CONTROLLER PWM6 8 BIT PWM GENERATOR 6 PG0 to PG7 CS1 SI1 SO1 SCK1 SERIAL INTERFACE UNIT (CH1) BUFFER RAM 8 PH0 to PH7 SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) EC0 8 PI0 to PI7 8 BIT TIMER/COUNTER 0 8 PJ0 to PJ7 CXP847P60 CXP847P60 Pin Assignment (Top View) 100-pin QFP package PG7/PWM7 PG6/PWM6 PG5/PWM5 PG4/PWM4 PG3/PWM3 PG2/PWM2 PG1/PWM1 PG0/PWM0 PI5/SCK2 PI7/SO2 PF2 PF1 PF0 Vpp VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PF3 PF4 PF5 PF6/TxD PF7/RxD PD0/PPO0 PD1/PPO1 PD2/PPO2 PD3/PPO3 PD4/PPO4 PD5/PPO5 PD6/PPO6 PD7/PPO7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PPO8 PH1/PPO9 PH2/PPO10 PH3/PPO11 PH4/PPO12 PH5/PPO13 PH6/PPO14 PH7/PPO15 PJ0/PPO16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI1/INT1 PI0/INT0 PE7/TO PE6 PE5 PE4 PE3/NMI PE2 PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/CS1 PB3 PB2 PB1 PB0/CINT SO0 SI0 SCK0 CS0 PA7 PA6 PA5 PA4 PA3/AN7 PA2/AN6 PA1/AN5 PA0/AN4 VSS PI6/SI2 PI4/INT4 PI3/INT3 AN2 AVREF Note) 1. Vpp (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. PJ1/PPO17 PJ2/PPO18 PJ3/PPO19 PJ4/PPO20 PJ5/PPO21 PJ6/EXI0 PJ7/EXI1 EXTAL –3– XTAL AVDD AVSS EXI2 EXI3 RST AN0 AN1 AN3 VSS PI2/INT2 CXP847P60 Pin Assignment (Top View) 100-pin LQFP package PG1/PWM1 PG7/PWM7 PG6/PWM6 PG5/PWM5 PG4/PWM4 PG3/PWM3 PG2/PWM2 PG0/PWM0 PI5/SCK2 PI7/SO2 PI4/INT4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PF4 PF3 PF2 PF1 PF0 Vpp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PF5 PF6/TxD PF7/RxD PD0/PPO0 PD1/PPO1 PD2/PPO2 PD3/PPO3 PD4/PPO4 PD5/PPO5 PD6/PPO6 PD7/PPO7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PPO8 PH1/PPO9 PH2/PPO10 PH3/PPO11 PH4/PPO12 PH5/PPO13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE6 PE5 PE4 PE3/NMI PE2 PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/CS1 PB3 PB2 PB1 PB0/CINT SO0 SI0 SCK0 CS0 PA7 PA6 PA5 PA4 PA3/AN7 PA2/AN6 VSS PI6/SI2 VDD Note) 1. Vpp (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. PH6/PPO14 PH7/PPO15 PJ0/PPO16 PJ1/PPO17 PJ2/PPO18 PJ3/PPO19 PJ4/PPO20 PJ5/PPO21 PJ6/EXI0 PJ7/EXI1 –4– PA0/AN4 PA1/AN5 AVREF XTAL EXTAL AVDD AVSS EXI2 EXI3 RST AN0 AN1 AN2 AN3 VSS PE7/TO CXP847P60 Pin Description Symbol AN0 to AN3 Input I/O Analog inputs to A/D converter. (4 pins) (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Description PA0/AN4 to PA3/AN7 I/O/Input Analog inputs to A/D converter. (4 pins) PA4 to PA7 PB0/CINT PB1 to PB3 PB4/CS1 PB5/SCK1 PB6/SI1 PB7/SO1 I/O I/O/Input I/O I/O/Input I/O/I/O I/O/Input I/O/Output External capture input to 16-bit timer/counter. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH1). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). PC0 to PC7 I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PD0/PPO0 to PD7/PPO7 I/O/Real-time output PPO0 to PPO7 outputs for programmable pattern generator (PPG0). Functions as high-precision real-time pulse output port. (PPG0: 11 pins; PPG1: 11 pins) PE0/EC0 PE1/EC1 PE2 PE3/NMI PE4 to PE5 PE6 PE7/TO Input/Input Input/Input Input Input/Input Input Output Output/Output (Port E) 8-bit port. Lower 6 bits are for input; upper 2 bits are for output. (8 pins) External event inputs for timer/counter. (2 pins) Non-maskable interruption request. Rectangular wave output for 16-bit timer/counter. –5– CXP847P60 Symbol I/O Description (Port F) Lower 6 bits are for I/O. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits (PF0 to PF3) or 2 bits (PF4, PF5). PF6 is for output; PF7 is for input. (8 pins) UART transmission data output. UART reception data input. (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port J) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. Data is gated with PPO contents by OR-gate and they are output. (8 pins) PF0 to PF5 I/O PF6/TXD PF7/RXD Output/Output Input/Input PG0/PWM0 to PG7/PWM7 I/O/Output PWM outputs. (8 pins) PH0/PPO8 to PH7/PPO15 I/O/Real-time output PPO8 to PPO11 (PPG0) outputs and PPO12 to PPO15 (PPG1) outputs for programmable pattern generator (PPG0, PPG1). Functions as high-precision real-time pulse output port. PI0/INT0 to PI4/INT4 PI5/SCK2 PI6/SI2 PI7/SO2 I/O/Input I/O/I/O I/O/Input I/O/Output External interruption request inputs. (5 pins) Serial clock I/O (CH2). Serial data input (CH2). Serial data output (CH2). PPO16 to PPO21 outputs for programmable pattern generator (PPG1). Functions as high-precision real-time pulse output port. External inputs to FRC capture unit. (2 pins) PJ0/PPO16 to PJ5/PPO21 I/O/Real-time output PJ6/EXI0 PJ7/EXI1 I/O/Input I/O/Input EXI2 to EXI3 Input CS0 SCK0 SI0 SO1 Input I/O Input Output External inputs to FRC capture unit. (2 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). –6– CXP847P60 Symbol EXTAL XTAL RST Input I/O Description Connects a crystal for system clock oscillation. When a clock is supplied externally, input it to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. (Mask option) Positive power supply for incorporated PROM writing. Leave this pin open for normal operation. (Internally connected to VDD.) Positive power supply of A/D converter. Output I/O Vpp AVDD AVREF AVSS VDD VSS Input Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. GND. –7– CXP847P60 I/O Circuit Format for Pins Pin Port A Pull-up resistor "0" when reset Port A data Circuit format ∗ When reset PA0/AN4 to PA3/AN7 Port A direction "0" when reset Data bus RD (Port A) Port A function selection "0" when reset A/D converter IP Input protection circuit Hi-Z Input multiplexer ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 4 pins Port A Port B Port F PA4 to PA7 PB1 to PB3 PF0 to PF5 Pull-up resistor "0" when reset Ports A, B, F data ∗ Ports A, B, F direction "0" when reset Data bus RD (Ports A, B, F) IP Hi-Z 13 pins Port B Port I Port J PB0/CINT PB4/CS1 PB6/SI1 PI6/SI2 PJ6/EXI0 PJ7/EXI1 Ports B, I, J data Pull-up resistor "0" when reset ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) ∗ Ports B, I, J direction "0" when reset Data bus RD (Ports B, I, J) CINT CS1 SI1 SI2 EXI0 EXI1 Schmitt input IP Hi-Z ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 6 pins –8– CXP847P60 Pin Port B Port I Pull-up resistor Circuit format ∗ When reset "0" when reset SCK OUT Serial clock output enable Ports B, I function selection PB5/SCK1 PI5/SCK2 "0" when reset Ports B, I data Ports B, I direction "0" when reset Data bus RD (Ports B, I) SCK in Schmitt input IP Hi-Z 2 pins Port B Port I Pull-up resistor ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) ∗ "0" when reset SO Serial data output enable Ports B, I function selection PB7/SO1 PI7/SO2 "0" when reset Ports B, I data Ports B, I direction "0" when reset Data bus RD (Ports B, I) ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) IP Hi-Z 2 pins Port C Pull-up resistor "0" when reset Port C data ∗2 PC0 to PC7 Port C direction "0" when reset Data bus RD (Port C) ∗1 IP Hi-Z 8 pins ∗1 Large current 12mA ∗2 Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) –9– CXP847P60 Pin Port D PD0/PPO0 to PD7/PPO7 PH0/PPO8 to PH7/PPO15 PJ0/PPO16 to PJ5/PPO21 Port H Port J Pull-up resistor "0" when reset Ports D, H, J data Circuit format When reset ∗ PPO data Hi-Z Ports D, H, J direction "0" when reset Data bus RD (Ports D, H, J) ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) IP 22 pins PE0/EC0 PE1/EC1 PE2 PE3/NMI PE4 PE5 PF7/RxD 7 pins Port E Port E Port F IP Schmitt input (Inverter input for PE2, PE4, PE5) EC0, EC1, NMI, RxD Data bus RD (Ports E, F) Hi-Z PE6 Data bus Port E data "1" when reset High level 1 pin Port E RD (Port E) Internal reset signal Port E data "1" when reset TO 00 MPX 01 ∗ PE7/TO Port E function selection (upper) Port E function selection (lower) ( ∗ Pull-up transistors approx. 150kΩ (VDD = 4.5 to 5.5V) approx. 400kΩ (VDD = 3.0 to 3.6V) High level with the resistor of pullup transistor ON for reset ) "00" when reset TO output enable 1 pin – 10 – CXP847P60 Pin Port F UART transmission circuit Control for transmission and ports Circuit format When reset PF6/TxD "0" when reset Port F data "1" when reset Data bus High level 1 pin Port G RD (Port F) Pull-up resistor "0" when reset PWM Port G function selection ∗ PG0/PWM0 to PG7/PWM7 "0" when reset Port G data Port G direction "0" when reset Data bus RD (Port G) ∗ Pull-up transistors IP Hi-Z 8 pins Port I Pull-up resistor "0" when reset Port I data approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) ∗ PI0/INT0 to PI4/INT4 Port I direction "0" when reset Data bus RD (Port I) INT0 INT1 INT2 INT3 INT4 Schmitt input IP Hi-Z 5 pins AN0 to AN3 4 pins ∗ Pull-up transistors approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) Input multiplexer IP A/D converter Hi-Z – 11 – CXP847P60 Pin EXI2 EXI3 IP Circuit format Schmitt input EXI2, EXI3 When reset Hi-Z 2 pins CS0 SI0 2 pins Schmitt input IP SIO Hi-Z SO0 SO0 from SIO Hi-Z 1 pin SO0 output enable SCK0 Internal serial clock from SIO High level SCK0 output enable External serial clock to SIO IP 1 pin Schmitt input EXTAL XTAL EXTAL IP IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during stop mode and XTAL becomes High level. Oscillation 2 pins XTAL Pull-up resistor RST OP Mask option IP Schmitt input From power-on reset circuit (Mask option) See the Selection Guide for the Mask option. Low level (During a reset) 1 pin – 12 – CXP847P60 Absolute Maximum Ratings Item Symbol VDD Vpp Supply voltage AVDD AVSS AVREF Input voltagte Output voltage High level output current VIN VOUT IOH Rating –0.3 to +7.0 –0.3 to +13.0 AVSS to +7.0∗1 –0.3 to +0.3 AVSS to +7.0 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –5 –50 15 20 100 –10 to +75 –55 to +150 600 Allowable power dissipation PD 380 Unit V V V V V V V mA mA mA mA mA °C °C mW QFP package LQFP package (Vss = 0V reference) Remarks Incorporated PROM Output (value per pin) Total for all output pins All pins excluding large current outputs (value per pin) Large current outputs (value per pin) ∗3 Total for all output pins High level total output current ∑IOH Low level output current Low level total output current Operating temperature Storage temperature IOL IOLC ∑IOL Topr Tstg ∗1 AVDD and VDD must be set to the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 The large current output pins are Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 13 – CXP847P60 Recommended Operating Conditions Item Symbol Min. 4.5 3.0 Supply voltage VDD 2.7 2.5 Analog voltage AVDD VIH High level input voltage VIHS VIHEX 3.0 0.7VDD 0.8VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V V V °C (Vss = 0V reference) Remarks fc = 16MHz or less Guaranteed operation range for 1/2 and 1/4 fc = 12MHz or less frequency dividing clock. Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed data hold range during stop mode ∗1 ∗2, ∗5 ∗2, ∗6 Hysteresis input∗3 EXTAL pin∗4, ∗5 EXTAL pin∗4, ∗6 ∗2, ∗5 ∗2, ∗6 Hysteresis input∗3 EXTAL pin∗4, ∗5 EXTAL pin∗4, ∗6 VDD – 0.4 VDD + 0.3 VDD – 0.2 VDD + 0.2 VIL Low level input voltage VILS VILEX Operating temperature Topr 0 0 0 –0.3 –0.3 –10 0.3VDD 0.2VDD 0.2VDD 0.4 0.2 +75 ∗1 AVDD and VDD must be set to the same voltage. ∗2 Normal input port (PA, PB1 to PB3, PB7, PC, PD, PE2, PE4, PE5, PF0 to PF5, PG, PH, PI7, PJ0 to PJ5) ∗3 RST, CINT, CS0, CS1, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, NMI, RxD, INT0, INT1, INT2, INT3, INT4, EXI0, EXI1, EXI2 and EXI3 ∗4 Specifies only when the external clock is input. ∗5 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). ∗6 This case applies to the range of 3.0 to 5.5V supply voltage (VDD). – 14 – CXP847P60 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item Symbol Pins Conditions (Ta = –10 to +75°C, VSS = 0V reference) Min. 4.0 Typ. Max. Unit V High level VOH output voltage PA to PD, VDD = 4.5V, IOH = –0.5mA PE6, PE7, PF0 to PF6, PG to PJ, VDD = 4.5V, IOH = –1.2mA SCK0, SO0 PA to PD, VDD = 4.5V, IOL = 1.8mA PE6, PE7, PF0 to PF6, PG to PJ, SCK0, SO0, VDD = 4.5V, IOL = 3.6mA RST∗1 PC VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V TEX RST∗2 VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V PA to PD∗3, PF0 to PF5∗3, VDD = 4.5V, VIL = 4.0V PG to PJ∗3 ∗3, PA to PD PE0 to PE5, PF0 to PF5∗3, PF7, PG to PJ∗3, VDD = 5.5V CS0, SCK0, VI = 0, 5.5V SI0, EXI2, EXI3, AN0 to AN3 RST∗2 3.5 V 0.4 V Low level VOL output voltage 0.6 1.5 0.5 –0.5 0.1 –0.1 –1.5 40 –40 10 –10 –400 –45 –2.78 V V µA µA µA µA µA µA µA IIHE IILE IIHT Input current IILT IILR IIL EXTAL I/O leakage current IIZ ±10 µA – 15 – CXP847P60 Item Symbol IDD Pins Conditions 1/2 frequency dividing clock operation VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode Min. Typ. 24 Max. 50 Unit mA Supply current∗4 IDDS1 VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) Stop mode VDD = 5.5V, termination of 16MHz crystal oscillation 1.5 10 mA IDDS2 10 µA Input capacity CIN PA to PD, PE0 to PE5, PF0 to PF5, PF7, PG to PJ, Clock 1MHz CS0, SCK0, 0V for all pins excluding measured SI0, EXI2, pins EXI3, AN0 to AN3, EXTAL, RST 10 20 pF ∗1 RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage current when no resistance is selected. ∗3 PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected, and specify the leakage current when no resistance is selected. ∗4 When all pins are open. Note) See the Selection Guide for the mask option. – 16 – CXP847P60 Electrical Characteristics DC Characteristics (VDD = 3.0 to 3.6V) Item Symbol Pins Conditions (Ta = –10 to +75°C, VSS = 0V reference) Min. 2.7 Typ. Max. Unit V High level VOH output voltage PA to PD, VDD = 3.0V, IOH = –0.15mA PE6, PE7, PF0 to PF6, PG to PJ, VDD = 3.0V, IOH = –0.5mA SCK0, SO0 PA to PD, VDD = 3.0V, IOL = 1.2mA PE6, PE7, PF0 to PF6, PG to PJ, SCK0, SO0, VDD = 3.0V, IOL = 1.6mA RST∗1 PC VDD = 3.0V, IOL = 5.0mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V TEX RST∗2 VDD = 3.6V, VIL = 3.6V VDD = 3.6V, VIL = 0.4V VDD = 3.6V, VIL = 0.3V PA to PD∗3, PF0 to PF5∗3, VDD = 3.0V, VIL = 2.7V PG to PJ∗3 ∗3, PA to PD PE0 to PE5, PF0 to PF5∗3, PF7, PG to PJ∗3, VDD = 3.6V CS0, SCK0, VI = 0, 3.6V SI0, EXI2, EXI3, AN0 to AN3 RST∗2 2.3 V 0.3 V Low level VOL output voltage 0.5 1 0.3 –0.3 0.1 –0.1 –0.9 20 –20 10 –10 –200 –20 –1.0 V V µA µA µA µA µA µA µA IIHE IILE IIHT Input current IILT IILR IIL EXTAL I/O leakage current IIZ ±10 µA – 17 – CXP847P60 Item Symbol IDD Pins Conditions 1/2 frequency dividing clock operation VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode Min. Typ. 10 Max. 25 Unit mA Supply current∗4 IDDS1 VDD VDD = 3.6V, 12MHz crystal oscillation (C1 = C2 = 15pF) Stop mode VDD = 3.6V, termination of 12MHz crystal oscillation 0.5 2.0 mA IDDS2 10 µA Input capacity CIN PA to PD, PE0 to PE5, PF0 to PF5, PF7, PG to PJ, Clock 1MHz CS0, SCK0, 0V for all pins excluding measured SI0, EXI2, pins EXI3, AN0 to AN3, EXTAL, RST 10 20 pF ∗1 RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage current when no resistance is selected. ∗3 PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected, and specify the leakage current when no resistance is selected. ∗4 When all pins are open. Note) See the Selection Guide for the mask option. – 18 – CXP847P60 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time Symbol fC Pin XTAL EXTAL XTAL EXTAL XTAL EXTAL EC0 EC1 EC0 EC1 (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Conditions VDD = 4.5 to 5.5V Min. 1 1 Typ. Max. 16 12 Unit MHz Fig. 1, Fig. 2 Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 tXL tXH tCR tCF tEH tEL tER tEF 28 37.5 200 ns ns ns 20 ms tsys + 50∗1 ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”) Fig. 1. Clock timing 1/fc EXTAL VDD – 0.4V (VDD = 4.5 to 5.5V) VDD – 0.3V 0.4V (VDD = 4.5 to 5.5V) 0.3V tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation External clock EXTAL XTAL EXTAL XTAL C1 C2 74HC04 Fig. 3. Event count clock timing 0.8VDD EC0 EC1 0.2VDD tEH tEF tEL tER – 19 – CXP847P60 (2) Serial transfer (CH0, CH1) Item CS↓ → SCK delay time CS↑ → SCK floating delay time CS↓ → SO delay time CS↑ → SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK0 SCK1 SCK0 SCK1 SO0 SO1 SO0 SO1 CS0 CS1 SCK0 SCK1 SCK0 SCK1 SI0 SI1 SI0 SI1 SO0 SO1 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 8000/fc tsys + 100 4000/fc – 50 –tsys + 100 200 2tsys + 200 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1 and SO1 for CH1, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. – 20 – CXP847P60 Serial transfer (CH0, CH1) Item CS↓ → SCK delay time CS↑ → SCK floating delay time CS↓ → SO delay time CS↑ → SO floating delay time CS High level width SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK0 SCK1 SCK0 SCK1 SO0 SO1 SO0 SO1 CS0 CS1 SCK0 SCK1 SCK0 SCK1 SI0 SI1 SI0 SI1 SO0 SO1 (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Conditions Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. Max. 1.5tsys + 250 1.5tsys + 200 1.5tsys + 250 1.5tsys + 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tsys + 200 2tsys + 200 8000/fc tsys + 100 4000/fc – 100 –tsys + 100 200 2tsys + 200 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”) Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1 and SO1 for CH1, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. – 21 – CXP847P60 Fig. 4. Serial transfer CH0, CH1 timing tWHCS CS0 CS1 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 SCK1 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 SI1 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 SO1 Output data 0.2VDD – 22 – CXP847P60 Serial transfer (CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK2 (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK2 SI2 SI2 SO2 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively. Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL. Serial transfer (CH2) Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK↑) SI input hold time (for SCK↑) SCK↓ → SO delay time Symbol Pin SCK2 (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Conditions Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 100 100 200 200 100 250 125 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO SCK2 SI2 SI2 SO2 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”) Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively. Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF. – 23 – CXP847P60 Fig. 5. Serial transfer CH2 timing tKCY tKL tKH 0.8VDD SCK2 0.2VDD tSIK tKSI 0.8VDD SI2 Input data 0.2VDD tKSO 0.8VDD SO2 0.2VDD Output data – 24 – CXP847P60 (3) A/D converter characteristics (Ta = –10 to +75°C, VDD = AVDD = 3.0 to 5.5V, Vss = AVSS = 0V reference) Item Resolution Linearity errror Zero transition voltage Full-scale transition voltage Linearity errror Zero transition voltage Full-scale transition voltage Convertion time Sampling time Reference input voltage Analog input voltage VZT∗1 VFT∗2 Ta = 25°C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V –10 3215 26/fADC∗3 6/fADC∗3 VDD = AVDD = 4.5 to 5.5V VREF VIAN IREF AVREF current IREFS AVREF Sleep mode Stop mode AVREF AN0 to AN7 Operation mode VDD = 5.5V VDD = 3.6V VDD = AVDD = 3.0 to 3.6V AVDD – 0.5 AVDD – 0.3 0 0.6 0.4 AVDD AVDD AVREF 1.0 0.7 10 6.5 3280 VZT∗1 VFT∗2 Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V –50 4910 10 4970 Symbol Pin Conditions Min. Typ. Max. 8 ±3 70 5030 ±5 70 3345 Unit Bits LSB mV mV LSB mV mV µs µs V V V mA mA µA tCONV tSAMP Fig.6. Definition of A/D converter terms ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H). PS1 selected fADC = fc PS2 selected fADC = fc/2 FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT – 25 – CXP847P60 (4) Interruption, reset input (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin INT0 INT1 INT2 INT3 INT4 NMI RST Conditions Min. Max. Unit External interruption High, Low level width tIH tIL 1 µs Reset input Low level width Fig. 7. Interruption input timing tRSL 32/fc µs tIH tIL INT0 INT1 INT2 INT3 INT4 NMI (NMI is specified only for the falling edge) 0.8VDD 0.2VDD tIL tIH Fig. 8. RST input timing tRSL RST 0.2VDD (5) Power-on reset∗1 Item Power supply rise time Power supply cut-off time Symbol Pin VDD (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Conditions Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF ∗1 Power-on reset function is selected by the mask option. See the Selection Guide for the mask option. Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V. Fig. 9. Power-on reset 4.5V VDD 0.2V 0.2V tR Turn the power on smoothly. tOFF – 26 – CXP847P60 Appendix Fig. 10. Recommended oscillation circuit for SPC700 Series (i) Main clock EXTAL XTAL Rd C1 C2 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd (Ω) Circuit example RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 16.00 8.00 22 (15) 15 12 22 (15) 5 5 0 (i) KINSEKI LTD. HC-49/U (-S) 10.00 12.00 16.00 15 12 0 (i) Selection Guide Option item Reset pin pull-up resistor Power-on reset function Mask Non-existent/Existent Non-existent/Existent∗1 CXP847P60Q-1Existent Existent CXP847P60R-1Existent Existent ∗1 Power-on reset function "Existent" is not selected under the using condition in the range of VDD=3.0 to 4.5V. – 27 – CXP847P60 Characteristics Curve (Reference) IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 20 1/2 dividing mode 20.0 1/4 dividing mode 10.0 5.0 1/16 dividing mode Sleep mode 1.0 0.5 15 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode IDD – Supply current [mA] IDD – Supply current [mA] 1/4 dividing mode 10 0.1 (100µA) 0.05 (50µA) 5 1/16 dividing mode 0.01 (10µA) 3 4 5 6 Stop mode Sleep mode 0 5 10 fc – System clock [MHz] 16 VDD – Supply voltage [V] IDD vs. VDD (fc = 12MHz, Ta = 25°C, Typical) 20.0 10.0 5.0 1/2 dividing mode 1/4 dividing mode 20 IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) IDD – Supply current [mA] 1/16 dividing mode Sleep mode 15 1.0 0.5 IDD – Supply current [mA] 10 1/2 dividing mode 0.1 (100µA) 0.05 (50µA) 5 1/4 dividing mode 0.01 (10µA) 3 6 4 5 VDD – Supply voltage [V] 01 5 10 fc – System clock [MHz] 1/16 dividing mode Sleep mode 15 – 28 – CXP847P60 Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 26 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 ∗QFP100-P-1414-A – 29 – 0.5 ± 0.2 A (15.0)