CXP853P40A

CXP853P40A CMOS 8-bit Single-chip Microcomputer Description The CXP853P40A are a highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM generator, remote control receiver, HSYNC counter, power supply frequency counter, and watchdog timer. Also, this IC provides power-on reset and sleep functions. The designers have ensured low power consumption for these powerful microcomputers. The CXP853P40A is the one-chip PROM version of the CXP85340A with on-chip mask ROM, providing the function of being able to write directly into the program. Furthermore, because of the OSD character ROM can also be written directly into, it is suitable for evaluation use during system development and for small quantity production. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Features • A wide instruction set (213 instructions) which covers various of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle 1µs/4MHz (4MHz verison) 0.5µs/8MHz (8MHz verison) • Incorporated PROM capacity 40K bytes (For program) 6.75K bytes (For OSD) • Incorporated RAM capacity 576 bytes • Peripheral funcitons — On-screen display function 12 × 18 dots, 256 types, 15 colors, 12 lines of 21 characters Black frame output half blanking, shadow, background color on full screen/half blanking Double scanning mode supported, jitter elimination circuit — I2C bus interface — PWM output 14 bits, 1 channel 8 bits, 8 channels — Remote control receiver circuit 8-bit pulse measuring counter, 6-stage FIFO — A/D converter 8-bit, 4 channels, successive approximation system (conversion time of 40µs/4MHz, 8MHz) — HSYNC counter — Power supply frequency counter — Watchdog timer — Serial I/O 8-bit synchronized — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer • Interruption 14 factors, 14 vectors, multiple interrupt possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93Z19A7Z-PS Block Diagram MP VDD VSS EXTAL PE0/INT0 PE1/INT1 PD0/INT2 XTAL RST Vpp XLC EXLC R G B I YS YM PA7/HSYNC PA6/VSYNC 2 ON SCREEN DISPLAY PORT A SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL PA0 to PA7 PD4/HSI WATCHDOG TIMER HSYNC COUNTER PRESCALER/ TIME BASE TIMER PE0 to PE5 PE6 to PE7 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 14BIT PWM I2C INTERFACE UNIT 8 BIT PWM 8CH PE6/PWM PF0/PWM0 to PF7/PWM7 PORT F PE2/AN0 to PE5/AN3 A/D CONVERTER PORT E PD5/ACI AC TIMER PORT D –2– FIFO PD6/RMC REMOCON PORT C PD7/EC PE7/TO TIMER/COUNTER INTERRUPT CONTROLLER PD3/SI PD2/SO PD1/SCK PROM 40K BYTES RAM 576 BYTES SERIAL I/O PORT B 2 PB0 to PB7 PC0 to PC7 PD0 to PD7 PF0 to PF7 CXP853P40A CXP853P40A Pin Assignment 1 (Top View) 64 pin SDIP Package PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7/EC PD6/RMC PD5/ACI PD4/HSI PD3/SI PD2/SO PD1/SCK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD Vpp VSS MP PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 BLK R G B VSYNC HSYNC EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3 PE6/PWM PE7/TO RST EXTAL XTAL PD0/INT2 Note) 1. Vpp (Pin 63) is always connected to VDD. 2. Vss (Pins 32 and 62) are both connected to GND. 3. MP (Pin 61) is always connected to GND. –3– CXP853P40A Pin Assignment 2 (Top View) 64 pin QFP Package 64 63 62 61 60 59 58 57 56 55 54 53 52 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7/EC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PF0/PWM0 PA7 PF1/PWM1 PA2 VSS PF2/PWM2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3 PA4 PA5 PA6 VDD Vpp MP PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 BLK R G B VSYNC HSYNC EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3 20 21 22 23 24 25 26 27 28 29 30 31 32 PD2/SO PD3/SI PD4/HSI PD0/INT2 PD5/ACI EXTAL XTAL Note) 1. Vpp (Pin 56) is always connected to VDD. 2. Vss (Pins 26 and 58) are both connected to GND. 3. MP (Pin 55) is always connected to GND. –4– PE6/PWM PD6/RMC VSS PD1/SCK PE7/TO RST CXP853P40A Pin Description Symbol PA0 to PA5 PA6/VSYNC PA7/HSYNC PB0 to PB7 I/O I/O/Input I/O/Input I/O I/O Description (Port A) Single bit selectable 8-bit I/O port. (8 pins) CRT display vertical synchronization signal input pin. CRT display horizontal synchronization signal input pin. (Port B) Single bit selectable 8-bit I/O port. (8 pins) (Port C) Single bit selectable 8-bit I/O port. (8 pins) Input pin for external interrupt request. Active on falling edge. Serial clock I/O pin. (Port D) Single bit selectable Serial data output pin. 8-bit I/Oport. Serial data input pin. 12mA sink current drive possible. HSYNC counter input pin. (8 pins) Power supply frequency counter input pin. Remote control receiver circuit input pin. External event timer/counter input pin. Input pin for external interrupt request. Active on falling edge. (2 pins) Analog input pin for A/D converter. (4 pins) 14-bit PWM output pin. (CMOS output) Square wave output for timer 1. (50% duty cycle) (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits middle voltage tolerance (12V), upper 4 bits 5V suppression. (8 pins) 8-bit PWM output pin. (8 pins) PC0 to PC7 I/O PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC PE0/INT0 PE1/INT1 PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO PF0/PWM0 to PF3/PWM3 PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 R, G, B, I, YS, YM I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input Input/Input (Port E) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 pins) Input/Input Output/Output Output/Output Output/Output Output/Output/ I/O I2C bus interface transfer clock I/O pin. Output/Output/ I/O Output I2C bus interface transfer data I/O pin. CRT display 6-bit output pin. –5– CXP853P40A Symbol EXLC XLC EXTAL XTAL RST MP VDD Vpp Vss Input I/O Description CRT display clock oscillator I/O pin. Oscillator frequency is determined by external L, C circuit. System clock oscillator crystal connection pin. When using an external clock, input to EXTAL pin and leave XTAL pin open. "L" level active system reset. This pin also acts as an I/O pin during power up. While internal power-on reset function is talking place a "L" level is output. (Mask option) Test mode input pin. Must be connected to GND. Positive supply voltage pin. Positive power supply pin for incorporated PROM writing. Connect to VDD for normal operation. GND. Both Vss pins should be connected to common GND. Output Input Output I/O Input –6– CXP853P40A Input/Output Circuit Formats for Pins Pin Port A Port B Port C PA0 to PA5 PB0 to PB7 PC0 to PC7 Port A data Port B data Port C data Port A I/O direction Port B I/O direction Port C I/O direction IP Data bus RD (Port A, B, C) Input protection circuit Circuit format When reset Hi-Z 22 pins Port A Port A data Port A I/O direction PA6/VSYNC PA7/HSYNC Data bus RD (Port A) VSYNC HSYNC Schmitt input Input polarity IP Input protection circuit Hi-Z 2 pins Port D PD0/INT2 PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC Port D data Port D I/O direction Large current source 12mA Data bus RD (Port D) INT2, SI, HSI, ACI, RMC, EC Schmitt input IP Hi-Z 6 pins –7– CXP853P40A Pin Port D Circuit format When reset SCK or SO Output enable PD1/SCK PD2/SO Large current source 12mA Port D data Port D I/O direction Schmitt input RD (Port D) SCK only IP Hi-Z Data bus 2 pins Port E PE0/INT0 PE1/INT1 2 pins Port E Input multiplexer IP Schmitt input (To interrupt circuit) Hi-Z Data bus RD (Port E) PE2/AN0 to PE5/AN3 IP To A/D converter Hi-Z Data bus 4 pins Port E TO, PWM RD (Port E) PE6/PWM PE7/TO Port E data Port E selection High level 2 pins –8– CXP853P40A Pin Port F PF0/PWM0 to PF3/PWM3 PWM Circuit format When reset 12V voltage torelance Port F data Port F selection Large current source 12mA Hi-Z 4 pins Port F SCL, SDA PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 I2C output enable PWM Large current source 12mA Hi-Z Port F data Port F selection Schmitt input SCL, SDA (To I2C circuit) BUS SW To other I2C pins IP 4 pins R G B I YS YM 6 pins R, G, B, I, YS, YM Output polarity To output polarity register Writing data to port register brings output from high impedance to active Hi-Z EXLC XLC EXLC IP Oscillator control Oscillation halted XLC IP CRT display clock 2 pins –9– CXP853P40A Pin Circuit format When reset EXTAL XTAL • Diagram indicates circuit composition during oscillation EXTAL IP • Feedback resistor is disconnected during stop Oscillation XTAL 2 pins Pull-up resistor RST Mask option OP Schmitt input Low level From power-on reset circuit (Mask option) 1 pin – 10 – CXP853P40A Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium voltage tolerance output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation Symbol VDD Vpp VIN VOUT VOUTP IOH ∑IOH IOL IOLC ∑IOL Topr Tstg PD Ratings –0.3 to +7.0 –0.3 to +13.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +15.0 –5 –50 15 20 130 –10 to +75 –55 to +150 1000 600 Unit V V V V V mA mA mA mA mA °C °C mW mW SDIP QFP (Vss = 0V reference) Remarks Incorporated PROM Pins PF0 to PF3 Total of all output pins Excludes large current output Large current output∗2 Total of all output pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current drivetransistor for the PD and PF ports is a N-ch transistor. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 11 – CXP853P40A Recommended Operating Conditions Item Symbol VDD Supply voltage Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr Min. 4.5 3.5 2.5 Max. 5.5 5.5 5.5 Unit V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed range during operation Guaranteed range for low speed data∗1 Guaranteed data hold operation range during stop ∗5 I2C Schmitt input included∗2 CMOS Schmitt input∗3 EXTAL pin∗4 I2C Schmitt input included∗2 CMOS Schmitt input∗3 EXTAL pin∗4 Vpp = VDD 0.7VDD 0.8VDD VDD – 0.4 0 0 –0.3 –10 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 ∗1 Rating for 1/16 frequency mode and sleep mode. ∗2 Normal input port (All pins of PA, PB, PC, PE2 to PE5), PF4 to PF7 pins. ∗3 Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HSI, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1, HSYNC, VSYNC, RST pins. ∗4 It specifies only when the external clock is input. ∗5 Vpp and VDD should be set to the same voltage. – 12 – CXP853P40A Electrical Characteristics DC Characteristics Item High level output voltage Symbol (Ta = –10 to +75°C, Vss = 0V reference) Pin Condition Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 –0.5 –1.5 40 –40 –400 ±10 50 10 120 Typ. Max. Unit V V V V V V V µA µA µA µA µA µA Ω VOH PA to PD, PE6, PE7, VDD = 4.5V, IOH = –0.5mA R, G, B, I, YS, YM VDD = 4.5V, IOH = –1.2mA PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, I, YS, YM, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, RST Low level output voltage VOL PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V IIHE Input current IIHL IILR I/O leakage current Open drain output leakage current (N-ch Tr off case) I2C bus switch connection impedance (output Tr off case) IIZ EXTAL RST PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM PF0 to PF3 VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V Operating mode (1/2, 1/4 clock rate) 4MHz, 8MHz crystal oscillator (C1 = C2 = 22pF) All output pins open Sleep mode Stop mode∗4 ILOH PF4 to PF7 RBS SCL0: SCL1 SDA0: SDA1 11∗2 17∗3 0.6∗2 0.8∗3 — — 10 30∗2 mA 40∗3 3∗2 3∗3 — 20 IDD Supply current IDDSL IDDST Input capacitance ∗1 ∗2 ∗3 ∗4 CIN Pins other than VDD and Vss VDD∗1 mA µA pF 1MHz clock 0V other than the measure pins Rating applies only if OSD oscillator is halted. Oscillator clock 4MHz version Oscillator clock 8MHz version This device does not enter the stop mode. – 13 – CXP853P40A AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock rise and fall times Event counter input clock pulse widtth Event counter input clock rise and fall times Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig 1, Fig 2 External clock drive Fig. 3 Fig. 3 Min. 3.5∗2 7∗3 100∗2 50∗3 200 Max. 4.5 9 Unit MHz ns ns ns 20 ms tXL, tXH tCR, tCF tEH, tEL tER, tEF tsys + 50∗1 ∗1 tsys indicates one of three values according to the contents of the clock control register (address : 00FEH) upper 2 bits (CPU clock selection) tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") ∗2 Oscillator clock 4MHz version ∗3 Oscillator clock 8MHz version 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillator Ceramic oscillator External clock EXTAL XTAL EXTAL XTAL C1 C2 OPEN Fig. 2. Clock applied condition 0.8VDD EC 0.2VDD tEH tEF tEL tER Fig. 3. Event count clock timing – 14 – CXP853P40A (2) Serial transfer Item SCK cycle time SCK High and Low level widths SI input setup time (referenced to SCK ↑) SI input hold time (referenced to SCK ↑) SCK ↓ → SO delay time Symbol Pin SCK (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode 400 4000/fc' – 50∗1 100 200 200 100 200 100 Min. 1000 8000/fc'∗1 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. ∗1 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSO 0.8VDD SO 0.2VDD Output data Fig. 4. Serial transfer timing – 15 – CXP853P40A (3) Interrupt, Reset input Item External interrupt High and Low level widths Reset input low level width (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 to INT2 RST Condition Min. 1 8/fc' ∗1 Max. Unit µs µs tIH tIL tRSL ∗1 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 tIH tIL INT0 to INT2 (falling edge) 0.8VDD 0.2VDD Fig. 5. Interrupt input timing tRSL RST 0.2VDD Fig. 6. RST input timing (4) Power-on reset Power-on reset Item Power supply rise time Power supply cutt-off time Symbol (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin VDD Condition Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF 4.5V VDD 0.2V tR The power supply should rise smoothly. tOFF 0.2V Fig. 7. Power-on reset – 16 – CXP853P40A (5) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT∗1 VFT∗2 Symbol Pin (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 8 ±3 Ta = 25°C VDD = 5.0V Vss = 0V –10 4930 160/fc' ∗3 12/fc' ∗3 70 5050 150 5120 Unit Bits LSB mV mV µs µs VDD V tCONV tSAMP VIAN AN0 to AN3 0 FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT ∗1 VZT: Digital conversion values change between 00H← 01H. → ∗2 VFT: Digital conversion values change between FEH← FFH. → ∗3 The value of fc' varies as shown below depending on the specification of oscillation clock option. 4MHz version ... fc' = fc 8MHz version ... fc' = fc/2 Fig. 8. Definitions for A/D converter terms – 17 – CXP853P40A (6) I2C bus timing Item SCL clock frequency Bus free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 0∗1 250 1 300 Max. 100 Unit kHz µs µs µs µs µs µs ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗1 Since for part of data hold time SCL rise time (max: 300ns) is not considered , allow at least 300ns. SDA tBUF tR tF tHD; STA SCL tHD; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STA tSU; STO P Fig. 9. I2C bus transfer data timing I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C device R S RP RP Fig. 10. I2C device recommended circuit • A pull-up resistor (RP) must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 18 – CXP853P40A (7) OSD (On Screen Display) timing Item Symbol Pin EXLC XLC HSYNC HSYNC VSYNC (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condiiton Shadow Existent Min. 4 1.2 200 1.0 Max. 7∗1 14∗2 Shadow Non-existent Min. 4 1.2 200 1.0 Max. 11∗1 16∗2 Unit OSD clock frequency HSYNC pulse width HSYNC afterwrite rise and fall times VSYNC afterwrite rise and fall times ∗1 Oscillator clock 4MHz version ∗2 Oscillator clock 8MHz version fOSC Fig. 12 Fig. 11 Fig. 11 Fig. 11 MHz µs ns µs tHWD tHCG tVCG tHWD tHCG HSYNC For OPOL register (01FAH) bit 7 at “0” 0.8VDD 0.2VDD tVCG VSYNC For OPOL register (01FAH) bit 6 at “0” 0.8VDD 0.2VDD Fig. 11. OSD timing EXLC XLC L C1 C2 Fig. 12. LC oscillator circuit connection – 19 – CXP853P40A Supplement (i) (ii) EXTAL XTAL Rd EXTAL XTAL Rd C1 C2 C1 C2 Fig. 13. Recommended oscillation circuit Circuit Example Manufacturer Model CSA4.00MG CSA4.19MG fc (MHz) 4.00 4.19 8.00 4.00 4.19 8.00 4.00 C1 (pF) C2 (pF) Rd (Ω) (i) 30 30 0 (ii) MURATA MFG CO., LTD. CSA8.00MTZ CST4.00MGW∗ CST4.19MGW∗ CST8.00MTW∗ RIVER ELETEC CORPORATION HC-49/U03 4.19 8.00 4.00 12 12 0 (i) KINSEKI LTD. HC-49/U(-S) 4.19 8.00 27 27 0 (i) ∗ Indicates types with on-chip grounding capacitors (C1 and C2). Product List Option item Package PROM capacitance Reset pin pull-up resistor Power-on reset circuit Font data Oscillator clock Mask 64-pin plastic SDIP/QFP 24K/32K/40K bytes Existent/Non-existent Existent/Non-existent User specified 4MHz/8MHz CXP853P40AS-2CXP853P40AQ-264-pin plastic SDIP/QFP PROM 40K bytes Existent Existent CXP853P40AS-3CXP853P40AQ-364-pin plastic SDIP/QFP PROM 40K bytes Existent Existent User specified (PROM)∗1 User specified (PROM)∗1 4MHz 8MHz ∗1 The font data for the one-time PROM version is operated in the same way as the program writing. – 20 – CXP853P40A IDD vs. VDD (fC = 4MHz, Ta = 25°C, Typical) 15 10 1/2 frequency mode 20 IDD vs. VDD (fC = 8MHz, Ta = 25°C, Typical) 10 1/2 frequency mode 1/4 frequency mode 1/4 frequency mode IDD – Supply current [mA] 1 Sleep mode IDD – Supply current [mA] 1/16 frequency mode 1/16 frequency mode 1 Sleep mode 0.1 0.1 2 3 4 5 VDD – Supply voltage [V] 6 2 3 4 5 VDD – Supply voltage [V] 6 IDD vs. fC (VDD = 5V, Ta = 25°C, Typical) 20 1/2 frequency mode 100 Parameter curve for OSD oscillator L vs. C (Analytically calculated value) 15 IDD – Supply current [mA] L – Inductance [µH] 5.0MHz 6.5MHz 1/4 frequency mode 10 1/16 frequency mode 10 5 13.0MHz Sleep mode 0 1 5 10 fC – System clock [MHz] 1 0 fOSC = 1 2π √ LC C = C1//C2 100 50 C1, C2 – Capacitance [pF] Fig. 14. Characteristic curves – 21 – CXP853P40A Package Outline Unit: mm 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 33 19.05 + 0.3 17.1 – 0.1 + 0.1 0.05 0.25 – 0° to 15° 32 1.778 0.5 ± 0.1 0.9 ± 0.15 1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 + 0.35 2.75 – 0.15 0.2 M 0° to10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g – 22 – 0.8 ± 0.2 19 16.3