CXP86616

CXP86608/86612/86616 CMOS 8-bit Single Chip Microcomputer Description The CXP86608/86612/86616 are the CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, I2C bus interface, PWM output, remote control reception circuit, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP86608/86612/86616 also provide a sleep function that enables to lower the power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM 8K bytes (CXP86608) 12K bytes (CXP86612) 16K bytes (CXP86616) • Incorporated RAM 352 bytes • Peripheral functions — A/D converter 8 bits, 6 channels, successive approximation method (Conversion time of 3.25µs at 16MHz) — Serial interface 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter — I2C bus interface — PWM output 8 bits, 4 channels — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — Watchdog timer • Interruption 11 factors, 11 vectors, multi-interruption possible • Standby mode Sleep • Package 64-pin plastic SDIP/QFP • Piggyback/evaluator CXP86400 64-pin ceramic PQFP CXP86490 64-pin ceramic PSDIP Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. Structure Silicon gate CMOS IC –1– E97750-PS INT0 INT1 INT2 ROM 8K/12K/16K BYTES RAM 352 BYTES PORT B RMC REMOCON FIFO PORT A AN0 to AN5 8 6 A/D CONVERTER 6CH SPC700 CPU CORE CLOCK GENERATOR /SYSTEM CONTROL TEX TX EXTAL XTAL RST VDD VSS Block Diagram PA0 to PA7 8 PB0 to PB7 PORT C SI SO SCK 2 SERIAL INTERFACE UNIT INTERRUPT CONTROLLER 6 2 PC0 to PC5 PC6 to PC7 EC 8 BIT TIMER/ COUNTER 0 PORT D TO 8 BIT TIMER 1 8 PD0 to PD7 PORT E PORT F 2 I2C BUS INTERFACE UNIT 8 BIT PWM 4 SDA0 SDA1 SCL0 SCL1 ADJ PWM0 to PWM3 PORT G –2– PRESCALER/ TIME BASE TIMER WATCHDOG TIMER 32kHz TIMER/COUNTER 2 2 3 4 4 PE0 to PE1 PE2 to PE3 PE4 to PE6 PF0 to PF3 PF4 to PF7 5 PG3 to PG7 CXP86608/86612/86616 CXP86608/86612/86616 Pin Assignment (Top View) 64-pin SDIP PC3 PC2 PC1 PC0 PD7/EC PD6/RMC PD5 PD4 PD3/SI PD2/SO PD1/SCK PD0/INT2 PA7 PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 PB6 PB5 PB4 PB3 PG7/INT1 PG6 PG5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PC4 PC5 PC6 PC7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 PE0/TO/ADJ PE1 PE2/TEX/INT0 PE3/TX VSS VDD NC NC NC PE4 PE5 PE6 NC NC NC PB0 PB1 PB2 PG3 PG4 Note) 1. NC (Pins 38, 39, 40, 44 and 46) are left open. 2. Vss (Pins 16 and 48) are both connected to GND. 3. Pin 45 is the NC pin. However, connect it to VDD because it is the EXLC pin (input) for the piggyback/evaluator and OTP devices. –3– CXP86608/86612/86616 Pin Assignment (Top View) 64-pin QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 PD5 PD4 PD3/SI PD2/SO PD1/SCK PD0/INT2 PA7 PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 PE0/TO/ADJ PE1 PE2/TEX/INT0 PE3/TX VSS VDD NC NC NC PE4 PE5 PE6 NC NC PC2 PB3 PG4 PG3 PB5 PB4 PB2 PF0/PWM0 PC3 PF1/PWM1 PB0 PD6/RMC PC4 PG6 PG5 PB6 Note) 1. NC (Pins 32, 33, 34, 38 and 40) are left open. 2. Vss (Pins 10 and 42) are both connected to GND. 3. Pin 39 is the NC pin. However, connect it to VDD because it is the EXLC pin (input) for the piggyback/evaluator and OTP devices. PG7/INT1 –4– PB1 NC PF2/PWM2 PD7/EC PC1 PC0 PC5 PC6 PC7 CXP86608/86612/86616 Pin Description Symbol PA0/AN0 to PA5/AN5 PA6 to PA7 I/O I/O/ Analog input I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Description Analog inputs to A/D converter. (6 pins) PB0 to PB7 I/O (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper 2bits are output port and large current (12mA) N-channel open drain output. Upper 2 bits are medium voltage drive (12V), lower 6 bits are 5V drive. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. (8 pins) Serial clock I/O. Serial data output. Serial data input. PC0 to PC5 PC6 to PC7 PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4 to PD5 PD6/RMC PD7/EC PE0/TO/ADJ PE1 PE2/TEX/INT0 I/O Output I/O/Input I/O/I/O I/O/Output I/O/Input I/O I/O/Input I/O/Input I/O/Output/ Output I/O Input/Input/ Input Input/Output Output Remote control reception circuit input. External event input for timer/counter. PE3/TX PE4 to PE6 (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins) Rectangular wave output for 8-bit timer/counter. 32kHz oscillation frequency dividing output. Connects a crystal for External interruption 32kHz timer/counter request input. Active at clock oscillation. When the falling edge used as an event counter, input to TEX pin and leave TX pin open. –5– CXP86608/86612/86616 Symbol PF0/PWM0 to PF3/PWM3 PF4/SCL0 to PF5/SCL1 I/O Output/Output (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium voltage drive (12V); upper 4 bits are 5V drive. (8 pins) Description 8-bit PWM output. (4 pins) I2C bus interface transfer clock I/O. (2 pins) Output/I/O PF6/SDA0 to PF7/SDA1 PG3 to PG6 PG7/INT1 EXTAL XTAL RST NC VDD Vss Output/I/O I2C bus interface transfer data I/O. (2 pins) I/O I/O/Input Input Output Input (Port G) 5-bit I/O port. I/O can be set in a unit of single bits. (5 pins) External interruption request input. Active at the falling edge. Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. No connected. Connect this pin to VDD under normal operation. Positive power supply. GND. Connect two Vss pins to GND. –6– CXP86608/86612/86616 Input/Output Circuit Formats for Pins Pin Port A Port A data Port A direction Circuit format After reset PA0/AN0 to PA5/AN5 "0" after reset IP RD (Port A) Port A function selection "0" after reset A/D converter Input multiplexer Input protection circuit Data bus Hi-Z 6 pins Port A Port A data PA6 PA7 Data bus RD (Port A) Port A direction "0" after reset Schmitt input Hi-Z IP 2 pins Port B Port C PB0 to PB7 PC0 to PC5 PG3 to PG6 PG7/INT1 Port G Ports B, C, G data Ports B, C, G direction "0" after reset Schmitt input only for PG7 Hi-Z IP Data bus RD (Ports B, C, G) 19 pins Port C PC6 PC7 INT1 Port C data ∗ Hi-Z Data bus ∗ 12V drive Large current 12mA 2 pins RD (Port C) –7– CXP86608/86612/86616 Pin Port D Circuit format After reset Port D data PD0/INT2 PD3/SI PD6/RMC PD7/EC Port D direction "0" after reset Schmitt input RD (Port D) INT2, SI, RMC, EC ∗ Large current 12mA ∗ Hi-Z Data bus IP 4 pins Port D SCK, SO SIO output enable Port D data PD1/SCK PD2/SO Port D direction "0" after reset ∗ Hi-Z IP Data bus RD (Port D) Schmitt input only for PD1 2 pins Port D SCK only ∗ Large current 12mA Port D data Port D direction "0" after reset Schmitt input RD (Port D) ∗ PD4 PD5 Data bus Hi-Z IP 2 pins ∗ Large current 12mA –8– CXP86608/86612/86616 Pin Port E Circuit format Internal reset signal Port E data "1" after reset TO ∗1 ADJ16K ∗ ADJ2K 1 00 01 10 11 MPX ∗2 After reset PE0/TO/ADJ Port E function selection (upper) Port E function selection (lower) "00" after reset Port E direction "1" after reset Data bus ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up transistor approx. 150kΩ High level (with the resistor of pull-up transistor ON when reset) 1 pin Port E RD (Port E) Port E data "1" after reset PE1 Port E direction "1" after reset IP Data bus RD (Port E) High level 1 pin Port E 32kHz oscillation circuit control "1" after reset Schmitt input INT0 Data bus PE2/TEX/INT0 PE3/TX PE2/ TEX/ INT0 IP IP RD (Port E) Data bus RD (Port E) Schmitt input Clock input Oscillation stop Port input 2 pins PE3/ TX –9– CXP86608/86612/86616 Pin Port E PE4 PE5 PE6 Circuit format After reset Port E data Output becomes active from high impedance by data writing to port register. RD (Port E) Hi-Z Data bus 3 pins Port F PWM0 to PWM3 PF0/PWM0 to PF3/PWM3 Port F function selection "0" after reset Port F data "1" after reset Data bus ∗ 12V drive Large current 12mA ∗ Hi-Z 4 pins Port F SCL, SDA I2C output enable RD (Port F) PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 ∗ Port F data "1" after reset Schmitt input SCL, SDA (I2C circuit) ∗ Large current 12mA IP BUS SW Hi-Z 4 pins To internal I2C pins (SCL1 for SCL0) – 10 – CXP86608/86612/86616 Pin Circuit format After reset EXTAL XTAL EXTAL IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during stop. (This device does not enter the stop mode.) Oscillation XTAL 2 pins Pull-up resistor RST Mask option OP Schmitt input Low level (when reset) 1 pin – 11 – CXP86608/86612/86616 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation Symbol VDD VIN VOUT VOUTP IOH ∑IOH IOL IOLC ∑IOL Topr Tstg PD Ratings –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +15.0 –5 –50 15 20 130 –20 to +75 –55 to +150 1000 600 Unit V V V V mA mA mA mA mA °C °C mW mW SDIP-64P-01 QFP-64P-L01 Total of all output pins (Vss = 0V reference) Remarks Ports excluding large current output (value per pin) Large current output ports (value per pin∗2) Total of all output pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.7 — VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 ∗5 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 — VDD VDD Unit V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed operation range for TEX Guaranteed data hold range for stop∗1 ∗2 ∗3 EXTAL pin∗4, TEX pin∗5 ∗2 ∗3 EXTAL pin∗4, TEX pin∗5 VDD – 0.4 VDD+0.3 0 0 –0.3 –20 0.3VDD 0.2VDD 0.4 +75 This device does not enter the stop mode. PA0 to PA5, PB0 to PB7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0, SCL1, SDA0, SDA1 pins PA6, PA7, INT2, SCK, SI, PD4, PD5, RMC, EC, INT0, INT1, RST pins Specifies only during external clock input. Specifies only during external event count input. – 12 – CXP86608/86612/86616 Electrical Characteristics DC characteristics Item High level output voltage Symbol VOH Pins PA, PB, PC0 to PC5, PD, PE0 to PE1, PE4 to PE6, PG (Ta = –20 to +75°C, Vss = 0V reference) Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 –0.5 0.1 –0.1 –1.5 40 –40 10 –10 –400 ±10 50 10 120 Typ. Max. Unit V V V V V V V µA µA µA µA µA µA µA µA Ω PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA PE4 to PE6, PF0 to PF3, VDD = 4.5V, IOL = 3.6mA PG Low level output voltage VOL PC6, PC7, PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE IILE Input current IIHT IILT IILR I/O leakage current IIZ EXTAL VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V TEX RST∗1 PA to PE, PG, RST∗1 Open drain I/O ILOH leakage current (in N-ch Tr off state) I2C bus switch connection impedance RBS (in output Tr off state) PC6, PC7, PF0 to PF3 VDD = 5.5V, VOH = 12.0V PF4 to PF7 SCL0: SCL1 SDA0: SDA1 VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing clock operation IDD1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) Sleep mode VDD 18 28 mA IDD2 30 80 µA Supply current∗2 IDDS1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) Stop mode∗3 VDD = 5.5V, termination of 16MHz and 32MHz oscillation – 13 – — 1.2 2.1 mA IDDS2 12 35 µA IDDS3 — — µA CXP86608/86612/86616 Item Input capacitance Symbol CIN Pins Conditions Min. Typ. 10 Max. 20 Unit pF PA to PD, PE0 to PE3, Clock 1MHz PF4 to PF7, PG3 to PG7, 0V for no measured pins EXTAL, TEX, RST ∗1 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. ∗2 When all output pins are left open. ∗3 This device does not enter the stop mode. – 14 – CXP86608/86612/86616 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied conditions) Fig. 3 Fig. 3 10 20 4tsys∗1 20 Min. 8 28 200 Typ. Max. 16 Unit MHz ns ns ns ms tXL, tXH System clock input rise and fall tCR, times tCF Event count input clock pulse tEH, width tEL Event count input clock rise and tER, fall times tEF System clock frequency Event count input clock input pulse width fC 32.768 kHz tTL, tTH Event count input clock rise and tTR, fall times tTF µs ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V EXTAL 0.4V tXH Crystal oscillation Ceramic oscillation tCF tXL tCR Fig. 1. Clock timing External clock 32kHz clock applied condition Crystal oscillation EXTAL C1 XTAL C2 EXTAL XTAL TEX TX 74HC04 C1 C2 Fig.2. Clock applied conditions TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR Fig. 3. Event count clock timing – 15 – CXP86608/86612/86616 (2) Serial transfer Item SCK cycle time SCK High and Low level width SI input setup time (for SCK ↑) SI hold time (for SCK ↑) SCK ↓ → SO delay time Symbol Pins SCK (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSO 0.8VDD SO 0.2VDD Output data Fig. 4. Serial transfer timing – 16 – CXP86608/86612/86616 (3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT∗1 VFT∗2 Symbol Pins (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. Typ. Max. 8 ±3 Ta = 25°C VDD = 5.0V Vss = 0V –10 4910 26/fADC∗3 6/fADC∗3 10 4970 70 5030 Unit Bits LSB mV mV µs µs VDD V tCONV tSAMP AN0 to AN5 Analog input voltage VIAN 0 FFh FEh Digital conversion value ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F6h): Linearity error fADC = fc (CKS = "0"), fc/2 (CKS = "1") 01h 00h VZT Analog input VFT Fig. 5. Definitions of A/D converter terms – 17 – CXP86608/86612/86616 (4) Interruption, reset input Item External interruption High, Low level width Reset input Low level width (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 RST Conditions Min. 1 32/fc Max. Unit µs µs tIH tIL tRSL tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 6. Interruption input timing tRSL RST 0.2VDD Fig. 7. RST input timing – 18 – CXP86608/86612/86616 (5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Conditions Min. 0 4.7 4.0 4.7 4.0 4.7 0∗1 250 1 300 Max. 100 Unit kHz µs µs µs µs µs µs ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P Fig. 8. I2C bus transfer timing I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C device R S RP RP Fig. 9. I2C device recommended circuit • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 19 – CXP86608/86612/86616 Appendix (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL Rd EXTAL XTAL Rd C1 TEX TX Rd C2 C1 C2 C1 C2 Fig. 10. Recommended oscillation circuit Manufacture Model CSA10.0MTZ CSA12.0MTZ fc (MHz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 C1 (pF) C2 (pF) Rd (Ω) Circuit example 30 5 30 5 18 12 10 10 5 Open 30 30 5 30 5 18 12 10 10 5 Open 33 120k 0 ∗1 330 ∗1 0 ∗1 (i) MURATA MFG CO., LTD. CSA16.00MXZ040 CST10.0MTW∗ CST12.0MTW∗ CST16.00MXW0C1∗ (ii) RIVER ELETEC HC-49/U03 CORPORATION (i) HC-49/U (-S) KINSEKI LTD. P3 12.0 16.0 32.768kHz (iii) ∗Models with an asterisk have the built-in ground capacitance (C1, C2). ∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Reset pin pull-up resistor Non-existent Content Existent – 20 – CXP86608/86612/86616 IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 100 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode 10 1/4 dividing mode 15 1/2 dividing mode 1/16 dividing mode IDD – Supply current [mA] 1 Sleep mode IDD – Supply current [mA] 10 1/4 dividing mode 0.1 32kHz operation mode 32kHz sleep mode 0.01 5 1/16 dividing mode Sleep mode 1 2 3 4 5 6 7 0 0 5 10 fc – System clock [MHz] 15 VDD – Supply voltage [V] Fig. 11. Characteristic curves – 21 – CXP86608/86612/86616 Package Outline Unit: mm 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0.1 64 33 19.05 + 0.3 17.1 – 0.1 + 0.1 0.05 0.25 – 0° to 15° 32 1.778 0.5 ± 0.1 0.9 ± 0.15 1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 3.0 MIN 0.5 MIN + 0.4 4.75 – 0.1 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 + 0.35 2.75 – 0.15 0.2 M 0° to10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g – 22 – 0.8 ± 0.2 19 16.3