CXP87452

CXP87452/87460 CMOS 8-bit Single Chip Microcomputer Description The CXP87452/87460 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface (2ch independently), timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit (PPG 2ch independently, RTG 2ch independently), PWM generator, general purpose prescaler, PWM for tuner, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP87452/87460 provides power on reset function, sleep/stop function which enables to lower power consumption . 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V) During operation 250ns/16MHz (4.5 to 5.5V) • Incorporated ROM capacity 52K bytes (CXP87452) 60K bytes (CXP87460) • Incorporated RAM capacity 1568 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation system (Conversion time: 20µs/16MHz) — Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer) 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer — High precision timing pattern generator PPG 19 pins 32-stage programmable PPG 10 pins 21-stage programmable RTG 5 pins 2-channel — PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz) DA gate pulse 12-bit, 4-channel — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — General purpose prescaler 10-bit (System clock asynchronous) — Pulse cycle measurement circuit • Interruption 18 factors, 14 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP87400 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95111-PS PI4/INT1 Block Diagram AVss PE0/INT0 PE1/INT2 EXTAL RST AVREF XTAL MP VDD Vss AVDD AN0 to AN3 PF0/AN4 to PF7/AN11 SPC700 CPU CORE PORT B CLOCK GENERATOR/ SYSTEM CONTROL 8 PORT A 12 A/D CONVERTER 2 8 PA0 to PA7 CS0 SI0 SO0 SCK0 BUFFER RAM PORT C SERIAL INTERFACE UNIT (CH0) PB0 to PB7 8 PC0 to PC7 PI7/SI1 PI6/SO1 FIFO 2 ROM 52K/60K BYTES RAM 1568 BYTES INTERRUPT CONTROLLER PORT E PE1/EC PI3/TO 8BIT TIMER/COUNTER 0 PORT D PI5/SCK1 SERIAL INTERFACE UNIT (CH1) 8 PD0 to PD7 8BIT TIMER 1 2 6 PORT F PE0 to PE1 PE2 to PE7 4 4 PF0 to PF3 PF4 to PF7 V SYNC SEPARATOR 2 2 PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 SERVO INPUT CONTROL 3 FIFO PRESCALER/ TIME BASE TIMER FRC CAPTURE UNIT PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL CTL PORT G PROGRAMMABLE PRESCALER PORT H PORT I 12BIT PWM GENERATOR CH0 2 PROGRAMMABLE PATTERN GENERATOR (CH0) RAM PROGRAMMABLE PATTERN GENERATOR (CH1) RAM PORT J PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 4 4 12BIT PWM GENERATOR CH1 19 10 2 PG4/PMI PG7/PMSK PULSE MEASURE UNIT REALTIME PULSE GENERATOR CH0 CH1 PPO100 to PPO000 to PPO018 PPO107 PPO112 to PPO113 RTO3 to RTO7 CXP87452/87460 19 10 5 PORT K –2– 2 CAPSTAN DRUM 8 PG0 to PG7 8 1 7 8 PH0 to PH7 PI0/PCK/OSCI PK0/OSCO PI1/PO PE0/XOUT PI0 PI1 to PI7 PJ0 to PJ7 PI2/PWM 14BIT PWM GENERATOR 1 PK0 CXP87452/87460 Pin Configuration 1 (Top View) 100 pin QFP Package PA0/PPO000/PPO100 PA1/PPO001/PPO101 PA2/PPO002/PPO102 PA4/PPO004/PPO104 PA5/PPO005/PPO105 PA3/PPO003/PPO103 PA6/PPO006/PPO106 PA7/PPO007/PPO107 PB6/PPO014 PB7/PPO015 PK0/OSCO PI0/PCK/OSCI Mask option PI2/PWM PI1/PO VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO013/PPO113 PB4/PPO012/PPO112 PB3/PPO011 PB2/PPO010 PB1/PPO009 PB0/PPO008 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO018 PC1/PPO017 PC0/PPO016 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0/XOUT PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PF2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 PI3/TO NC PF6/AN10 EXTAL PH1 RST SO0 PH6 PH0 PH2 VSS SI0 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– PF7/AN11 PF5/AN9 PH4 CS0 SCK0 PH7 PH5 PH3 MP XTAL PI5/SCK1 VSS PI4/INT1 CXP87452/87460 Pin Configuration 2 (Top View) 100 pin LQFP Package PA3/PPO003/PPO103 PA1/PPO001/PPO101 PA2/PPO002/PPO102 PA4/PPO004/PPO104 PA6/PPO006/PPO106 PB4/PPO012/PPO112 PB5/PPO013/PPO113 PA0/PPO000/PPO100 PA5/PPO005/PPO005 PA7/PPO007/PPO107 Mask option 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO011 PB2/PPO010 PB1/PPO009 PB0/PPO008 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO018 PC1/PPO017 PC0/PPO016 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC PE0/INT0/XOUT PK0/OSCO PI0/PCL/OSCI PB6/PPO014 PB7/PPO015 PI2/PWM PI4/INT1 PI5/SCK1 PI6/SO1 PI1/PO VDD PI3/TO PI7/SI1 VSS 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PF2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PH4 PH3 PF7/AN11 PF5/AN9 PF4/AN8 PH1 EXTAL SO0 PH0 VSS SCK0 PH5 MP PD1 CS0 XTAL Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– PF6/AN10 AVSS PH6 RST PD2 PD0 PH7 PH2 SI0 CXP87452/87460 Pin Description Symbol PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 PB0/PPO008 to PB7/PPO015 PC0/PPO016 to PC2/PPO018 PC3/RTO3 to PC7/RTO7 I/O Output/ Real time output Description (Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins) Programmable pattern generator (PPG0, PPG1) output. (Port B) 8-bit output port. Data is gated Functions as high precision real time with PPO0 and PPO1 contents pulse output port. PPG0 19 pins by OR-gate and they are output. PPG1 10 pins (8 pins) Output/ Real time output I/O/ Real time output I/O/ Real time output ( ) (Port C) 8-bit I/O port. Enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sinc current. (During 5V ± 0.5V operation) (8 pins) Input pin to request 1/2 dividing clock external interruption. output of XTAL Active when falling edge. or OSCO. External event input pin for timer/counter. Input pin to request external interruption. Active when falling edge. PE0/INT0 /XOUT Input/input/output PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0 Input/input/input Output/output Output/output Output/output Output/output Output/output Output/output Input Input/input (Port E) 8-bit port. Lower 2 bits are input port and upper 6 bits are output port. (8 pins) PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) Analog input pins to A/D converter. (12 pins) (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) Output/input I/O Ouput Input Input Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin. –5– CXP87452/87460 Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 /PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/ PMSK PH0 to PH7 I/O Input/input Input/input Input/input Input/input Input/input/input Input/input Input/input Input/input/input (Port G) 8-bit input port. (8 pins) Description Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL pulse input pin. Composite sync signal input pin. Measuring pulse signal input pin of pulse cycle measuring unit. External input pin to FRC capture unit. Measuring enable signal input pin of pulse cycle measuring unit. Output (Port H) 8-bit output port; large current, N-ch open drain output. (8 pins) External clock input pin of general purpose prescaler. Connecting pin of crystal oscillation circuit for general purpose prescaler. (Mask option) PI0/PCK /OSCI PI1/PO PI2/PWM PI3/TO PI4/INT1 PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 Input/input/input I/O/output I/O/output I/O/output I/O/input I/O/I/O I/O/output I/O/input I/O (Port I) Lower 1 bit is input port (mask option) and upper 7 bits are I/O port. I/O port can be specified by bit unit. (8 pins) General purpose prescaler output pin. 14-bit PWM output pin. Timer/counter, output pin. (duty = 50%) Input pin to request external interruption. Active when falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. –6– CXP87452/87460 Symbol PK0/OSCO EXTAL XTAL RST MP AVDD AVREF AVSS VDD VSS Input I/O Input/output Input Output I/O Input Input port. (Mask option) Description Connecting pin of crystal oscillation circuit for general purpose prescaler. (Mask opiton) Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. System reset pin of active "L" level. RST pin is I/O pin, which output "L" level by incorporated power on reset function when power on. (Mask option) Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND. –7– CXP87452/87460 Input/Output Circuit Format for Pins Pin PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 PB4/PPO012 /PPO112 to PB5/PPO013 /PPO113 10 pins Port A Port B PPO0 data PPO1 data Port A or Port B Circuit format When reset Hi-Z Data bus RD Output becomes active from high impedance by data writing to port register. Port B PB0/PPO008 to PB3/PPO011 PB6/PPO014 to PB7/PPO015 Data bus PPO0 data Port A or Port B Hi-Z Output becomes active from high impedance by data writing to port register. RD 6 pins Port C PC0/PPO016 to PC2/PPO018 PC3/RTO3 to PC7/RTO7 Data bus PPO, RTO data Port C data IP (Every bit) Input protection circuit Hi-Z Port C direction 8 pins Port D RD (Port C) PD0 to PD7 Port D data IP (Every 4 bits) PD0 to 3 PD4 to 7 RD (Port D) Large current 12mA Hi-Z Port D direction Data bus 8 pins –8– CXP87452/87460 Pin Port E PE1/EC/INT2 IP Circuit format Schmitt input When reset Data bus Hi-Z 1 pin Port E PS1 MPX RD (Port E) PE0/INT0 /XOUT OSCO 1/2 Port E function select register IP Hi-Z Data bus 1 pin Port E RD (Port E) To interruption circuit DA gate output or PWM output PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Hi-Z control Port E data MPX Hi-Z Port E function select register Data bus 4 pins Port E RD (Port E) DA gate output Hi-Z control MPX PE6/DAB0 PE7/DAB1 Port E data H level Port E function select register Data bus RD (Port E) 2 pins –9– CXP87452/87460 Pin AN0 to AN3 4 pins Port F Circuit format Input multiplexer IP A/D converter When reset Hi-Z Input multiplexer IP A/D converter PF0/AN4 to PF3/AN7 Hi-Z Data bus RD (Port F) 4 pins Port F Port F data PF4/AN8 to PF7/AN11 Data bus RD (Port F) Port/AD select Input multiplexer IP Hi-Z 4 pins Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK 8 pins Port H PH0 to PH7 Schmitt input IP A/D converter Pulse cycle measurement unit input Servo input Data bus RD (Port G) Hi-Z Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option. Port H data Hi-Z Data bus RD (Port H) Large current 12mA 8 pins – 10 – CXP87452/87460 Pin Port I Circuit format When reset Port I function select PI1: From general purpose prescaler PI2: From 14-bit PWM PI3: From timer/counter Port I data Port I direction PI1/PO PI2/PWM PI3/TO MPX Hi-Z IP Data bus 3 pins Port I RD (Port I) Port I data PI4/INT1 PI7/SI1 Data bus Port I direction Hi-Z IP RD (Port I) 2 pins PI4: To interruption circuit PI7: To serial CH1 Schmitt input Port I Port I function select From serial CH1 MPX PI5/SCK1 PI6/SO1 Port I data Port I direction MPX Note) PI5 is schmitt input PI6 is inverter input Hi-Z IP Data bus RD (Port I) To serial CH1 2 pins Port J Port J data PJ0 to PJ7 Data bus Port J direction Hi-Z IP RD (Port J) Edge detection 8 pins Standby release – 11 – CXP87452/87460 Pin CS0 SI0 2 pins Circuit format Schmitt input IP To SIO When reset Hi-Z SO0 1 pin SO0 from SIO Hi-Z SO0 output enable Internal serial clock from SIO SCK0 SCK0 output enable External serial clock to SIO IP Hi-Z 1 pin Schmitt input EXTAL XTAL EXTAL IP • Shows the circuit composition during oscillation. • Feedback resistor is removed during stop. Oscillation 2 pins XTAL Mask option Pull-up resistor Schmitt input RST OP IP From power on reset circuit (mask option) L level 1 pin MP 1 pin Port I Port K OSCI IP CPU mode Hi-Z IP Oscillation PI0/PCK/OSCI PK0/OSCO OSCO Fig. 1 PI0/PCK or PK0 IP Data bus Hi-Z 2 pins Note) Circuit format of Fig. 1 or Fig. 2 can be selected with mask option. Fig. 2 RD Port I Port K – 12 – CXP87452/87460 Absolute Maximum Ratings Item Symbol VDD Power supply voltage AVDD AVSS Input voltage Output voltage High level output current High level total output current Low level output current VIN VOUT IOH ∑IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD Rating –0.3 to +7.0 AVss to +7.0∗1 –0.3 to +0.3 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –5 –50 15 20 130 –20 to +75 –55 to +150 600 380 mW Unit V V V V V mA mA mA mA mA °C °C QFP LQFP Total of output pins Remarks (Vss = 0V) Other than large current output pins: per pin Large current output pin∗3: per pin Total of output pins ∗1 AVDD and VDD should be set to a same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. (CS0, SI0, PG and PH excluded.) ∗3 The large current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 13 – CXP87452/87460 Recommended Operating Conditions Item Symbol Min. 3.0 Power supply voltage VDD 2.7 2.5 Analog power supply AVDD VIH VIHS High level input voltage VIHTS VIHEX 3.0 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 VDD VDD 5.5 5.5 Unit V V V V V V V V V V V V V V V V °C Remarks (Vss = 0V) Guaranteed range during high speed mode (1/2 dividing clock) operation Guaranteed range during low speed mode (1/16 dividing clock) operation Guaranteed data hold operation range during STOP ∗1 ∗2 CMOS schmitt input∗3 and PE0/INT0 pins CMOS schmitt input∗4 TTL schmitt input∗5, ∗8 EXTAL pin∗6, ∗8 EXTAL pin∗6, ∗7 ∗2, ∗8 ∗2, ∗7 CMOS schmitt input∗3, ∗4 and PE0/INT0 pins TTL schmitt input∗5, ∗8 EXTAL pin∗6, ∗8 EXTAL pin∗6, ∗7 VDD – 0.4 VDD + 0.3 VDD – 0.2 VDD + 0.2 0.3VDD 0 0 0 –0.3 –0.3 0.2VDD 0.2VDD 0.8 0.4 0.2 +75 VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 –20 AVDD and VDD should be set to a same voltage. Normal input port (each pin of PC, PD, PF0 to PF3, PI PJ, and PK), MP pin. Each pin of SCK0, RST, PE1/EC/INT2, PI1/PO, PI4/INT1, PI5/SCK1 and PI7/SI1. Each pin of CS0, SI0, and PG (for PG and PG5, when CMOS schmitt input is selected.) Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) It specifies only when the external clock is input. In case of 3.0 to 3.6V supply voltage (VDD). In case of 4.5 to 5.5V supply voltage (VDD). – 14 – CXP87452/87460 Electrical Characteristics DC Characteristics Supply voltage (VDD) 4.5 to 5.5V Item High level output voltage Symbol VOH Pin PA to PE, PF4 to PF7, PH (VOL only) PI1 to PI7, PJ, SO, SCK, RST∗1 (VOL only) PD, PH IIHE Input current IILE IILR EXTAL RST∗2 PA to PK, MP, AN0 to AN3, CS, SI, SO, SCK, RST∗2 Condition VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V 0.5 –0.5 –1.5 (Ta = –20 to +75°C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 –400 Typ. Max. Unit V V V V V µA µA µA Low level output voltage VOL I/O leakage current IIZ VDD=5.5V, VI = 0, 5.5V ±10 µA IDD1 Supply current∗3 Crystal oscillation (C1 = C2 = 15pF) of 16MHz VDD = 5V ± 0.5V∗4 VDD SLEEP mode VDD = 5V ± 0.5V 31 50 mA IDDS1 2.0 8.0 mA IDDS3 STOP mode VDD = 5.5V 10 µA Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss pins 10 20 pF ∗1 RST pin specifies only when the power on reset circuit has been selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistance is selected. ∗3 When entire output pins are open. ∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 15 – CXP87452/87460 Supply voltage (VDD) 3.0 to 3.6V Item High level output voltage Symbol VOH Pin PA to PE, PF4 to PF7, PH (VOL only) PI1 to PI7, PJ, SO, SCK, RST∗1 (VOL only) PD, PH IIHE Input current IILE IILR EXTAL RST∗2 PA to PK, MP, AN0 to AN3, CS, SI, SO, SCK, RST∗2 Condition VDD = 3.0V, IOH = –0.15mA VDD = 3.0V, IOH = –0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5.0mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL =0.3V (Ta = –20 to +75°C, Vss = 0V) Min. 2.7 2.3 0.3 0.5 1.0 0.3 –0.3 –0.9 20 –20 –200 Typ. Max. Unit V V V V V µA µA µA Low level output voltage VOL I/O leakage current IIZ VDD = 5.5V, VI = 0, 5.5V ±10 µA IDD2 Supply current∗3 Crystal oscillation (C1 = C2 = 15pF) of 12MHz VDD = 3.3V ± 0.3V∗4 VDD SLEEP mode VDD = 3.3V ± 0.3V 15 30 mA IDDS2 0.8 2.5 mA IDDS3 STOP mode VDD = 5.5V 10 µA Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss pins 10 20 pF ∗1 RST pin specifies only where the power on reset circuit has been selected with mask option. ∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistance is selected. ∗3 When entire output pins are open. ∗4 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 16 – CXP87452/87460 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rising and falling times Event count clock input pulse width Event count clock input rising and falling times Symbol fC Pin XTAL EXTAL XTAL EXTAL XTAL EXTAL PE1/EC PE1/EC Fig. 1, Fig. 2 (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Condition VDD = 4.5 to 5.5V Min. 1 1 28 37.5 200 ns ns 20 ms Max. 16 12 ns Unit MHz tXL, tXH tCR, tCF tEL, tEH tER, tEF VDD = 4.5 to 5.5V Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3 tsys × 4∗ ∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc XTAL EXTAL VDD – 0.4V 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation External clock EXTAL XTAL EXTAL XTAL C1 C2 74HC04 Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF tEL tER – 17 – CXP87452/87460 (2) Serial transfer (CH0) Item CS ↓ → SCK delay time CS ↑ → SCK floating delay time CS ↓ → SO delay time CS ↓ → SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (against SCK ↑) SI input hold time 0 (against SCK ↑) SCK ↓ → SO delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 8000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 100 –tsys + 100 200 2tsys + 100 100 Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL. – 18 – CXP87452/87460 Serial transfer (CH0) Item CS ↓ → SCK delay time CS ↑ → SCK floating delay time CS ↓ → SO delay time CS ↓ → SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (against SCK ↑) SI input hold time (against SCK ↑) SCK ↓ → SO delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns tDCSK tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 150 –tsys + 100 200 2tsys + 100 100 Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF. – 19 – CXP87452/87460 Fig. 4. Serial transfer timing (CH0) tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 20 – CXP87452/87460 Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 100 100 200 tsys + 200 100 tsys + 200 100 ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 150 100 200 tsys + 200 100 tsys + 250 125 ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF. – 21 – CXP87452/87460 Fig. 5. Serial transfer CH1 timing (SIO mode) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 22 – CXP87452/87460 Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time Symbol Pin SO1 SI1 SI1 SI1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Note 1) 2 2 Min. Typ. 104 Max. Unit µs µs µs tLCY tLSU tLHD Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104µs. Note 2) The load of SO1 pin is 50pF + 1TTL. Serial transfer (CH1) (Special mode) Item SO1 cycle time SI1 data setup time SI1 data hold time Symbol Pin SO1 SI1 SI1 SI1 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Condition Note 1) 2 2 Min. Typ. 104 Max. Unit µs µs µs tLCY tLSU tLHD Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock selection) has been set at 104µs. Note 2) The load of SO1 pin is 50pF. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY tLCY SO1 Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD 0.8VDD 0.2VDD SI1 Input data bit – 23 – CXP87452/87460 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Item Resolution Linearity error Absolute error Conversion time Sampling time Only for A/D converter operation Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pin Condition Min. Typ. Max. 8 ±1 ±2 160/fADC 12/fADC AVREF AN0 to AN11 Operating mode AVREF = 4.0 to 5.5V SLEEP mode STOP mode VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VIAN Reference input voltage VREF Analog input voltage AVREF current IREF AVREF A/D converter characteristics Item Resolution Linearity error Absolute error Conversion time Sampling time (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V) Pin Condition Min. Typ. Max. 8 Only for A/D converter operation Ta = 25°C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V ±1 ±2 160/fADC 12/fADC AVREF AN0 to AN11 Operating mode AVREF = 2.7 to 3.6V SLEEP mode STOP mode VDD = AVDD = 3.0 to 3.6V AVDD – 0.3 0 0.4 AVDD AVREF 0.7 10 Unit Bits LSB LSB µs µs V V mA µA Symbol tCONV tSAMP VIAN Reference input voltage VREF Analog input voltage AVREF current IREF AVREF Fig. 7. Definitions of A/D converter terms FFH FEH Digital conversion value ∗ The value of fADC is as follows by selecting ADC Linearity error 01H 00H VZT Analog input VFT operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc – 24 – CXP87452/87460 (4) Interruption, reset input Item External interruption high and low level widths Reset input low level width Symbol (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 PJ0 to PJ7 RST Condition Min. Max. Unit tIH tIL tRSL 1 µs 32/fc µs Fig. 8. Interruption input timing INT0 INT1 INT2 PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 9. Reset input timing tRSL RST 0.2VDD (5) Power on reset Power on reset∗ Item Power supply rising edge Power supply cut-off time Symbol Pin (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Condition Power on reset Repetitive power on reset Min. 0.05 1 Max. 30 Unit ms ms tR tOFF VDD ∗ Specifies only when power on reset function is selected. Fig. 10. Power on reset 3.0V VDD 0.2V 0.2V tR The power supply should rise smoothly. tOFF – 25 – CXP87452/87460 (6) General purpose prescaler Item External clock input frequency External clock input pulse width External clock input rising and falling times Prescaler output delay time (against PCK ↑) Prescaler output rising and falling times Note) The load of PO pin is 50pF. General purpose prescaler Item External clock input frequency External clock input pulse width External clock input rising and falling times Prescaler output delay time (against PCK ↑) Prescaler output rising and falling times Note) The load of PO pin is 50pF. Symbol fPCK Pin PCK PCK PCK PO Symbol fPCK Pin PCK PCK PCK PO (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Min. Typ. Max. 12 33 200 External clock input PCK tR = tF = 6ns External clock input PCK tR = tF = 6ns 80 60 50 20 130 100 100 40 Unit MHz ns ns ns ns ns ns tWH, tWL tR, tF tPLH tPHL tTLH tTHL PO (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Condition Min. Typ. Max. 12 33 200 External clock input PCK tR = tF = 6ns External clock input PCK tR = tF = 6ns 130 90 100 30 220 150 280 70 Unit MHz ns ns ns ns ns ns tWH, tWL tR, tF tPLH tPHL tTLH tTHL PO Fig. 11. General purpose prescaler timing 1/fPCK tWH tF 0.8VDD PCK 0.5VDD 0.2VDD tWL tPLH 0.8VDD PO 0.5VDD 0.2VDD tR tPHL tTLH tTHL – 26 – CXP87452/87460 (7) Others Item CFG input high and low level widths Symbol Pin CFG DFG DPG DPG PBCTL EXI0 EXI1 PMI PMSK (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Condition Min. Max. Unit ns ns ns ns ns ns ns ns tCFH tCFL tDFH DFG input tDFL high and low level widths DPG minimum pulse width tDPW DPG minimum removal time PBCTL input high and low level widths EXI input high and low level widths PMI input high and low level widths PMSK input high and low level widths tFRC × 24 + 200 tFRC × 8 + 200 50 50 trem tCTH tCTL tEIH tEIL tPIH tPIL tPSH tPSL tsys = 2000/fc tsys = 2000/fc tFRC × 8 + tsys + 200 tFRC × 8 + tsys + 200 tsys + 200 tsys + 200 Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The value of tFRC is as follows by selecting FRC clock (FRCS: 01EEH bit 7) When PS0 is selected, tFRC = 1000/fc (ns) When PS1 is selected, tFRC = 2000/fc (ns) – 27 – CXP87452/87460 Fig. 12. Other timings tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD trem tDPW trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH tEIL EXI0 EXI0 0.8VDD 0.2VDD – 28 – CXP87452/87460 tPIH tPIL 0.8VDD PMI 0.2VDD tPSH tPSL 0.8VDD PMSK 0.2VDD – 29 – CXP87452/87460 Supplement Fig. 13. Recommended oscillation circuit Main clock EXTAL XTAL Rd C1 C2 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd (Ω) Circuit example RIVER ELETEC CO., LTD. 10.00 HC-49/U03 12.00 16.00 8.00 22 (15) 15 12 22 (15) 5 5 0 (i) KINSEKI LTD. HC-49/U (-S) 10.00 12.00 16.00 15 12 0 (i) Mask Option Table Item Reset pin pull-up resistor Power on reset circuit Genaral purpose prescaler oscillation circuit Input circuit format∗ Non-existent Non-existent Non-existent CMOS schmitt Content Existent Existent Existent TTL schmitt ∗ In PG4/SYNC0/PMI pin and PG5/SYNC1 pin, the input circuit format can be selected every pin. However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.5V to 5.5V. – 30 – CXP87452/87460 Characteristics Curve IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 1/2 dividing mode 20.0 10.0 1/4 dividing mode 1/16 dividing mode 30 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode IDD – Supply current [mA] 5.0 SLEEP mode 1.0 0.5 IDD – Supply current [mA] 20 1/4 dividing mode 0.1 (100µA) 0.05 (50µA) 10 1/16 dividing mode 0.01 (10µA) 3 4 5 6 7 0 5 10 SLEEP mode 15 16 VDD – Supply voltage [V] fc – System clock [MHz] IDD vs. VDD (fc = 12MHz, Ta = 25°C, Typical) 1/2 dividing mode 20.0 10.0 1/4 dividing mode 1/16 dividing mode 5.0 SLEEP mode 1.0 0.5 30 IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) IDD – Supply current [mA] IDD – Supply current [mA] 20 1/2 dividing mode 0.1 (100µA) 0.05 (50µA) 10 1/4 dividing mode 0.01 (10µA) 3 4 5 6 7 0 5 10 1/16 dividing mode SLEEP mode 15 16 VDD – Supply voltage [V] fc – System clock [MHz] – 31 – CXP87452/87460 Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 26 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 ∗QFP100-P-1414-A – 32 – 0.5 ± 0.2 A (15.0)