CXP87500

CXP87500 CMOS 8-bit Single Chip Microcomputer Description The CXP87500 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP87532/87540. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which LQFP supported QFP supported covers various types of data – 16-bit operation/multiplication and division/ boolean bit operation instructions • Minimum instruction cycle 326ns at 12.288MHz operation • Applicable EPROM LCC type 27C512 (Maximum 40Kbytes are available) • Incorporated RAM capacity 1344bytes • Peripheral functions – Arithmetic coprocessor Signed multiplication and division, signed sum of products. high speed execution of many bits shift rotation operation – A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 13µs/12.288MHz) Incorporated 3-stage FIFO for A/D conversion data – Serial interface Incorporated buffer RAM (auto transfer for 1 to 128bytes), 2-channel – Timer 8-bit timer 8-bit timer/counter 19-bit time base timer – High precision timing pattern generator PPG 11-pin, 32-stage programmable – PWM output 12-bit, 2-channel (repetitive frequency 48kHz) 8-bit, 3-channel (repetitive frequency 48kHz) – Servo input control Capstan FG, drum FG/PG, reel FG input – FRC capture unit Incorporated 28-bit and 8-stage FIFO • Interruption 12 factors, 12 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP87500. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93X12B81-PS CXP87500 Pin Assignment in Piggyback Mode (QFP package) PA2/PPO10 PA3/PROUT PA4/ATFS1 PA5/ATFS3 PA7/ATFS2 PE1/EC/INT2 PB6/PPO6 PB7/PPO7 PA0/PPO8 PA1/PPO9 PA6/AREA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO5 PB4/PPO4 PB3/PPO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 1 2 3 4 5 6 7 80 79 78 77 76 75 74 PE6/PWM4 PE7/SWP PK0/RFDT PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVss SCK0 SO0 SI0 CS0 PH0/SCK1 A12 A15 A14 VDD A13 Vss NMI PE0/INT0 NC PE2/PWM0 VDD PE3/PWM1 PE4/PWM2 PE5/PWM3 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 9 10 11 12 13 14 15 16 17 18 19 20 21 4 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC D1 D2 D3 D4 D5 22 A7 8 NC Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –2– PH3/CS1/INT1 PH1/SO1 PH2/SI1 EXTAL XTAL RST PH7 PH6 PH5 PH4 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Vss MP CXP87500 Pin Assignment in Piggyback Mode (LQFP package) PA3/PROUT PE1/EC/INT2 PA2/PPO10 PA4/ATFS1 PA5/ATFS3 PA7/ATFS2 PE3/PWM1 PE4/PWM2 PE2/PWM0 PE5/PWM3 PE6/PWM4 PB4/PPO4 PB7/PPO7 PA0/PPO8 PA6/AREA PB5/PPO5 PB6/PPO6 PA1/PPO9 VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVSS SCK0 SO0 SI0 PB3/PPO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PJ5 PJ3 PJ0 VSS NC NMI PH7 PE0/INT0 PH2/SI1 PJ1 PE7/SWP PH0/SCK1 EXTAL PH6 PH5 PH4 PH3/CS1/INT1 RST XTAL Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND. –3– PH1/SO1 CS0 PJ6 PJ7 PJ4 PJ2 VSS PI2 PI1 PI0 MP PK0/RFDT CXP87500 Pin Assignment in Evaluator Mode (QFP package) PA2/PPO10 PA3/PROUT PA4/ATFS1 PA5/ATFS3 PE1/EC/INT2 PA7/ATFS2 PB6/PPO6 PB7/PPO7 PA0/PPO8 PA1/PPO9 PA6/AREA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO5 PB4/PPO4 PB3/PPO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 1 2 3 4 5 6 80 79 78 77 76 75 PE6/PWM4 PE7/SWP PK0/RFDT PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVss SCK0 SO0 SI0 CS0 PH0/SCK1 Vss NMI PE0/INT0 PE2/PWM0 PE3/PWM1 NC PE4/PWM2 VDD PE5/PWM3 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7/D7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A12 A15 4 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 3 2 NC 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYNC GND RST WR NC C2 C1 22 A14 VDD A13 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –4– PH3/CS1/INT1 PH1/SO1 PH2/SI1 EXTAL XTAL RST PH7 PH6 PH5 PH4 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Vss MP CXP87500 Pin Assignment in Evaluator Mode (LQFP package) PA2/PPO10 PA5/ATFS3 PE1/EC/INT2 PA3/PROUT PA4/ATFS1 PA7/ATFS2 PE3/PWM1 PE2/PWM0 PE4/PWM2 PE5/PWM3 PE6/PWM4 PA6/AREA PB5/PPO5 PB4/PPO4 PB6/PPO6 PB7/PPO7 PA0/PPO8 PA1/PPO9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 A15 A12 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 RD WR SYNC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 HALT A10 E/P I/T MON RST C1 C2 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PK1/MCLK PK2 PK3 PG0/EXI0 PG1/EXI1 PG2/DREF PG3/DPG PG4/DFG PG5/CFG PG6/RFG0 PG7/RFG1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVSS SCK0 SO0 SI0 PB3/PPO3 PB2/PPO2 PB1/PPO1 PB0/PPO0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI7 PI6 PI5 PI4 PI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NMI VSS PE0/INT0 PH3/CS1/INT1 PH0/SCK1 PH1/SO1 PI2 PI0 PJ7 PH5 PJ0 PH2/SI1 RST XTAL PH7 PH6 Note) 1. NC (Pin 88) is always connected to VDD. 2. VSS (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND. –5– EXTAL PH4 CS0 PJ3 PJ5 PJ2 PJ6 PJ4 PJ1 VSS PI1 MP PK0/RFDT VDD NC PE7/SWP CXP87500 EPROM Read Timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Address → data input delay time Address → data hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 100 Unit ns ns tACC tIH 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Optional item CXP87532 Package ROM capacity Pull-up resistance for reset pin Power on reset circuit Input circuit format∗1 PG0 to PG7, PK1 PK0 Mask CXP87540 Piggyback/evaluator CXP87500-U01Q CXP87500-U01R 100-pin ceramic PQFP EPROM 40Kbytes Existent Existent TTL schmitt Buffer amplifier 100-pin plastic QFP/LQFP 32Kbytes 40Kbytes Existent/Non-existent Existent/Non-existent CMOS schmitt/TTLschmitt Buffer amplifier/Normal input ∗1 On PK1/MCLK pin and PG0/EXI0 to PG7/RFG1 pin, the input circuit format of CMOS schmitt or TTL schmitt can be selected to every pin. On PK0/RFDT pin, buffer amplifier or normal input circuit format can be selected. –6– CXP87500 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe EPROM adaptor Pin 1 marking Note) Evaluator cap should be connected to CPU probe. Pin 1 index CPU probe for LQFP –7– CXP87500 Package Outline Unit: mm 100PIN PQFP (CERAMIC) PIN NO. 1 INDEX INDEX 100 18.7 16.3 ± 0.2 81 81 100 PIN No. 1 INDEX 1 80 80 1 0.65 ± 0.05 4.5 1.27 ± 0.13 22.3 ± 0.25 18.12 ± 0.2 12.02 14.22 24.7 6.0 0.3 1.0 0.7 30 51 51 30 31 9.48 11.66 15.58 ± 0.2 50 1.3 ± 0.3 50 0.45 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 3.57 ± 0.36 JEDEC CODE + 0.05 0.15 – 0.02 0.50 ± 0.25 100PIN PQFP (CERAMIC) 16.0 ± 0.4 14.0 ± 0.2 75 76 0.5 ± 0.05 51 12.4 50 0.5 ± 0.05 3.2 ± 0.2 1.5 0.8 ± 0.2 26 10.44 MAX 0.3 ± 0.08 + 0.08 0.18 – 0.03 INDEX 12.0 ± 0.15 + 0.08 0.18 – 0.03 100 1 INDEX 12.8 ± 0.2 25 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC GOLD PLATING 42 ALLOY 2.2g + 0.05 0.127 – 0.02 + 0.15 0.2 – 0.13 6.9 SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L02 AQFP100-C-1414-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 3.32 –8– 12.0 ± 0.15