CXP87740A

CXP87740A/87748A CMOS 8-bit Single Chip Microcomputer Description The CXP87740A/87748A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, VISS/VASS circuit, 32kHz timer/event counter, remote control receiving circuit, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP87740A/87748A provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation. 100 pin QFP (PIastic) 100 pin LQFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which cover various types of data — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction • Minimum instruction cycle During operation 333ns/12MHz (Supply voltage 3.0 to 5.5V) During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V) During operation 122µs/32kHz • Incorporated ROM capacity 40K bytes (CXP87740A) 48K bytes (CXP87748A) • Incorporated RAM capacity 1344 bytes • Peripheral functions — A/D converter 8-bit, 12-channel, successive approximation system (Conversion time 20.0µs/16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO, 1-channel (1 to 8 bytes auto transfer) 8-bit serial I/O, 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 19 pins 32-stage programmable RTG 5-pins 2-channel — PWM/DA gate output 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz) — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO • Interruption 21 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin plastic QFP/LQFP • Piggyback/evaluation chip CXP87700 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Z16-ST Block Diagram PE0/INT0 PI4/INT1/NMI AVDD AVREF AVss PE1/INT2 TEX TX SPC700 CPU CORE PORT B CLOCK GENERATOR/ SYSTEM CONTROL 8 CS0 SI0 SO0 SCK0 FIFO PORT C PORT A AN0 to AN3 PF0/AN4 to PF7/AN11 2 8 NMI PA0 to PA7 12 A/D CONVERTER EXTAL XTAL RST MP VDD Vss SERIAL INTERFACE UNIT (CH0) PB0 to PB7 PI3/TO/DDO 8 BIT TIMER 1 PORT D PE1/EC 8 BIT TIMER/COUNTER 0 INTERRUPT CONTROLLER PI7/SI1 PI6/SO1 PI5/SCK1 2 ROM 40K/48K BYTES RAM 1344 BYTES SERIAL INTERFACE UNIT (CH1) 8 PC0 to PC7 8 PD0 to PD7 PORT E PG4/SYNC0 PG5/SYNC1 2 2 V SYNC SEPARATOR 2 6 4 4 PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7 PRESCALER/ TIME BASE TIMER DRUM 3 FIFO FIFO FRC CAPTURE UNIT SERVO INPUT CONTROL PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL CTL PORT F PI1/RMC REMOCON INPUT 32kHz TIMER/COUNTER PI2/PWM 14 BIT PWM GENERATOR 2 PORT H VISS/VASS PORT G 12 BIT PWM GENERATOR CH0 2 PE2/PWM0 PE4/DAA0 PE6/DAB0 PE3/PWM1 PE5/DAA1 PE7/DAB1 4 19 CH0 5 CH 1 PI3/ADJ PA0/PPO0 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PORT J 12 BIT PWM GENERATOR CH1 PROGRAMMABLE PATTERN GENERATOR RAM REALTIME PULSE GENERATOR PORT I –2– PG6/EXI0 PG7/EXI1 CAPSTAN 8 PG0 to PG7 8 PH0 to PH7 7 PI1 to PI7 8 PJ0 to PJ7 CXP87740A/87748A CXP87740A/87748A Pin Configuration 1 (Top View) 100 pin QFP package PI3/TO/DDO/ADJ PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 TX TEX VDD PI1/RMC PI2/PWM Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. –3– PF7/AN11 PF6/AN10 PF5/AN9 EXTAL SCK0 XTAL RST SO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 VSS MP SI0 PI5/SCK1 CXP87740A/87748A Pin Configuration 2 (Top View) 100 pin LQFP package PI3/TO/DDO/ADJ PB4/PPO12 PB5/PPO13 PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI PI5/SCK1 PI1/RMC PI2/PWM PI6/SO1 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF TX TEX NC VDD PF5/AN9 PF4/AN8 PI7/SI1 Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. –4– PF7/AN11 PF6/AN10 EXTAL SCK0 XTAL AVSS SO0 RST PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 VSS SI0 MP PE0/INT0 CXP87740A/87748A Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real time Output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port, enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 Output/ Real time Output I/O/ Real time Output I/O/ Real time Output Programmable pattern generator (PPG) output. Functions as high precision real time pulse output port. (19 pins) Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (8 pins) Input pin to request external interruption. Active when falling edge. External event input pin for timer/counter. Input pin to request external interruption. Active when falling edge. PE0/INT0 Input/input PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0 Input/input/input Output/output Output/output Output/output Output/output Output/output Output/output Input Input/input (Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) PWM output pins. (2 pins) DA gate pulse output pins. (4 pins) Analog input pins to A/D converter. (12 pins) (Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins) Output/input I/O Ouput Input Input Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin. –5– CXP87740A/87748A Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 I/O Input/input Input/input Input/input Input/input Input/input Input/input Input/input Input/input (Port G) 8-bit input port. (8 pins) Description Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL pulse input pin. Composite sync signal input pin. External input pin to FRC capture unit. (Port H) 8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open drain output. (8 pins) Remote control receiving circuit input pin. 14-bit PWM output pin. (Port I) 7-bit I/O port. I/O port can be specified by bit unit. (7 pins) Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin. (Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) System reset pin of active "L" level. Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. PH0 to PH7 Output PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD Vss I/O/input I/O/output I/O/output/ output/output I/O/input/Input I/O/I/O I/O/output I/O/input I/O Input Output Input Output Input Input Input Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND. –6– CXP87740A/87748A Input/Output Circuit Formats for Pins Pin Port A Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 PPO data Circuit format When reset Port A or Port B Hi-Z Output becomes active from high impedance by data writing to port register. Data bus RD 16 pins Port C PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 Data bus PPO, RTO data Port C data IP (Every bit) Input protection circuit Hi-Z Port C direction RD (Port C) 8 pins Port D PD0 to PD7 Port D data IP (Every 4 bits) PD0 to 3 PD4 to 7 RD (Port D) High current 12mA Hi-Z Port D direction Data bus 8 pins –7– CXP87740A/87748A Pin Port E Circuit format Schmitt input When reset PE0/INT0 PE1/EC/INT2 IP Hi-Z Data bus RD (Port E) 2 pins Port E DA gate output or PWM output PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Hi-Z control Port E data MPX Hi-Z Port/DA output select Data bus 4 pins Port E RD (Port E) DA gate output Hi-Z control MPX PE6/DAB0 PE7/DAB1 Port E data H level Port/DA output select Data bus 2 pins RD (Port E) AN0 to AN3 4 pins Port F PF0/AN4 to PF3/AN7 Input multiplexer IP A/D converter Hi-Z Input multiplexer IP A/D converter Hi-Z Data bus 4 pins RD (Port F) –8– CXP87740A/87748A Pin Port F Circuit format When reset PF4/AN8 to PF7/AN11 Port F data Data bus RD (Port F) Port/AD select IP Hi-Z A/D converter 4 pins PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port G Schmitt input IP Input multiplexer Servo input Data bus RD (Port G) Hi-Z Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option. Port H PH0 to PH7 Medium withstand voltage 12V Port H data Hi-Z High current 12mA Data bus 8 pins RD (Port H) Port I Port I function select PI2: From 14-bit PWM PI3: From timer/counter, CTL duty detection circuit, 32kHz timer Port I data Port I direction PI2/PWM PI3/TO/ DDO/ADJ MPX Hi-Z IP Data bus 2 pins RD (Port I) –9– CXP87740A/87748A PIn Port I Port I data Circuit format When reset PI1/RMC PI4/INT1/NMI PI7/SI1 Data bus Port I direction IP RD (Port I) Hi-Z 3 pins PI1: To remote control circuit PI4: To interruption circuit PI7: To serial CH1 Schmitt input Port I Port I function select From serial CH1 Port I data Port I direction MPX Note) PI5 is schmitt input PI6 is inverter input RD (Port I) To serial CH1 PI5/SCK1 PI6/SO1 MPX Hi-Z IP Data bus 2 pins Port J Port J data PJ0 to PJ7 Data bus Port J direction Hi-Z IP RD (Port J) Standby release Edge detection 8 pins CS0 SI0 2 pins Schmitt input Hi-Z IP To SIO SO0 SO0 from SIO Hi-Z 1 pin SO0 output enable – 10 – CXP87740A/87748A PIn Circuit format When reset SCK0 Internal serial clock from SIO SCK0 output enable External serial clock to SIO IP Hi-Z 1 pin Schmitt input EXTAL XTAL EXTAL IP • Shows the circuit composition during oscillation. • Feedback resistor is removed during stop. XTAL becomes "H" level. Oscillation 2 pins XTAL TEX TX 32kHz timer counter TEX IP 2 pins TX • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level. Oscillation RST Mask option Pull-up resistor Schmitt input OP IP L level 1 pin MP IP CPU mode Hi-Z 1 pin – 11 – CXP87740A/87748A Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage Medium withstand output voltage High level output current High level total output current Low level output current VIN VOUT VOUTP IOH ∑IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD Rating –0.3 to +7.0 AVss to +7.0∗1 –0.3 to +0.3 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –0.3 to +15.0 –5 –50 15 20 130 –20 to +75 –55 to +150 600 380 mW Unit V V V V V V mA mA mA mA mA °C °C QFP package type LQFP package type Total of output pins PH pin Remarks (Vss=0V) Other than high current output pins: per pin High current port pin∗3: per pin Total of output pins ∗1 AVDD and VDD should be set to a same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The high current operation transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 12 – CXP87740A/87748A Recommended Operating Conditions Item Symbol Min. 4.5 3.0 Supply voltage VDD 2.7 2.7 2.5 Analog power supply AVDD VIH VIHS HIgh level input voltage VIHTS VIHEX 3.0 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V V V V V °C Remarks (Vss = 0V) fc = 16MHz Guaranteed range during high speed mode (1/2 dividing fc = 12MHz clock) operation Guaranteed range during low speed mode (1/16 dividing clock) operation Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP ∗1 ∗2 CMOS schmitt input∗3 TTL schmitt input∗4, ∗7 EXTAL pin∗5, ∗7 EXTAL pin∗5, ∗8 ∗2, ∗7 ∗2, ∗8 CMOS schmitt input∗3 TTL schmitt input∗4, ∗7 EXTAL pin∗5, ∗7 EXTAL pin∗5, ∗8 TEX pin∗6, ∗7 TEX pin∗6, ∗8 TEX pin∗6, ∗7 TEX pin∗6, ∗8 VDD – 0.4 VDD + 0.3 VDD – 0.2 VDD + 0.2 0 0 0 0 –0.3 –0.3 –20 0.3VDD 0.2VDD 0.2VDD 0.8 0.4 0.2 +75 VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr ∗1 AVDD and VDD should be set to a same voltage. ∗2 Normal input port (each pin of PC, PD, PE0 to PE1, PF0 to PF3, PG, PI and PJ), MP pin. ∗3 Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. ∗4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) ∗5 It specifies only when the external clock is input. ∗6 It specifies only when the event count clock is input. ∗7 This case applies to the range of 4.5 to 5.5V supply voltage (VDD). ∗8 This case applies to the range of 3.0 to 3.6V supply voltage (VDD). – 13 – CXP87740A/87748A Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST∗1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 EXTAL Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 –0.5 0.1 –0.1 –1.5 (Ta = –20 to +75°C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 10 –10 –400 Typ. Max. Unit V V V V V µA µA µA µA µA VOL I/O leakage current IIZ VDD = 5.5V, VI = 0, 5.5V ±10 µA Open drain output leakage current (N-CH Tr OFF in state) ILOH PH VDD = 5.5V VOH = 12V 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5V ± 0.5V∗3 SLEEP mode VDD = 5V ± 0.5V 1.3 24 50 µA IDD1 45 mA IDDS1 8 mA Supply current∗2 IDD2 32kHz crystal oscillation (C1 = C2 = 47pF) VDD VDD = 3V ± 0.3V SLEEP mode VDD = 3V ± 0.3V 6 30 µA 35 100 µA IDDS2 IDDS3 STOP mode (EXTAL and TEX pins oscillation stop) VDD = 5V ± 0.5V 10 µA Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 20 pF ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 14 – CXP87740A/87748A DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST∗1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 PH EXTAL Conditions VDD = 3.0V, IOH = –0.15mA VDD = 3.0V, IOH = 0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V (Ta = –20 to +75°C, Vss = 0V) Min. 2.7 2.3 0.3 0.5 1.0 0.3 –0.3 0.1 –0.1 –0.9 20 –20 10 –10 –200 Typ. Max. Unit V V V V V µA µA µA µA µA VOL I/O leakage current IIZ VDD = 3.6V, VI = 0, 3.6V ±10 µA Open drain output leakage current ILOH VDD = 3.6V, VOH = 12V 12MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V ± 0.3V∗3 SLEEP mode 11 50 µA IDD1 25 mA Supply current∗2 IDDS1 VDD VDD = 3.3V ± 0.3V STOP mode (EXTAL and TEX pins oscillation stop) VDD = 3.3V ± 0.3V 0.5 2.5 mA IDDS3 10 µA Input capacity CIN Other than VDD, Clock 1MHz Vss, AVDD, and 0V other than the measured pins AVss 10 20 pF ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When entire output pins are open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 15 – CXP87740A/87748A AC Characteristics (1) Clock timing Item System clock frequency Symbol fC Pins XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 VDD = 4.5 to 5.5V Min. 1 1 28 37.5 200 ns ns 20 32.768 10 20 ns kHz µs ms Max. Unit 16 12 ns MHz System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times tXL, tXH tCR, tCF tEH, tEL tER, tEF fC VDD = 4.5 to 5.5V Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3 tsys × 4∗ tTL, tTH tTR, tTF ∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation External clock 32kHz clock applying condition crystal oscillation EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HC04 C1 C2 – 16 – CXP87740A/87748A Fig. 3. Event count clock timing TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 floating delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input setup time (against SCK0 ↑) SI0 input hold time (against SCK0 ↑) SCK0 ↓ → SO0 delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys+200 tsys+200 tsys+200 tsys+200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 50 100 200 tsys + 200 100 tsys + 200 100 ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 17 – CXP87740A/87748A Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 floating delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input setup time (against SCK0 ↑) SI0 input hold time (against SCK0 ↑) SCK0 ↓ → SO0 delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 100 100 200 tsys + 200 100 tsys + 250 100 ns ns Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF. – 18 – CXP87740A/87748A Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 19 – CXP87740A/87748A Serial transfer (CH1) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pins SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Serial transfer (CH1) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (against SCK1 ↑) SI1 input hold time (against SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pins SCK1 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc – 100 100 200 200 100 250 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load of SCK1 output mode and SO1 output delay time is 50pF. – 20 – CXP87740A/87748A Fig. 5. Serial transfer CH1 timing tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 21 – CXP87740A/87748A (3) A/D converter characteristics Item Resolution Linearity error Absolute error Conversion time Sampling time Symbol (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Pins Conditions Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Min. Typ. Max. 8 ±1 ±2 160/fADC∗ 12/fADC∗ AVREF AN0 to AN11 Operating mode AVREF SLEEP mode STOP mode 32kHz operating mode AVDD – 0.5 0 0.6 1.0 10 AVDD Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25°C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 ±1 ±2 160/fADC∗ 12/fADC∗ AVREF AN0 to AN11 Operating mode AVREF SLEEP mode STOP mode 32kHz operating mode AVDD – 0.3 0 0.4 0.7 10 mA µA AVDD Unit Bits LSB LSB µs µs V tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current IREFS Fig. 6. Definitions of A/D converter terms FFH FEH Digital conversion value ∗ The value of fADC is as follows by selecting ADC Linearity error 01H 00H VZT Analog input VFT operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc – 22 – CXP87740A/87748A (4) Interruption, reset input Item Symbol (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit External interruption high and low level widths tIH tIL tRSL 1 µs Reset input low level width 32/fc µs Fig. 7. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 8. Reset input timing tRSL RST 0.2VDD (5) Others Item CFG input high and low level widths Symbol Pins CFG DFG DPG DPG PBCTL EXI0 EXI1 (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Conditions Min. Max. Unit ns ns ns ns ns ns tCFH tCFL tDFH DFG input tDFL high and low level widths DPG minimum pulse width tDPW DPG minimum removal time PBCTL input high and low level widths EXI input high and low level widths tFRC × 24 + 200 tFRC × 8 + 200 50 50 trem tCTH tCTL tEIH tEIL tsys = 2000/fc tsys = 2000/fc tFRC × 8 + 200 + tsys tFRC × 8 + 200 + tsys Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") tFRC [ns] = 1000/fc – 23 – CXP87740A/87748A Fig. 9. Other timings tCFH tCFL CFG 0.8VDD 0.2VDD tDFH tDFL DFG 0.8VDD 0.2VDD trem tDPW trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH tEIL EXI0 EXI1 0.8VDD 0.2VDD – 24 – CXP87740A/87748A Supplement Fig. 10. Recommended oscillation circuit (i) (ii) EXTAL XTAL Rd TEX TX Rd C1 C2 C1 C2 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd (Ω) Circuit example RIVER ELETEC CO., LTD. HC-49/U03 10.00 12.00 16.00 8.00 5 16 16 12 12 30 5 12 12 12 12 18 0 (i) HC-49/U (-S) KINSEKI LTD. 10.00 12.00 16.00 0 (i) P3 32.768kHz 470k (ii) Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistor Input circuit format∗ Content Non-existent C-MOS schmitt Existent TTL schmitt ∗ In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin. However, TTL schmitt can not be selected when the supply voltage (VDD) ranges from 3.5V to 5.5V. – 25 – CXP87740A/87748A Characteristics Curve IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 20.0 10.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20 IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 1/2 dividing mode IDD – Supply current [mA] 5.0 SLEEP mode 1.0 0.5 32kHz mode (instruction) 32kHz mode SLEEP IDD – Supply current [mA] 15 1/4 dividing mode 10 0.1 (100µA) 0.05 (50µA) 5 0.01 (10µA) 2 3 4 5 6 7 0 10 5 fc – System clock [MHz] 1/16 dividing mode SLEEP mode 16 VDD – Supply voltage [V] IDD vs. VDD (fc = 12MHz, Ta = 25°C, Typical) 20.0 10.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20 IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) IDD – Supply current [mA] 5.0 1.0 0.5 SLEEP mode IDD – Supply current [mA] 15 1/2 dividing mode 10 0.1 (100µA) 0.05 (50µA) 1/4 dividing mode 5 0.01 (10µA) 2 3 4 5 6 7 0 5 10 1/16 dividing mode SLEEP mode 16 VDD – Supply voltage [V] fc – System clock [MHz] – 26 – CXP87740A/87748A Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 25 26 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 ∗QFP100-P-1414-A – 27 – 0.5 ± 0.2 A (15.0)