CXP87940

CXP87940/87948 CMOS 8-bit Single Chip Microcomputer Description The CXP87940/87948 is a CMOS 8-bit single chip microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control reception circuit, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. Also the CXP87940/87948 provides sleep/stop functions which enable to lower power consumption. 100 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V) 122µs at 32kHz operation (2.7V to 5.5V) • Incorporated ROM capacity 40K bytes (CXP87940), 48K bytes (CXP87948) • Incorporated RAM capacity 1376 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0µs at 16MHz) — Serial Interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel Incorporated 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz) DA gate pulse output: 13 bits, 4 channels — Servo input control Capstan FG, drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits — VISS/VASS circuit Pulse duty auto detection circuit — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP • Piggyback/evaluator CXP87800 100-pin ceramic PQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X01-PS Block Diagram AVss INT1/NMI INT2 INT0 TEX TX EXTAL XTAL RST MP VDD Vss AVDD AVREF 2 PORT A AN0 to AN11 8 SPC700 CPU CORE PORT B 12 CLOCK GENERATOR/ SYSTEM CONTROL 8 A/D CONVERTER 2 PA0 to PA7 SCL0 SCL1 SDA0 SDA1 FIFO SERIAL INTERFACE UNIT (CH2) PB0 to PB7 INTERRUPT CONTROLLER CS0 SI0 SO0 SCK0 RAM ROM 40K/48K BYTES RAM 1376 BYTES PORT C SERIAL INTERFACE UNIT (CH0) 8 PC0 to PC7 SI1 SO1 SCK1 FIFO 2 SERIAL INTERFACE UNIT (CH1) EC 8 BIT TIMER/COUNTER 0 PORT D 8 PD0 to PD7 2 6 4 4 PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7 8 BIT TIMER 1 VSYNC SEPARATOR 2 2 SYNC0 SYNC1 EXI0 EXI1 FRC CAPTURE UNIT FIFO PORT F PRESCALER/ TIME BASE TIMER PORT E TO/DDO DRUM 3 FIFO SERVO INPUT CONTROL 32kHz TIMER/COUNTER CFG DFG DPG PBCTL CTL PORT G RMC REMOCON INPUT 2 PWM 14 BIT PWM GENERATOR 12 BIT PWM GENERATOR CH0 2 CH0 CH1 PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 4 12 BIT PWM GENERATOR CH1 19 5 ADJ CKOUT RTO3 to RTO7 PORT J PROGRAMMABLE PATTERN GENERATOR RAM REALTIME PULSE GENERATOR PORT I VISS/VASS PORT H PPO0 to PPO18 –2– CAPSTAN 8 PG0 to PG7 8 PH0 to PH7 7 PI1 to PI7 8 PJ0 to PJ7 CXP87940/87948 CXP87940/87948 Pin Assignment (Top View) PI3/TO/DDO/ADJ PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PI4/INT1/NMI VDD NC VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3/SDA1 PD2/SDA0 PD1/SCL1 PD0/SCL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0/CKOUT PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 TX TEX PI1/RMC PI2/PWM Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. –3– PF7/AN11 PF6/AN10 PF5/AN9 EXTAL SCK0 XTAL RST SO0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 CS0 VSS MP SI0 PI5/SCK1 CXP87940/87948 Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1 PD4 to PD7 PE0/INT0/ CKOUT Output/ Real-time output I/O/ Real-time output I/O/ Real-time output Programmable pattern generator (PPG) output. Functions as high-precision real-time pulse output port. PB0 and PB2 can be 3-state controlled with PPG. (19 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. PC3 can be 3-state controlled with RTG. (5 pins) Serial clock (CH2) I/O. (2 pins) Serial data (CH2) I/O. (2 pins) I/O (Port D) 8-bit I/O port. I/O can be set in a unit of single bits for upper 4 bits. Can drive 12mA sink current. Lower 4-bit output is N-ch open drain. (8 pins) Input to request external interruption. Active at the falling edge. (Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins) Input/Input/Output System clock frequency dividing output. PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0 Input/Input/Input Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input External event Input to request external interruption. input for Active at the falling edge. timer/counter. PWM outputs. (2 pins) DA gate pulse outputs. (4 pins) Analog inputs to A/D converter. (12 pins) (Port F) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pin. (8 pins) Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input. –4– Output/Input I/O Ouput Input Input CXP87940/87948 Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 I/O Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input (Port G) 8-bit input port. (8 pins) Description Capstan FG input. Drum FG input. Drum PG input. Playback CTL pulse input. External event input for timer/counter. Composite sync signal input. (2 pins) External input to FRC capture unit. (2 pins) (Port H) 8-bit output port. N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input. 14-bit PWM output. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Timer/counter, CTL duty detection, 32kHz oscillation adjustment output. Input to request external interruption and non-maskable interruption. Active at the falling edge. Serial clock (CH1) I/O. Serial data (CH1) output. Serial data (CH1) input. (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL and input the opposite phase clock to XTAL . Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz crystal oscillator is inserted between TEX and TX. When used as event input, connect the clock source to TEX and leave TX open. System reset; active at Low level. Test mode input. Always connect to GND. Positive power supply of A/D converter. PH0 to PH7 Output PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD NC Vss I/O/Input I/O/Output I/O/Output/ Output/Output I/O/Input/Input I/O/I/O I/O/Output I/O/Input I/O Input Output Input Output Input Input Input Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. Connect VDD pin to VDD. No connected. Connect to VDD in normal operation. GND. Connect both Vss pins to GND. –5– CXP87940/87948 Input/Output Circuit Formats for Pins Pin Port A Port B PA0 /PPO0 to PA7/PPO7 PB4/PPO12 to PB7/PPO15 PPO data Circuit format When reset Ports A, B data Hi-Z Output becomes active from high impedance by data writing to port register. Data bus RD (Ports A, B) 12 pins PB0/PPO8 PB2/PPO10 PPO8, PPO10 data Hi-Z PB0, PB2 data Data bus RD (Port B) 2 pins PPO9, PPO11 data PPG control status register bit 0 3-state control selection PPO9, PPO11 data Output becomes active from high impedance by data writing to port register. PB1/PPO9 PB3/PPO11 PB1, PB3 data Hi-Z Data bus RD (Port B) Output becomes active from high impedance by data writing to port register. 2 pins –6– CXP87940/87948 Pin Port C Circuit format When reset PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7 PPO, RTO data Port C data IP Input protection circuit Hi-Z Port C direction “0” when reset Data bus RD (Port C) 6 pins RTO3 data PC3 data PC3/RTO3 PC3 direction “0” when reset IP Data bus RD (Port C) RTO4 data Hi-Z 1 pin RTG interruption control register bit 7 3-state control selection “0” when reset RTO4 data PC4 data PC4/RTO4 PC4 direction “0” when reset Data bus RD (PortC) RTO data is OR-gate data of CH0 and CH1. IP Hi-Z 1 pin –7– CXP87940/87948 Pin Port D Circuit format When reset SCL, SDA Serial interface CH2 output enable ∗ PD0/SCL0 PD1/SCL1 PD2/SDA0 PD3/SDA1 Port D data Data bus RD (Port D) SCL, SDA (Serial interface CH2 circuit) Schmitt input IP Hi-Z BUS SW To another serial CH2 pin ∗ Large current 12mA 4 pins Port D PD4 to PD7 Port D data ∗ Hi-Z Port D direction “0” when reset Data bus IP 4 pins Port E RD (Port D) ∗ Large current 12mA ESL0 Port E selection ESL1 PE0/INT0/ CKOUT PS1 PS2 PS3 01 10 MPX 11 Hi-Z IP Data bus 1 pin Interruption circuit RD (Port E) –8– CXP87940/87948 Pin Port E IP Circuit format When reset PE1/EC/INT2 Data bus RD (Port E) Interruption circuit/ event counter Hi-Z 1 pin Port E DA gate output, PWM output PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 Hi-Z control Port E data MPX Hi-Z Port/DA output selection “0” when reset Data bus 4 pins Port E RD (Port E) DA gate output Hi-Z control MPX PE6/DAB0 PE7/DAB1 Port E data Port/DA output selection “1” when reset Data bus High level 2 pins RD (Port E) AN0 to AN3 4 pins Input multiplexer Hi-Z IP A/D converter –9– CXP87940/87948 Pin Port F PF0/AN4 to PF3/AN7 IP Circuit format Input multiplexer A/D converter When reset Hi-Z Data bus 4 pins Port F PF4/AN8 to PF7/AN11 Port F data RD (Port F) Data bus RD (Port F) Port/AD selection “0” when reset A/D converter IP Hi-Z 4 pins Input multiplexer Port G PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port H ∗ Schmitt input IP Servo input Data bus RD (Port G) Note) For PG4/SYNC0, PG5/SYNC1, CMOS Schmitt input and TTL Schmitt input can be selected with the mask option. Hi-Z PH0 to PH7 Port H data Hi-Z Data bus ∗ Large current 12mA Medium drive voltage 12V 8 pins RD (Port H) – 10 – CXP87940/87948 Pin Port I Circuit format Port I function selection “0” when reset PI2...14-bit PWM PI3...Timer/counter, CTL duty detection circuit, 32kHz timer Port I data Port I direction “0” when reset Data bus When reset PI2/PWM PI3/TO/ DDO/ADJ MPX Hi-Z IP 2 pins RD (Port I) Port I Port I data PI1/RMC PI4/INT1/NMI PI7/SI1 Data bus Port I direction “0” when reset IP Hi-Z RD (Port I) 3 pins Port I PI1...Remote control circuit PI4...Interruption circuit PI7...Serial interface CH1 Schmitt input Port I function selection “0” when reset Serial interface CH1 Port I data Port I direction “0” when reset Data bus MPX PI5/SCK1 PI6/SO1 MPX Hi-Z IP 2 pins Port J RD (Port I) Serial interface CH1 PI6 is not Schmitt input. Port J data Port J direction PJ0 to PJ7 Data bus “0” when reset IP RD (PortJ) Standby release Data bus Hi-Z Edge detection 8 pins RD (Port J direction) – 11 – CXP87940/87948 Pin CS0 SI0 2 pins Circuit format Schmitt input IP CS0 Serial interface CH0 SIO When reset Hi-Z SO0 SO0 Serial interface CH0 Hi-Z 1 pin SO0 output enable SCK0 SCK0 Serial interface CH0 SCK0 output enable SCK0 IP Hi-Z 1 pin Schmitt input EXTAL XTAL EXTAL IP • Shows the circuit composition during oscillation. • Feedback resistor is removed during stop mode and XTAL becomes High level. Oscillation 2 pins XTAL TEX TX 32kHz timer/counter TEX IP 2 pins TX • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level. Oscillation RST Mask option Pull-up resistor Schmitt input OP Low level 1 pin IP – 12 – CXP87940/87948 Absolute Maximum Ratings Item Symbol VDD AVDD Supply voltage AVSS AVREF Input voltage Output voltage Medium drive output voltage High level output current VIN VOUT VOUTP IOH Symbol –0.3 to +7.0 AVss to +7.0∗1 –0.3 to +0.3 AVss to +7.0∗1 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –0.3 to +15.0 –5 –50 15 20 130 –20 to +75 –55 to +150 600 Unit V V V V V V V mA mA mA mA mA °C °C mW Total of output pins Port H pin (Vss = 0V reference) Unit High level total output current ∑IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD Ports excluding large current output (value per pin) Large current output port (value per pin∗3) Total of output pins ∗1 AVDD and AVREF should not exceed VDD + 0.3V. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The large current output ports are the pins of the port D (PD) and Port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 13 – CXP87940/87948 Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.0 Analog voltage AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 4.5 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD 5.5 5.5 Unit V V V V V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes Guaranteed operation range for 1/16 frequency dividing mode or during sleep mode Guaranteed operation range by TEX clock Guaranteed data hold range during stop mode ∗1 Includes the serial CH2 input∗2 CMOS Schmitt input∗3 and PE0/INT0 pin CMOS Schmitt input∗7 TTL Schmitt input∗4 EXTAL pin∗5 and TEX pin∗6 Includes the serial CH2 input∗2 CMOS Schmitt input∗3 and PE0/INT0 pin TTL Schmitt input∗4 EXTAL pin∗5 and TEX pin∗6 Supply voltage VDD VDD – 0.4 VDD + 0.3 0 0 0 –0.3 –20 0.3VDD 0.2VDD 0.8 0.4 +75 AVDD and VDD should be set to the same voltage. Normal input port (PC, PD4 to PD7, PF0 to PF3, PG, PI and PJ), MP pin SCK0, RST, EC/INT2, RMC, INT1/NMI, SCK1 and SI1 PG4 and PG5 (When TTL Schmitt input is selected with mask option) Specifies only when the external clock is input. Specifies only when the external event count clock is input. CS0, SI0, and PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option.) – 14 – CXP87940/87948 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Symbol VOH Pins PA to PC, PD4 to PD7, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH PD0 to PD3 (SCL0, CSL1 SDA0, SDA1) IIHE IILE Input current IIHT IILT IILR RST∗1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST∗1 PH PD0 to PD3 TEX VDD = 5.5V, VIL = 0.4V EXTAL Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 6.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V 0.5 –0.5 0.1 –0.1 –1.5 (Ta = –20 to +75°C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 –40 10 –10 –400 Typ. Max. Unit V V V V V V V µA µA µA µA µA Low level output voltage VOL I/O leakage current IIZ VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V VOH = 12V VDD = 5.5V VOH = 5.5V ±10 µA Open drain output leakage ILOH current (in N-CH Tr off state) Serial interface CH2 bus switch connection impedance (in output Tr off state) 50 10 µA µA RBS VDD = 4.5V SCL0: SCL1 VSCL0 = VSCL1 = 2.25V SDA0: SDA1 VSDA0 = VSDA1 = 2.25V 120 Ω – 15 – CXP87940/87948 Item Symbol IDD1 Pins Conditions 1/2 frequency dividing clock operation VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 16pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Sleep mode Min. Typ. 36 Max. 50 Unit mA IDD2 Supply current∗2 60 100 µA IDDS1 VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 16pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation 2.8 8 mA IDDS2 10 30 µA IDDS3 10 µA Input capacity CIN PC, PD, PE0, PE1, PF, PG, PI1 to PI7, PJ, CS0, Clock 1MHz SI0, SCK0, 0V for all pins excluding measured AN0 to AN3, pins EXTAL, XTAL, TEX, TX, MP, RST 10 20 pF ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. ∗2 When all output pins are open. – 16 – CXP87940/87948 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times System clock frequency Event count input clock pulse width Event count input clock rise and fall times Symbol fC Pins (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 28 200 4tsys∗1 20 32.768 10 20 Typ. Max. 16 Unit MHz ns ns ns ns kHz µs ms XTAL Fig. 1, EXTAL Fig. 2 XTAL Fig. 1, EXTAL Fig. 2 (External clock drive) XTAL Fig. 1, Fig. 2 EXTAL (External clock drive) EC EC TEX TX TEX TEX Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3 tXL, tXH tCR, tCF tEH, tEL tER, tEF fC tTL, tTH tTR, tTF ∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation EXTAL C1 XTAL C2 EXTAL XTAL C1 TEX TX C2 74HC04 Fig. 3. Event count clock timing 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR TEX EC – 17 – CXP87940/87948 (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 floating delay time CS0 ↓ → SO0 delay time CS0 ↓ → SO0 floating delay time CS0 High level width SCK0 cycle time SCK0 High and Low level widths SI0 input setup time (for SCK0 ↑) SI0 input hold time (for SCK0 ↑) SCK0 ↓ → SO0 delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO tsys + 100 8000/fc – 100 –tsys + 100 200 2tsys + 100 100 Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 18 – CXP87940/87948 Fig. 4. Serial transfer CH0 timing tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD – 19 – CXP87940/87948 Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO tsys +100 8000/fc – 50 100 200 tsys + 200 100 tsys + 200 100 ns ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing (SIO mode) tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data – 20 – CXP87940/87948 Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SO1 cycle time SI1 data setup time SI1 data hold time ∗1 Symbol Pin SO1 SI1 SI1 SI1 ∗1 2 2 Condition Min. Typ. 104 Max. Unit µs µs µs tLCY tLSU tLHD tLCY is specified only when serial mode register (CH1) (SIOM1: 05FZH) lower 2 bits (SO1 clock selection) are set at 104µs. Note) The load of SO1 pin is 50pF + 1TTL. Fig. 6. Serial transfer CH1 timing (Special mode) tLCY tLCY SO1 Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD 0.8VDD 0.2VDD SI1 Input data bit – 21 – CXP87940/87948 Serial transfer (CH2) Item SCL0, SCL1 clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA0, SCL0, SDA1, SCL1 rise time SDA0, SCL0, SDA1, SCL1 fall time Setup time for transfer completion (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL0, SCL1 SDA0, SCL1 SDA0, SCL1 SDA0, SCL1 SDA1, SCL1 SCL0, SCL1 SCL0, SCL1 SDA0, SCL0 SDA0, SCL1 SDA0, SCL0 SDA1, SCL1 SDA0, SCL0 SDA1, SCL1 SDA0, SCL0 SDA1, SCL1 SDA0, SCL0 SDA1, SCL1 SDA0, SCL0 SDA1, SCL1 1.6 2.6 1.0 1.0 1.0 1.0 0∗1 100 300 300 Condition Min. Max. 400 Unit kHz µs µs µs µs µs µs ns ns ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗1 The SCL0, SCL1 fall time (300ns Max.) is not included in the data hold time. Fig. 7. Serial transfer CH2 timing SDA0 SDA1 tBUF SCL0 SCL1 P tR tF tHD; STA tHD; STA tSU; STA S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P Fig. 8. Device recommended circuit Device Device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS R S RP RP • A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 22 – CXP87940/87948 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 ±1 ±2 160/fADC∗1 12/fADC∗1 AVREF AN0 to AN11 Operation mode AVREF IREFS Sleep mode Stop mode 32kHz operation mode AVDD – 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current Fig. 9. Definitions of A/D converter terms FFH FEH Digital conversion value ∗1 fADC indicates the below values due to the peripheral clock control register (PCC: 05F8H) bit 3 and clock control register (CLC: 00FEH) upper 2 bits. PCC bit 3 CLC upper 2 bits Linearity error 0 (φ/2 selection) 1 (φ selection) fADC = fc/2 fADC = fc/4 fADC = fc/16 fADC = fc fADC = fc/2 fADC = fc/8 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16) 01H 00H Analog input – 23 – CXP87940/87948 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit External interruption High and Low level widths tIH tIL tRSL 1 µs Reset input Low level width 32/fc µs Fig. 10. Interruption input timing INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 11. RST input timing tRSL RST 0.2VDD (5) Others Item CFG input High and Low level widths Symbol Pins CFG DFG DPG DPG PBCTL EXI0 EXI1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 24tFRC + 200 16tFRC + 200 8tFRC + 200 16tFRC + 200 Max. Unit ns ns ns ns ns ns tCFH tCFL DFG input tDFH High and Low level widths tDFL DPG minimum pulse width tDPW DPG minimum removal time PBCTL input High and Low level widths trem tCTH tCTL EXI input tEIH High and Low level widths tEIL tsys = 2000/fc tsys = 2000/fc 8tFRC + 200 + tsys 8tFRC + 200 + tsys Note 1) tFRC = 1000/fc [ns] Note 2) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) – 24 – CXP87940/87948 Fig. 12. Other timings tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD tDPW trem trem 0.8VDD DPG tCTH tCTL 0.8VDD PBCTL 0.2VDD tEIH tEIL EXI0 EXI1 0.8VDD 0.2VDD – 25 – CXP87940/87948 Appendix Fig. 13. Recommended oscillation circuit for SPC 700 series (i) (ii) EXTAL XTAL Rd TEX TX Rd C1 C2 C1 C2 Manufacturer Model fc (MHz) 8.00 C1 (pF) 10 C2 (pF) 10 Rd (Ω) Circuit example RIVER ELETEC CO., LTD. 10.00 HC-49/U03 12.00 16.00 8.00 HC-49/U (-S) 10.00 12.00 16.00 P3 32.768kHz 16 16 12 12 30 16 16 12 12 18 5 5 0 (i) 0 (i) KINSEKI LTD. 470k (ii) Mask option table Item Reset pin pull-up resistor Input circuit format∗1 Non-existent C-MOS Schmitt Content Existent TTL Schmitt ∗1 The input circuit format can be selected for PG4/SYNC0 and PG5/SYNC1, respectively. – 26 – CXP87940/87948 Characteristics Curve IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) IDD vs. fc (VDD = 5.0V, Ta = 25°C, Typical) 1/2 dividing mode 1/4 dividing mode 10 1/16 dividing mode Sleep mode 40 30 IDD – Supply current [mA] 1 32kHz mode (instruction) 0.1 32kHz Sleep mode IDD – Supply current [mA] 20 1/2 dividing mode 0.01 (10µA) 10 1/4 dividing mode 1/16 dividing mode Sleep mode 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD – Supply voltage [V] 5.5 6.0 0 5 10 fc – System clock [MHz] 15 – 27 – CXP87940/87948 Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 A 0.65 ±0.12 M + 0.35 2.75 – 0.15 0.15 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g – 28 –