CXP88100A

CXP88100A CMOS 8-bit Single Chip Microcomputer Description The CXP88100 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP88132/88140/88152/88160/88216/88220/88224. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features • A wide instruction set (213 instructions) which cover various types of data. — 16-bit operation/multiplication and division/ boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Applicable EPROM LCC type 27C512 (Maximum 60Kbytes are available.) • Incorporated RAM capacity 1296 bytes • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 20.0µs/16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO (auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronous type, 1 channel — Timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32kHz timer/counter — High precision timing pattern generator PPG 8-pin, 21-stage programmable, RTG 5 pins, 2 channels — PWM/DA gate output PWM output 12 bits 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output 13 bits, 4 channels — Servo input control Capstan FG, drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO — Fluorescent display panel controller/driver Maximum 144 segments display possible Hardwave key scan function (Maximum 16 x 3 key matrix compatible.) — Tri-state output PPG output 1 pin, RTG output 1 pin, output 8 pins — Psendo HSYNC output function — High-speed head switching circuit • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 100-pin ceramic QFP Note) Mask option depends on the type of the CXP88100A. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95626-ST CXP88100A Pin Assignment in Piggyback Mode PI3/TO/DDO/ADJ PI4/INT1/NMI/CS0 PH0/KR0 PH1/KR1 PH2/KR2 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB0 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2 PC1 PC0 PA7/PPO7 (HAMP) PA6/PPO6 (ROTA) PA5/PPO5 (RF-PLS) PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0/HGO PF7 PF6/SI1 PF5/SO1 PF4/SCK1 PF3/AN7 PF2/AN6 PF1/AN5 PF0/AN4 AN3 AN2 AVREF AVSS AVDD 1 2 3 4 5 6 80 79 78 77 76 75 PI6/SO0 PI7/SI0 VFDP PD0/S0 PD1/S1 PD2/S2 PD3/S3 PD4/S4 PD5/S5 PD6/S6 PD7/S7 T15/S8 T14/S9 T13/S10 T12/S11 T11/S12 T10/S13 T9/S14 T8/S15 T7 T6 T5 T4 T3 T2 T1 T0 PE0/INT0 (ENV-DET) PE1/EC0/INT2 PE2/PWM0 TX TEX VDD PI1/RMC PI2/PWM PI5/SCK0 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A12 A15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 A7 4 3 2 NC 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 14 15 16 17 18 19 20 A14 D4 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC D1 D2 D3 D5 A13 7 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. PG4/SYNC0/EC2 PG3/PBCTL/EC1 PG5/SYNC1 –2– PE3/PWM1 PE7/DAB1 PE6/DAB0 PE5/DAA1 PE4/DAA0 PG7/EXI1 PG6/EXI0 PG2/DPG PG1/DFG PG0/CFG EXTAL XTAL RST AN1 AN0 VSS MP CXP88100A Pin Assignment in Evaluator Mode PI3/TO/DDO/ADJ PI4/INT1/NMI/CS0 PH0/KR0 PH1/KR1 PH2/KR2 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB0 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2 PC1 PC0 PA7/PPO7 (HAMP) PA6/PPO6 (ROTA) PA5/PPO5 (RF-PLS) PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0/HGO PF7 PF6/SI1 PF5/SO1 PF4/SCK1 PF3/AN7 PF2/AN6 PF1/AN5 PF0/AN4 AN3 AN2 AVREF AVSS AVDD 1 2 3 4 5 6 80 79 78 77 76 75 PI6/SO0 PI7/SI0 VFDP PD0/S0 PD1/S1 PD2/S2 PD3/S3 PD4/S4 PD5/S5 PD6/S6 PD7/S7 T15/S8 T14/S9 T13/S10 T12/S11 T11/S12 T10/S13 T9/S14 T8/S15 T7 T6 T5 T4 T3 T2 T1 T0 PE0/INT0 (ENV-DET) PE1/EC0/INT2 PE2/PWM0 A7/D7 TX TEX VDD PI1/RMC PI2/PWM PI5/SCK0 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A12 A15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 4 3 2 NC 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 A14 C1 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYNC GND RST WR NC C2 A13 7 PG3/PBCTL/EC1 Note) 1. NC (Pin 90) is always connected to VDD. 2. VSS (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND. PG4/SYNC0/EC2 PG5/SYNC1 –3– PE3/PWM1 PE7/DAB1 PE6/DAB0 PE5/DAA1 PE4/DAA0 PG2/DPG PG7/EXI1 PG6/EXI0 PG1/DFG PG0/CFG RST MP EXTAL XTAL AN1 AN0 VSS CXP88100A EPROM Read Timing (Ta=–20 to +75°C, VDD=4.5 to 5.5V, VSS=0V) Item Address → data input delay time Address → data hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 75 Unit ns ns tACC tIH 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Mask product CXP CXP CXP CXP CXP CXP CXP 88132 88140 88152 88160 88216 88220 88224 Package ROM capacity Pull-up resistor for reset pin Input circuit format∗1 Pull-down resistor for high voltage drive pin 32K bytes 40K bytes 100-pin plastic QFP 52K bytes 60K bytes 16K bytes 20K bytes 24K bytes Piggyback/evaluator product CXP88100A-U01Q 100-pin ceramic PQFP EPROM 60Kbytes Existent TTL schmitt Existent∗2 Existent/Non-existent CMOS schmitt/TTL schmitt Existent/Non-existent ∗1 On PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin. ∗2 Not exist on PD0/S0 to PD7/S7. –4– CXP88100A Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe Note) Evaluation cap should be connected to CPU probe. Package Outline Unit: mm 100PIN PQFP (CERAMIC) PIN NO. 1 INDEX INDEX 100 18.7 16.3 ± 0.2 81 81 100 PIN No. 1 INDEX 1 80 80 1 4.5 1.27 ± 0.13 22.3 ± 0.25 18.12 ± 0.2 12.02 14.22 24.7 6.0 0.3 1.0 0.7 30 51 51 30 31 9.48 11.66 15.58 ± 0.2 50 1.3 ± 0.3 50 0.45 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 3.57 ± 0.36 JEDEC CODE + 0.05 0.15 – 0.02 0.50 ± 0.25 10.44 MAX –5– 0.3 ± 0.08 0.65 ± 0.05