CXP913040

CXP913040 CMOS 16-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP913040 is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface with an incorporated buffer RAM, highprecision timing pattern generation function, pulse cycle measurement circuit, PWM generator, generalpurpose prescaler, vertical sync separation circuit, and a measurement circuit which measures the signals of capstan FG, drum FG/PG, reel FG and other servo systems with high precision, as well as basic configurations like a 16-bit CPU, ROM, RAM, and I/O port. This LSI also provides sleep/stop modes that enable lower power consumption. 100 pin LQFP (Plastic) Structure Silicon gate CMOS IC Features • An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS — Highly quadratic instruction system, general-purpose register of 16-bit × 8-pin × 16-bank configuration • Minimum instruction cycle time 100ns at 20MHz operation • Incorporated ROM capacity 160K bytes • Incorporated RAM capacity 6144 bytes • Peripheral functions — A/D converter 8-bit 12-channel successive approximation system, automatic scanning function, 8-stage (soft) + 4-stage (hard) FIFO for conversion results (Conversion time: 20µs at 20MHz) — Serial interface Buffer RAM (128 bytes, supports high-speed transfer mode), 3 channels — Timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel 16-bit capture timer/counter (with timing output), 1 channel 16-bit timer, 4 channels — High-precision timing pattern generator PPG for 27 pins, 42 stages (max.) PPG for 16 pins, 16 stages (max.) RTG for 5 pins, 3 channels — PWM/DA gate output PWM for 14 bits, 2 channels (Repetitive frequency of 39.1kHz, 20MHz) DA gate pulse for 14 bits, 2 channels — Servo input control Capstan FG, drum FG/PG, reel FG — VSYNC separator — FRC capture unit 24-bit and 8-stage FIFO — PWM output 14 bits, 2 channels — General-purpose prescaler 10 bits, 1 channel — Pulse cycle measurement circuit 1 channel with mask input • General-purpose I/O 80 pins (max.; when all multi-purpose pins are used as general-purpose I/O.) • Interruption 28 factors, 28 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin plastic LQFP • Piggy/evaluation chip CXP913000 100-pin ceramic LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X05-PS Block Diagram INT2 INT1 INT0 NMI EXTAL XTAL RST VDD Vss CS0 SI0 SO0 SCK0 SPC900 CPU CORE PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I CLOCK GENERATOR/ SYSTEM CONTROLLER 8 8 CS1 SI1 SO1 SCK1 RAM RAM 2 ROM 160K BYTES RAM 6144 BYTES SERIAL INTERFACE UNIT (CH1) PORT A SERIAL INTERFACE UNIT (CH0) RAM EC0 2 8-BIT TIMER/COUNTER 0 INTERRUPT CONTROLLER CS2 SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) 8 8 T1 8-BIT TIMER 1 EC2 CINT T2 4 4 FRC CAPTURE UNIT FIFO 16-BIT CAPTURE TIMER/COUNTER 8 SYNC0 SYNC1 V SYNC SEPARATOR PRESCALER 16-BIT TIMER (× 4ch) 4 4 6 2 2 3 3 REAL-TIME PULSE GENERATOR FIFO CH0 CH1 CH2 10 5 12 A/D CONVERTER PROGRAMMABLE PATTERN (CH0) RAM GENERATOR 4 4 FIFO PMI PMSK 19 PULSE MEASURE UNIT RTO0 to RTO4 PPO000 to PPO018 PPO100 to PPO109 AVSS AVREF AVDD AN0 to AN11 PORT J –2– SERVO INPUT CONTROL 2 PROGRAMMABLE PATTERN (CH1) RAM GENERATOR DRUM CAPSTAN REEL DFG DPG CFG RFG0 RFG1 EXI0 EXI1 2 PO PCK/OSCI (OSCO) XOUT PROGRAMMABLE PRESCALER 8 PWM0 PWM1 DA0 DA1 14-BIT PWM/DA GENERATOR (× 2ch) 4 4 PWM2 PWM3 14-BIT PWM GENERATOR (× 2ch) 8 CXP913040 CXP913040 Pin Configuration (Top View) PB1/PPO009/PPO109 PB0/PPO008/PPO108 PA7/PPO007/PPO107 PA6/PPO006/PPO106 PA5/PPO005/PPO105 PA4/PPO004/PPO104 PA3/PPO003/PPO103 PA2/PPO002/PPO102 PA1/PPO001/PPO101 PA0/PPO000/PPO100 PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PB3/PPO011 PB2/PPO010 PJ1/AN5/KS9 PJ0/AN4/KS8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB4/PPO012 PB5/PPO013 PB6/PPO014 PB7/PPO015 PC0/PPO016 PC1/PPO017 PC2/PPO018 PC3/RTO0 PC4/RTO1 PC5/RTO2 PC6/RTO3 PC7/RTO4 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AVSS AN3 AN2 AN1 PI7/AN0 VSS PI6/XOUT PI5/OSCO PI4/PCK/OSCI PI3/CS2/PO PI2/SCK2 PI1/SO2 PI0/SI2 SCK0 SO0 SI0 CS0 PH7/CFG PH6/DFG PH5/DPG PH4/PMSK PH3/SYNC1 PH2/SYNC0/PMI PH1/EXI1 PH0/EXI0 VDD VDD VSS Note) 1. Vss (Pins 13, 39, 70 and 88) must be connected to GND. 2. VDD (Pins 42, 86 and 87) must be connected to VDD. PF2/CS1/NMI/CINT PF0/EC0/INT0 PF1/EC2/INT1 PF3/SI1/INT2 –3– PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG6/RFG0 PG7/RFG1 PF5/SCK1 PG4/DA0 PG5/DA1 EXTAL RST PF7/T2 PF4/SO1 PF6/T1 XTAL PE4 PE5 PE6 PE7 VDD VSS AVREF AVDD CXP913040 Pin Description Symbol PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 PB0/PPO008 /PPO108 PB1/PPO009 /PPO109 PB2/PPO010 to PB7/PPO015 PC0/PPO016 to PC2/PPO018 PC3/RTO0 to PC7/RTO4 I/O Output / Real time output / Real time output (Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO0 and PPO1 contents by ORgate and they are output. (8 pins) Programmable pattern generator (PPG0, PPG1) output. Functions as high-precision real-time pulse output port. (PPG0 19 pins, PPG1 10 pins) Functions Output / Real time output / Real time output Output / Real time output Output / Real time output Output / Real time output (Port C) 8-bit I/O port. I/O can be specified by bit unit. Data is gated with PPO0 or RTO contents by ORgate and they are output. (8 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. Can drive 12mA sink current when VDD = 5V. (8 pins) (Port E) 8-bit I/O port. I/O can be specified by bit unit. Can drive 12mA sink current when VDD = 5V. (8 pins) External event input for timer/counter. (2 pins) Serial chip select (CH1) input. Input to request external interruption. Active at the falling edge. (2 pins) External capture input for 16-bit timer/counter. PE0 to PE7 I/O PF0/EC0/ INT0 PF1/EC2/ INT1 PF2/CS1/ NMI/CINT Input / Input / Input Input / Input / Input Input / Input / Input / Input (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. (8 pins) Input to request non-maskable interruption. Active at the falling edge. PF3/SI1/INT2 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2 Input / Input / Input Output / Output Output / I/O Output / Output Output / Output Serial data (CH1) input. Serial data (CH1) output. Serial data (CH1) I/O. 8-bit timer/counter output. Input to request external interruption. Active at the falling edge. 16-bit capture timer/counter output. –4– CXP913040 Symbol PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 PG6/RFG0 PG7/RFG1 PH0/EXI0 PH1/EXI1 PH2/ SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG SCK0 SO0 SI0 CS0 PI0/SI2 PI1/SO2 PI2/SCK2 PI3/CS2/PO PI4/PCK/ OSCI PI5/OSCO PI6/XOUT PI7/AN0 AN1 to AN3 I/O Output / Output Output / Output Output / Output Output / Output Output / Output Output / Output Input / Input Input / Input Input / Input Input / Input Input / Input / Input Input / Input Input / Input Input / Input Input / Input Input / Input I/O Output Input Input I/O / Input (Port I) 8-bit port. I/O / I/O Lower 4 bits I/O / Input / Output are for I/O; upper 4 bits Input / Input / are for input. Input Lower 4 bits can be Input / Output specified by bit unit. Input / Output (8 pins) Input / Input I/O / Output Input (Port J) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. (8 pins) –5– (Port H) 8-bit input port. (8 pins) (Port G) 8-bit port. Lower 6 bits are for output; upper 2 bits are for input. (8 pins) Functions 14-bit PWM output. (4 pins) DA gate pulse output. (2 pins) Reel FG input. (2 pins) External input for FRC capture unit. (2 pins) Composite sync signal input. (2 pins) Pulse input for pulse cycle measurement circuit. Mask input for pulse cycle measurement circuit. Drum PG input. Drum FG input. Capstan FG input. Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input. Serial data (CH2) input. Serial data (CH2) output. Serial clock (CH2) I/O. Serial chip select (CH2) input. General-purpose prescaler output. General-purpose Connects a crystal for generalprescaler external clock input. purpose prescaler clock oscillation. (Mask option) Clock output from clock generator or general-purpose prescaler. PJ0/AN4 to PJ7/AN11 Analog input for A/D converter. (12 pins) I/O / Input CXP913040 Symbol EXTAL XTAL RST AVDD AVREF AVSS VDD VSS Input Input Output I/O I/O Functions Connects a crystal for system clock oscillation. When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL. System reset. Active at "L" level. Positive power supply for A/D converter. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. All three VDD pins must be connected to the positive power supply. GND. All four VSS pins must be connected to GND. –6– CXP913040 I/O Circuit Format for Pins Pin PA0/PPO000/ PPO100 to PA7/PPO007/ PPO107 PB0/PPO008/ PPO108 to PB1/PPO009/ PPO109 10 pins Port B PPO0 data Circuit format Port A Port B PPO0 data PPO1 data Port A or Port B data Output becomes active from Hi-Z by writing data to port register. RD When reset Hi-Z Data bus PB2/PPO010 to PB7/PPO015 Port B data Output becomes active from Hi-Z by writing data to port register. RD Hi-Z Data bus 6 pins Port C PC0/PPO016 to PC2/PPO018 PC3/RTO0 to PC7/RTO4 PPO0 or RTO data Port C data Input protection circuit IP (Every bit) Data bus Hi-Z "0" when reset Port C direction 8 pins Port D RD (Port C) Port D data ∗ PD0/KS0 to PD7/KS7 "0" when reset Port D direction IP (Every bit) Hi-Z Data bus RD Standby release Port D standby release data Edge detection ∗ Large current drive transistor 8 pins –7– CXP913040 Pin Port E Circuit format When reset Port E data PE0 to PE7 "0" when reset Port E direction ∗ Hi-Z IP (Every bit) Data bus 8 pins Port F PF0/EC0/INT0 PF1/EC2/INT1 PF3/SI1/INT2 RD ∗ Large current drive transistor Schmitt trigger input IP Interrupt circuit and timer/counter or SIO Data bus Hi-Z 3 pins Port F "0" when reset RD (Port F) PF2/CS1/ NMI/CINT Port F function selection Schmitt trigger input IP RD (Port F) Interrupt circuit Timer/counter or SIO Data bus Hi-Z 1 pin Port F "0" when reset Port F function selection SO1 from SIO MPX Port F data Data bus PF4/SO1 Hi-Z Hi-Z control RD (Port F) 1 pin –8– CXP913040 Pin Port F "0" when reset Port F function selection Circuit format When reset Internal serial clock from SIO PF5/SCK1 Port F data Data bus RD (Port F) MPX Hi-Z Hi-Z control IP 1 pin Port F SIO Schmitt trigger input "0" when reset Port F function selection Timer/counter MPX PF6/T1 PF7/T2 "1" when reset "H" level Port F data Data bus 2 pins RD (Port F) Port G PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 "0" when reset Port G function selection DA gate output or PWM output MPX Port G data Data bus Hi-Z 6 pins RD (Port G) Hi-Z control Port G PG6/RFG0 PG7/RFG1 2 pins Schmitt trigger input IP Servo circuit Data bus RD (Port G) Hi-Z PH0/EXI0 PH1/EXI1 PH2/SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG 8 pins Port H Schmitt trigger input IP Servo circuit Data bus RD (Port H) Note) PH2/SYNC0/PMI and PH3/SYNC1 can select CMOS Schmitt trigger input or TTL Schmitt trigger input with the mask option. Hi-Z –9– CXP913040 Pin CS0 SI0 2 pins Circuit format Schmitt trigger input IP SIO When reset Hi-Z SO0 SO0 from SIO Hi-Z 1 pin SO0 output enable Internal serial clock from SIO SCK0 Hi-Z SCK0 output enable External serial clock to SIO IP 1 pin Schmitt trigger input Port I Port I data PI0/SI2 "0" when reset Port I direction IP (Every bit) Data bus Hi-Z 1 pin Port I "0" when reset RD (Port I) SIO Schmitt trigger input Port I function selection SIO MPX Port I data PI1/SO2 PI2/SCK2 SIO MPX "0" when reset Port I direction IP Hi-Z Data bus 2 pins RD (Port I) SIO (PI2 only) Schmitt trigger input Note) Only PI2 is Schmitt trigger input. – 10 – CXP913040 Pin Port I Port I function selection Circuit format When reset "0" when reset General-purpose prescaler PI3/CS2/PO Port I data "0" when reset Port I direction MPX Hi-Z IP Data bus RD (Port I) 1 pin Port I "0" when reset Port I function selection IP SIO Schmitt trigger input PI4/PCK/OSCI OSCI General-purpose prescaler Oscillation Fig. 1. OSCO PI4/PCK or PI5 IP General-purpose prescaler Data bus RD (Port I) PI5/OSCO Hi-Z Fig. 2. 2 pins Note) The circuit format in Fig. 1 or Fig. 2 can be selected with the mask option. Port I "0" when reset Port I function selection Clock generator PI6/XOUT General-purpose prescaler MPX Hi-Z IP Data bus 1 pin RD (Port I) – 11 – CXP913040 Pin Port I IP Circuit format Input multiplexer A/D converter When reset PI7/AN0 Hi-Z Port I function selection Data bus RD (Port I) 1 pin "0" when reset AN1 to AN3 IP Input multiplexer A/D converter Hi-Z 3 pins Port J Port J data Port J direction "0" when reset IP PJ0/AN4/KS8 to PJ7/AN11/KS15 Data bus Hi-Z RD (Port J) Standby release Port J input selection "0" when reset Input multiplexer A/D converter 8 pins Stop signal EXTAL XTAL EXTAL IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop mode. Oscillation XTAL 2 pins Mask option Pull-up resistor RST OP IP Schmitt trigger input "L" level Emulator (CXP913000 only) 1 pin – 12 – CXP913040 Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage High level output current VIN VOUT IOH Rating –0.3 to +7.0 AVss to +7.0∗1 –0.3 to +0.3 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –5 –50 15 20 130 –20 to +75 –55 to +150 380 Unit V V V V V mA mA mA mA mA °C °C mW (VSS = 0V reference) Remarks High level total output current ∑IOH Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL IOLC ∑IOL Topr Tstg PD Total for all output pins All pins excluding large current output pins Large current output pins∗3 Total for all output pins ∗1 AVDD and VDD must be the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 N-ch transistors of PD and PE output ports are the large current drive transistors. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 13 – CXP913040 Recommended Operating Conditions Item Symbol Min. 2.7 Supply voltage VDD 2.7 2.5 Analog voltage AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr 2.7 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V °C (VSS = 0V reference) Remarks Guaranteed operation range for high-speed mode (1/2 frequency dividing clock) Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) Guaranteed data hold range during stop mode ∗1 ∗2 CMOS Schmitt trigger input∗3 TTL Schmitt trigger input∗4, ∗7 EXTAL∗5 ∗2 ∗2, ∗6 CMOS Schmitt trigger input∗3 TTL Schmitt trigger input∗4, ∗7 EXTAL VDD – 0.4 VDD + 0.3 0 0 0 –0.3 –20 0.3VDD 0.2VDD 0.2VDD 0.8 0.4 +75 ∗1 AVDD and VDD must be the same voltage. ∗2 PC, PD, PE, PI1, PI3 to PI7, PJ for normal input port ∗3 CS0, SI0, SCK0, RST, PF0/EC0/INT0, PF1/EC2/INT1, PF2/CS1/NMI/CINT, PF3/SI1/INT2, PF5/SCK1, PG6/RFG0, PG7/RFG1, PH (PH2 and PH3 when CMOS Schmitt trigger input is selected with the mask option), PI0/SI2, PI2/SCK2. ∗4 PH2 and PH3 (when TTL Schmitt trigger input is selected with the mask option). ∗5 Specified only during external clock input. ∗6 When the supply voltage (VDD) is within the range of 2.7 to 3.6V. ∗7 When the supply voltage (VDD) is within the range of 4.5 to 5.5V. – 14 – CXP913040 DC Characteristics Item Symbol Pin PA to PE, PF6 to PF7, PG0 to PG5, PI0, PI3, PI6, PJ PF4, PF5, PI1, PI2, SO0, SCK0 PA to PC, PF4 to PF7, PG0 to PG5, PI0 to PI3, PI6, PJ, SO0, SCK0, RST∗1 PD, PE Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA (Ta = –20 to +75°C, VSS = 0V reference) Min. 4.0 3.5 2.4 2.0 3.6 2.0 0.4 0.6 0.3 0.5 1.5 1.0 0.5 0.3 –0.5 –0.3 –1.5 –0.9 40 20 –40 –20 –400 –200 ±10 ±10 Typ. Max. Unit V V V V V V V V V V V V µA µA µA µA µA µA µA µA High level output voltage VOH VDD = 2.7V, IOH = –0.15mA VDD = 2.7V, IOH = –0.5mA VDD = 4.5V, IOH = –4.0mA VDD = 3.0V, IOH = –4.0mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 2.7V, IOL = 1.2mA VDD = 2.7V, IOL = 1.6mA VDD = 4.5V, IOL = 12.0mA VDD = 2.7V, IOL = 5.0mA Low level output voltage VOL IIHE EXTAL Input current IILE RST∗2 PA to PJ, AN1 to AN3, CS0, SI0, SO0, SCK0, RST∗2 VDD = 5.5V, VIH = 5.5V VDD = 3.6V, VIH = 3.6V VDD = 5.5V, VIL = 0.4V VDD = 3.6V, VIL = 0.3V VDD = 5.5V, VIL = 0.4V VDD = 3.6V, VIL = 0.3V VDD = 5.5V, VI = 0, 5.5V VDD = 3.6V, VI = 0, 3.6V 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10% 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V IILR I/O leakage current IIZ 40 65 mA IDD∗4 22 40 mA Supply current∗3 IDDS1∗5 VDD, VSS 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10%, Sleep mode 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V, Sleep mode 8 14 mA 4.5 8 10 10 mA µA µA pF IDDS2 Input capacitance Pins other than VDD, VSS, AVDD, AVSS VDD = 5.5V, Stop mode VDD = 3.6V, Stop mode CIN Clock 1MHz 0V for all pins excluding measured pins – 15 – 10 20 CXP913040 ∗1 RST is specified only in evaluation mode. ∗2 In RST, the input current is specified when pull-up resistor is selected; the leakage current is specified when no resistor is selected. ∗3 When all output pins are open. ∗4 When the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (1/2 frequency dividing clock). ∗5 When the clock generator output is not selected at PI6. AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time Symbol fC Pin XTAL, EXTAL EXTAL Fig. 1, Fig. 2 Conditions VDD = 5.0V ± 10% VDD = 3.0V ± 10% (Ta = –20 to +75°C, VSS = 0V reference) Min. 1 1 20 20 200 200 Max. Unit 20 20 MHz MHz ns ns ns ns ns ns 20 20 ms ms tXH, tXL tCR, tCF tEH, tEL tER, tEF VDD = 5.0V ± 10% Fig. 1, Fig. 2 External clock drive VDD = 3.0V ± 10% VDD = 5.0V ± 10% Fig. 1, Fig. 2 External clock drive VDD = 3.0V ± 10% Fig. 3 VDD = 5.0V ± 10% EXTAL PF0/EC0, PF1/EC2 PF0/EC0, PF1/EC2 tsys + 50∗1 VDD = 3.0V ± 10% tsys + 100∗1 VDD = 5.0V ± 10% Fig. 3 VDD = 3.0V ± 10% ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation External clock EXTAL XTAL EXTAL XTAL 74HC04 Fig. 3. Event count clock timing 0.8VDD 0.2VDD PF0/EC0 PF1/EC2 tEH tEF tEL tER – 16 – CXP913040 (2) Serial interface (CH0, CH1, CH2) Item CS ↓ → SCK delay time CS ↑ → SCK float delay time CS ↓ → SO delay time CS ↑ → SO float delay time CS high level width Symbol Pin Conditions (Ta = –20 to +75°C, VSS = 0V reference) Min Max. Unit ns SCK0, Chip select transfer VDD = 5.0V ± 10% tsys + 200 tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 250 tDCSK SCK1, mode SO0, SO2 SCK2 (SCK = output mode) VDD = 3.0V ± 10% Chip select transfer VDD = 5.0V ± 10% tDCSKF SO1, mode tDCSO SO1 SO2 CS0, CS2 SO0, ns (SCK = output mode) VDD = 3.0V ± 10% Chip select transfer mode Chip select transfer mode VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% ns tDCSOF CS1 ns SCK0, VDD = 5.0V ± 10% tsys + 100 tWHCS SCK1 Chip select transfer mode VDD = 3.0V ± 10% tsys + 100 SCK2 VDD = 5.0V ± 10% 2tsys + 200 ns SCK cycle time tKCY Input mode SCK0, SCK1, SCK2 Output mode VDD = 3.0V ± 10% 2tsys + 200 VDD = 5.0V ± 10% VDD = 3.0V ± 10% 16000/fc 16000/fc ns ns SCK high, low level width tKH, tKL SCK0, SCK1, SCK2 Output mode Input mode tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% VDD = 5.0V ± 10% 8000/fc – 50 VDD = 3.0V ± 10% 8000/fc – 75 VDD = 5.0V ± 10% VDD = 3.0V ± 10% 100 100 ns ns SI input setup time (for SCK ↑) tSIK SI0, SI1, SI2 SCK input mode ns SCK output mode VDD = 5.0V ± 10% 200 – tsys VDD = 3.0V ± 10% 200 – tsys ns SI input hold time (for SCK ↑) tKSI SI0, SI1, SI2 SCK input mode SCK output mode tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% tsys + 100 VDD = 3.0V ± 10% tsys + 100 VDD = 5.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% ns ns SCK ↓ → SO delay time tKSO SO0, SO1, SO2 SCK input mode tsys + 100 tsys + 150 50 100 ns SCK output mode VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% 2tsys + 100 VDD = 3.0V ± 10% 2tsys + 125 VDD = 5.0V ± 10% 8000/fc – 50 VDD = 3.0V ± 10% 8000/fc – 75 ns Minimum interval time tINT SCK0, SCK1, SCK2 SCK output mode SCK input mode ns ns – 17 – CXP913040 Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK output mode, SO output delay time is 150pF when VDD = 5.0V ± 10% and 100pF when VDD = 3.0V ± 10%. Fig. 4. Serial interface CH0, CH1, CH2 timing tWHCS 0.8VDD CS0 CS1 CS2 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 SCK1 SCK2 0.2VDD tSIK tKSI 0.8VDD SI0 SI1 SI2 Input data 0.2VDD tDCSO tKSO tDCSOF SO0 SO1 SO2 0.8VDD Output data 0.2VDD tINT 0.8VDD SCK0 SCK1 SCK2 – 18 – CXP913040 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 5.5V, VSS = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage VZT∗1 Ta = 25°C VFT∗2 VDD = AVDD = 5.0V VDD = AVDD = 3.0V VDD = AVDD = 5.0V VDD = AVDD = 3.0V VDD = AVDD = 5.0V VDD = AVDD = 3.0V –10 –10 4935 2955 200tsys 14tsys AVREF AN0 to AN11 Operation mode AVREF IREFS Sleep mode Stop mode VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V 0.9AVDD 0 0.65 0.45 AVDD AVREF 1.2 0.8 10 10 10 5 4975 2985 Symbol Pin Conditions Min. Typ. Max. 8 ±1.5 ±1.5 50 35 5015 3015 Unit Bits LSB mV mV µs µs V V tCONV tSAMP VREF VIAN IREF AVREF current mA µA ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 5. Definition of A/D converter terms FFh FEh Digital conversion value Linearity error 01h 00h VZT Analog input VFT – 19 – CXP913040 (4) Interruption and reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Item Symbol Pin NMI INT0 INT1 INT2 PD0 to PD7 RST Conditions Min. Max. Unit External interruption high, low level width tIH, tIL tRSL 1 µs Reset input low level width 6tsys∗1 µs ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 6. Interruption input timing tIH tIL NMI INT0 INT1 INT2 PD0 to PD7 PJ0 to PJ7 (During standby release input) (Falling edge) 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD – 20 – CXP913040 (5) General-purpose prescaler Item External clock input frequency External clock input pulse width External clock input rise time, fall time Prescaler output delay time (for PCK ↑) Symbol fPCK Pin PCK Conditions (Ta = –20 to +75°C, Vss = 0V reference) Min. Typ. Max. 12 12 33 33 200 200 80 130 60 90 50 100 20 40 130 220 100 150 100 280 40 80 ns ns ns ns ns ns Unit MHz VDD = 5.0V ±10% VDD = 3.0V ± 10% tWH, tWL tR, tF tPLH PCK VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% PCK VDD = 3.0V ± 10% VDD = 5.0V ± 10% External clock input VDD = 3.0V ± 10% PCK VDD = 5.0V ± 10% tR = tF = 6ns VDD = 3.0V ± 10% VDD = 5.0V ± 10% External clock input VDD = 3.0V ± 10% PCK VDD = 5.0V ± 10% tR = tF = 6ns VDD = 3.0V ± 10% PO tPHL tTLH Prescaler output rise time, fall time PO tTHL Note) PO pin load condition: 50pF Fig. 8. General-purpose prescaler timing 1/fPCK tWH tF PCK 0.8VDD 0.5VDD 0.2VDD tWL tPLH tR tPHL 0.8VDD PO 0.5VDD 0.2VDD tTLH tTHL – 21 – CXP913040 (6) Other Item CFG input high, low level width DFG input high, low level width DPG minimum pulse width DPG minimum removal time RFG input high, low level width EXI input high, low level width PMI input high, low level width PMSK minimum pulse width PMSK minimum removal time Symbol Pin CFG Conditions VDD = 5.0V ± 10% VDD = 3.0V ± 10% DFG (Ta = –20 to +75°C, VSS = 0V reference) Min. Typ. Max. Unit ns tCFH, tCFL tDFH, tDFL tDPW tDPR tRFH, tRFL tEIH, tEIL tPIH, tPIL tPMW tPMR tTLH tsys +200 tsys +200 VDD = 5.0V ± 10% 1000/fc +200 VDD = 3.0V ± 10% 1000/fc +200 VDD = 5.0V ± 10% VDD = 3.0V ± 10% 50 50 50 50 ns DPG ns DPG RFG0 RFG1 EXI0 EXI1 PMI VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% When tsys = 2000/fc VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% ns PMSK VDD = 5.0V ± 10% VDD = 3.0V ± 10% PMSK VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 50 100 20 40 100 280 40 80 ns ns ns ns ns XOUT output rise time, fall time tTHL Note) When the XOUT load is 50pF VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% ns tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") – 22 – CXP913040 Fig. 9. Other timing tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD tDPR tDPW tDPR 0.8VDD DPG tRFH tRFL RFG0 RFG1 0.8VDD 0.2VDD tEIH tEIL EXI0 EXI1 0.8VDD 0.2VDD tPIH tPIL 0.8VDD PMI 0.2VDD tPMR tPMW tPMR 0.8VDD PMSK 0.8VDD XOUT 0.2VDD tTLH tTHL – 23 – CXP913040 Appendix Fig. 10. Recommended oscillation circuit General-purpose prescaler clock Mask option Main clock EXTAL XTAL OSCI OSCO C1 C2 C1 C2 Manufacturer Model fc (MHz) 12 Main clock C1 (pF) C2 (pF) General-purpose prescaler clock C1 (pF) 4 C2 (pF) 4 RIVER ELETEC HC-49/U03 CORPORATION 16 20 12 10 10 4 10 10 4 KINSEKI LTD. HC-49/U (-S) 16 20 Note 1) Use the general-purpose prescaler clock at 12MHz or less. Note 2) Crystals and capacitors should be placed near the LSI and wiring should be as short as possible. Mask option table Item EXTAL system operating voltage∗1 Reset pin pull-up resistor PH2 input format PH3 input format PI4/PI5 pin format 2.7 to 5.5V Non-existent CMOS Schmitt trigger CMOS Schmitt trigger Oscillation circuit Selection 4.5 to 5.5V Existent TTL Schmitt trigger TTL Schmitt trigger Input pin ∗1 Select 4.5V to 5.5V when this LSI is used with a supply voltage range of 4.5V to 5.5V. – 24 – CXP913040 Example of Representative Characteristics IDD vs. VDD (fc = 20MHz, Ta = 25°C, Typical) 50 40 30 25 20 15 10 8 6 5 4 3 2 3 4 5 6 1/2 frequency dividing mode 1/4 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode IDD – Supply current [mA] Sleep mode VDD – Supply voltage [V] IDD vs. fC (VDD = 5V, Ta = 25°C, Typical) 40.00 38.00 36.00 34.00 32.00 30.00 28.00 26.00 24.00 22.00 20.00 18.00 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 0 5 10 15 1/2 frequency dividing mode IDD – Supply current [mA] 1/4 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode Sleep mode 20 fc – System clock [MHz] – 25 – CXP913040 Package Outline Unit: mm 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 + 0.08 0.18 – 0.03 25 26 (0.22) 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.8g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 LQFP100-P-1414 – 26 – 0.5 ± 0.2 A (15.0)