CXP921064A

CXP921064A CMOS 16-bit Single Chip Microcomputer Description The CXP921064A is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface, I2C bus interface, timer, real-time pulse generator, clock prescaler, remote control receive circuit, and as well as basic configurations like a 16bit CPU, ROM, RAM, and I/O port. This LSI also provides the sleep/stop functions that enable lower power consumption. 100 pin QFP (Plastic) 100 pin LQFP (Plastic) 104 pin LFLGA (Plastic) Features • An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS — Highly quadratic instruction system, generalpurpose register of eigth 16-bit × 16-bank configuration • Minimum instruction cycle 100ns at 20MHz operation (2.7 to 3.3V) 61µs at 32kMHz operation (2.2 to 3.3V) • Incorporated ROM capacity 256K bytes • Incorporated RAM capacity 10K bytes • Peripheral functions — A/D converter 8-bit 12 analog input, 2 channels successive approximation system, automatic scanning function, (Conversion time: 3.4µs at 20MHz) — Serial interface 128 -byte buffer RAM, 3 channels 8-stage FIFO, 1 channel (supports special mode master/slave) — I2C bus interface 64-byte buffer RAM , 2 channels (supports master/slave and automatic transfer mode) — Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit timer, 3 channels — Real-time pulse generator 5-bit output, 1 channel (2-stage FIFO) — Clock prescaler — Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO • Interruption 30 factors, 30 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP 104-pin plastic LFLGA • Piggy/evaluation chip CXP921000A • FLASH EEPROM incorporated version CXP921F064A Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99707-PS Block Diagram NMI INT0 to INT7 KS0 to KS15 TEX TX EXTAL XTAL RST VDD VSS 8 PORT A 8 16 CS0 SI0 SO0 SCK0 SPC950 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROLLER PORT B 8 SERIAL INTERFACE UNIT (CH0) BUFFER RAM PA0 to PA7 PB0 to PB7 CS1 SI1 SO1 SCK1 2 2 2 3 ROM 256K BYTES RAM 10K BYTES SERIAL INTERFACE UNIT (CH1) BUFFER RAM INTERRUPT CONTROLLER PRESCALER/ TIME-BASE TIMER PORT E SI3 SO3 SCK3 SERIAL INTERFACE UNIT (CH3) FIFO PORT D CS2 SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) BUFFER RAM PORT C 8 PC0 to PC7 8 PD0 to PD7 8 PE0 to PE7 PORT F I2C BUS INTERFACE UNIT (CH1) PORT G TO 8-BIT TIMER (CH1) 16-BIT TIMER (CH1) A/D CONVERTER (CH0) A/D CONVERTER (CH1) REALTIME PULSE GENERATOR RMC REMOCON FIFO 12 AVREF0 AN0 to AN11 AVSS AVREF1 AVDD 12 AN12 to AN23 5 XOUT RTO0 to RTO4 PORT J 16-BIT TIMER (CH2) PORT I TMO 16-BIT TIMER (CH0) PORT H –2– SCL0 SDA0 I2C BUS INTERFACE UNIT (CH0) BUFFER RAM 4 CLOCK PRESCALER 4 PF0 to PF3 PF4 to PF7 SCL1 SDA1 BUFFER RAM 8 PG0 to PG7 EC 8-BIT TIMER/COUNTER (CH0) FIFO 6 2 PH0 to PH5 PH6, PH7 8 PI0 to PI7 8 PJ0 to PJ7 CXP921064A CXP921064A Pin Assignment 1 (Top View) 100-pin QFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PB1/AN21 PB0/AN20 PA2/AN14 PA1/AN13 PA0/AN12 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC PJ1/AN5/KS9 VSS PB2/AN22 PB3/AN23 PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PJ0/AN4/KS8 AVDD AVREF1 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PG7/SCK2 PG6/SO2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PF2/CS0 PF4/SO0 PF5/SCK0 PF7/TMO Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 15, 41, 56 and 90) must be connected to GND. 3. VDD (Pins 44, 53 and 89) must be connected to VDD. –3– PG5/SI2 PE7 PF0 PF3/SI0 PF1/EC PF6/TO RST XTAL EXTAL VDD VSS CXP921064A Pin Assignment 2 (Top View) 100-pin LQFP package PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PJ1/AN5/KS9 PB3/AN23 PB2/AN22 PB1/AN21 PB0/AN20 PA7/AN19 PA6/AN18 PA5/AN17 PA4/AN16 PA3/AN15 PA2/AN14 PA1/AN13 PA0/AN12 PJ0/AN4/KS8 VDD VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AVREF0 AVss AN3 AN2 AN1 PI7/AN0 PI6/NMI PI5/INT7 PI4/INT6 PI3/INT5 PI2/INT4 PI1/INT3 PI0/INT2 PH7/INT1 PH6/INT0 PH5/XOUT PH4/RTO4 PH3/RTO3 PH2/RTO2 PH1/RTO1 PH0/RTO0 Vss TX TEX VDD PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 PC5 PC6 PC7 VSS PD0/KS0 PD1/KS1 PD2/KS2 PD3/KS3 PD4/KS4 PD5/KS5 PD6/KS6 PD7/KS7 PE0 PE1 PE2 PE3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC AVREF1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PG7/SCK2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PF2/CS0 PF4/SO0 PF5/SCK0 PF7/TMO PG5/SI2 VSS PE7 PF0 PF3/SI0 PF1/EC PF6/TO RST XTAL EXTAL VDD Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 13, 39, 54 and 88) must be connected to GND. 3. VDD (Pins 42, 51 and 87) must be connected to VDD. –4– PG6/SO2 PE4 PE5 PE6 AVDD CXP921064A Pin Assignment 3 (Top View) 104-pin LFLGA package 1 A B C D E 3 PB6 5 PC0 2 3 98 PB1 99 PB2 4 96 PA7 97 PB0 100 PB3 5 93 PA4 94 PA5 95 PA6 6 90 PA1 91 PA2 92 PA3 7 88 VSS 87 VDD 89 PA0 8 86 NC 85 PJ7 84 PJ6 9 83 PJ5 82 PJ4 10 80 PJ2 79 PJ1 11 78 PJ0 77 AVDD 12 13 A B 2 PB5 4 PB7 7 PC2 10 PC5 12 PC7 16 PD2 19 PD5 22 PE0 24 PE2 27 PE5 28 PE6 3 1 PB4 6 PC1 9 PC4 14 PD0 17 PD3 20 PD6 25 PE3 81 76 PJ3 AVREF1 74 AVSS 73 AN3 71 AN1 68 PI5 65 PI2 63 PI0 61 PH6 58 PH3 55 PH0 53 TX C D E F G H J K L M N 75 72 AVREF0 AN2 70 PI7 67 PI4 64 PI1 59 PH4 56 PH1 51 VDD 26 PE4 29 PE7 30 PF0 4 31 PF1 32 PF2 33 PF3 5 34 PF4 35 PF5 36 PF6 6 39 VSS 42 VDD 45 PG2 50 PG7 47 PG4 46 PG3 10 49 PG6 48 PG5 11 69 PI6 66 PI3 62 PH7 60 PH5 57 PH2 54 VSS 52 TEX 8 PC3 F 11 PC6 G 13 VSS H J 15 PD1 18 PD4 K 21 PD7 L M N 1 23 PE1 37 41 44 PF7 EXTAL PG1 38 40 43 RST XTAL PG0 7 8 9 2 12 13 Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM incorporated version. 2. Vss (Pins 13, 39, 54 and 88) must be connected to GND. 3. VDD (Pins 42, 51 and 87) must be connected to VDD. –5– CXP921064A Pin Functions Symbol PA0/AN12 to PA7/AN19 PB0/AN20 to PB3/AN23 PB4/SI3 PB5/SO3 PB6/SCK3 PB7/RMC PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PC4 to PC7 I/O Output / Input (Port A) 8-bit output port. (8 pins) Functions Analog input for A/D converter. (12 pins) Output / Input (Port B) 8-bit output port. Output / Output (8 pins) Output / I/O Output / Input Output / Input I/O / I/O I/O / I/O I/O / I/O I/O / I/O I/O Serial data (CH3) input. Serial data (CH3) output. Serial clock (CH3) I/O. Remote control receive circuit input. Data I/O of I2C bus interface (CH0). (Port C) Clock I/O of I2C bus interface (CH0). 8-bit I/O port. I/O can be specified in 1-bit units. Data I/O of I2C bus interface (CH1). Pull-up resistor is present or not Clock I/O of I2C bus interface (CH1). through program in 1-bit units. (8 pins) (Port D) 8-bit I/O port. I/O can be specified in 1-bit units. Can drive 5mA sink current (VDD = 2.7 to 3.3V). (8 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) PD0/KS0 to PD7/KS7 I/O / Input Standby release input function can be specified in 1-bit units. (8 pins) PE0 to PE7 I/O PF0 PF1/EC PF2/CS0 PF3/SI0 PF4/SO0 PF5/SCK0 PF6/TO PF7/TMO Input Input / Input (Port F) 8-bit port. Input / Input Lower 4 bits are for input; Output / Output upper 4 bits are for output. (8 pins) Output / I/O Input / Input Output / Output Output / Output External event input for 8-bit timer/counter. Serial chip select (CH0) input. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH0) I/O. 8-bit timer/counter output. 16-bit timer (CH0) output. –6– CXP921064A Symbol PG0/CS1 PG1/SI1 PG2/SO1 PG3/SCK1 PG4/CS2 PG5/SI2 PG6/SO2 PG7/SCK2 PH0/RTO0 to PH4/RTO4 PH5/XOUT PH6/INT0 to PH7/INT1 PI0/INT2 to PI5/INT7 PI6/NMI PI7/AN0 AN1 to AN3 PJ0/AN4/ KS8 to PJ7/AN11/ KS15 EXTAL XTAL TEX TX RST AVDD AVREF0 AVREF1 AVSS VDD VSS NC Input Input Input Input I/O I/O / Input I/O / Input I/O / Output I/O / I/O I/O / Input I/O / Input I/O / Output I/O / Output Output / Output (Port H) 8-bit port. Output / Output Lower 6 bits are for output; upper 2 bits are for input. (8 pins) Input / Input Input / Input Input / Input Input / Input Input Analog input for A/D converter. (12 pins) Functions Serial chip select (CH1) input. Serial data (CH1) input. Serial data (CH1) output. (Port G) Serial clock (CH1) I/O. 8-bit I/O port. I/O can be specified in 1-bit units. Serial chip select (CH2) input. (8 pins) Serial data (CH2) input. Serial data (CH2) output. Serial clock (CH2) output. Real-time pulse generator output. (5 pins) Clock output for clock prescaler buzzer. External interrupt input. (8 pins) Non-maskable external interrupt input. (Port I) 8-bit input port. (8 pins) I/O / Input / Input Input (Port J) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins) Standby release input function can be specified in 1-bit units. (8 pins) Connects a crystal for main clock oscillation. (When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL.) Connects a crystal for sub clock oscillation. (When the clock is supplied externally, input it to TEX and input an opposite phase clock to TX.) System reset. Active at "L" level. Positive power supply for A/D converter. Reference voltage input for A/D converter (CH0). Reference voltage input for A/D converter (CH1). GND for A/D converter. Positive power supply. (Connect all three VDD pins to positive power supply.) GND (Connect all four Vss pins to GND.) NC. (NC is used for FLASH EEPROM incorporated version.) –7– CXP921064A I/O Circuit Format for Pins Pin Circuit format After a reset PA register "0" after a reset PA0/AN12 to PA7/AN19 Internal data bus PASL register "0" after a reset IP Input protection circuit Hi-Z A/D converter RD Input multiplexer PB register "0" after a reset PB0/AN20 to PB3/AN23 Internal data bus PBSL register "0" after a reset IP Hi-Z A/D converter RD Input multiplexer PB register "0" after a reset PB4/SI3 PB7/RMC Internal data bus PBSL register "0" after a reset IP Hi-Z RD SI3, RMC CMOS Schmitt input –8– CXP921064A Pin Circuit format After a reset SO3 0 MPX 1 PB register PB5/SO3 "0" after a reset Internal data bus RD PBSL register "0" after a reset SO3 output enable Hi-Z SCK3 0 MPX 1 PB register "0" after a reset Internal data bus PB6/SCK3 RD PBSL register IP "0" after a reset SCK3 output enable SCK3 CMOS Schmitt input Hi-Z PULC register "0" after a reset SDA0, SCL0, SDA1, SCL1 PC register Underfined after a reset ∗ 1 MPX 0 PC0/SDA0 PC1/SCL0 PC2/SDA1 PC3/SCL1 PCSL register "0" after a reset PCD register "0" after a reset Internal data bus RD SDA0, SCL0 SDA1, SCL1 IP Hi-Z CMOS Schmitt input ∗ Pull-up transistor approximately 15kΩ (VDD = 2.7 to 3.3V) –9– CXP921064A Pin Circuit format After a reset PULC register "0" after a reset ∗ PC register Underfined after a reset PC4 to PC7 PCD register "0" after a reset IP Hi-Z Internal data bus RD ∗ Pull-up transistor approximately 15kΩ (VDD = 2.7 to 3.3V) PD register Underfined after a reset ∗ IP PD0/KS0 to PD7/KS7 Internal data bus PDD register "0" after a reset Hi-Z RD Standby release ∗ Large current drive 5mA (VDD = 2.7 to 3.3V) PE register Underfined after a reset PE0 to PE7 PED register "0" after a reset IP Hi-Z Internal data bus RD – 10 – CXP921064A Pin Circuit format After a reset PF0 Internal data bus RD IP Hi-Z Internal data bus IP RD PF1/EC EC Hi-Z CMOS Schmitt input Internal data bus IP RD CMOS Schmitt input PF2/CS0 PF3/SI0 PFSL register "0" after a reset CS0, SI0 Hi-Z SO0 PF register Internal data bus "0" after a reset RD PFSL register "0" after a reset SO0 output enable PF register write Reset 1 MPX 0 PF4/SO0 Hi-Z S R Q SCK0 PF register Internal data bus "0" after a reset RD 1 MPX 0 PF5/SCK0 PFSL register "0" after a reset SCK0 output enable PF register write Reset S R CMOS Schmitt input Q SCK0 IP Hi-Z – 11 – CXP921064A Pin Circuit format After a reset PF register write Reset TO, TMO S R Q ∗ PF6/TO PF7/TMO Internal data bus PF register "0" after a reset RD PFSL register "0" after a reset 1 MPX 0 "H" level ("H" level at ON resistance of pullup transistor during a reset.) ∗ Pull-up transistor approximately 150kΩ (VDD = 2.7 to 3.3V) PG register Underfined after a reset PGD register PG0/CS1 PG1/SI1 PG4/CS2 PG5/SI2 IP "0" after a reset Hi-Z Internal data bus RD PGSL register "0" after a reset CS1, SI1 CS2, SI2 CMOS Schmitt input SO1, SCK1 SO2, SCK2 PG register Underfined after a reset 1 MPX 0 PGSL register PG2/SO1 PG3/SCK1 PG6/SO2 PG7/SCK2 "0" after a reset Hi-Z PGD register "0" after a reset Internal data bus RD SCK1 CMOS Schmitt input (PG3 only) SO1, SCK1 output enable SO2, SCK2 IP – 12 – CXP921064A Pin Circuit format After a reset RTO0 to RTO4 PH0/RTO0 to PH4/RTO4 Internal data bus PH register Underfined after a reset Hi-Z RD PH register write Reset S R Q XOUT PH register Underfined after a reset Internal data bus 1 MPX 0 PH5/XOUT RD PHSL register "0" after a reset PH register write Reset S R Q Hi-Z PH6/INT0 to PH7/INT1 Internal data bus RD Interrupt circuit CMOS Schmitt input IP Hi-Z PI0/INT2 to PI5/INT7 Internal data bus RD Interrupt circuit CMOS Schmitt input IP Hi-Z – 13 – CXP921064A Pin PISL register "0" after a reset Circuit format After a reset PI6/NMI Interrupt circuit (NMI) CMOS Schmitt input RD IP Hi-Z Internal data bus PISL register "0" after a reset PI7/AN0 Internal data bus RD A/D converter Input multiplexer IP Hi-Z AN1 to AN3 A/D converter Input multiplexer IP Hi-Z PJ register Underfined after a reset PJD register "0" after a reset PJ0/AN4/ KS8 to PJ7/AN11/ KS15 Internal data bus RD Standby release IP PJSL register "0" after a reset A/D converter Input multiplexer Hi-Z – 14 – CXP921064A Pin Circuit format After a reset EXTAL IP Timing generator EXTAL XTAL Oscillation stop control • Diagram shows circuit configuration during oscillation. • Feedback registor is removed during stop mode, and XTAL is driven at "H" level. Oscillation XTAL Oscillation stop control Timing generator, clock prescaler TEX IP TEX TX • TX is driver at Hi-Z during stop. TX IP Oscillation Mask option ∗ OP RST IP CMOS Schmitt input ∗ Pull-up transistor approximately 30kΩ (VDD = 2.7 to 3.3V) "L" level (during a reset) – 15 – CXP921064A Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVREF AVSS Input voltage Output voltage High level output current High level total output current VIN VOUT IOH ∑IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature ∑IOL Topr Tstg 20 130 –20 to +75 –55 to +150 600 Allowable power dissipation PD 380 500 mA mA °C °C mW mW mW QFP-100P-L01 LQFP-100P-L01 LFLGA-104P-02 Rating –0.3 to +4.6 AVSS to +4.6∗1 AVSS to +4.6∗1 –0.3 to +0.3 –0.3 to +4.6∗2 –0.3 to +4.6∗2 –5 –50 15 Unit V V V V V V mA mA mA (VSS = 0V reference) Remarks Output (value per pin) Total for all output pins All pins excluding large current output pins (value per pin) Large current output pins∗3 (value per pin) Total for all output pins ∗1 AVDD and AVREF must be the same voltage with VDD. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 The large current drive transistor is N-ch transistor of PD. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 16 – CXP921064A Recommended Operating Conditions Item Symbol Min. 2.7 VDD Supply voltage AVDD AVREF VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 2.2 2.2 2.0 2.7 2.7 0.7VDD 0.8VDD 0.7VDD 0 0 –0.3 –20 Max. 3.3 3.3 3.3 3.3 3.3 3.3 VDD VDD VDD+0.3 0.2VDD 0.2VDD 0.3VDD +75 Unit V V V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed operation range with TEX clock Guaranteed operation range for clock mode Guaranteed data hold range during stop mode ∗1 ∗1 ∗2 CMOS Schmitt input∗3 EXTAL, TEX ∗2 CMOS Schmitt input∗3 EXTAL, TEX ∗1 AVDD and AVREF must be the same voltage with VDD. ∗2 PC4 to PC7, PD, PE, PF0, PG2, PG6, PI7, PJ for normal input port. ∗3 PB4, PB6, PB7, PC0 to PC3, PF1 to PF3, PF5, PG0, PG1, PG3 to PG5, PG7, PH6, PH7, PI0 to PI6, RST. – 17 – CXP921064A Electrical Characteristics DC Characteristics Item High level output voltage Symbol Pins PA, PB, PD, PE, PF4 to PF7, PG, PH0 to PH5, PJ PC PA, PB, PC4 to PC7, PE, PF4 to PF7, PG, PH0 to PH5, PJ VOL PC0 to PC3 (SCL0, SCL1, SDA0, SDA1) PD IIHE IILE Input current IILR IIL EXTAL RST∗1 PC∗2 VDD = 2.7V, VIH = 2.4V PA, PB, PD to PG, PH6, PH7, PI, PJ, AN1 to AN3, TEX, RST∗1 Conditions VDD = 2.7V, IOH = –0.15mA VDD = 2.7V, IOH = –0.5mA VDD = 2.7V, IOH = –0.05mA VDD = 2.7V, IOL = 1.2mA VDD = 2.7V, IOL = 1.6mA VDD = 2.7V, IOL = 2.0mA VDD = 2.7V, IOL = 3.0mA VDD = 2.7V, IOL = 5.0mA VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL = 0.3V VDD = 3.3V, VIL = 0.3V (Topr = –20 to +75°C, Vss = 0V reference) Min. 2.4 2.0 1.3 0.3 0.5 0.3 0.5 1.0 0.3 –0.3 –0.9 20 –20 –250 –250 –1.0 Typ. Max. Unit V V V V VOH Low level output voltage V V V V µA µA µA µA µA I/O leakage IIZ current VDD = 3.3V, VI = 0, 3.3V ±10 µA Open drain output leakage ILOH current (N-ch Tr. off state) IDD1∗4 PC∗2 VDD = 3.3V, VIH = 3.3V 10 µA VDD = 3.0 ± 0.3V, 20MHz crystal oscillation, A/D off state (C1 = C2 = 10pF) VDD = 3.0 ± 0.3V, 32kHz crystal oscillation, 20MHz oscillation stop, A/D off state (C1 = C2 = 47pF) VDD = 3.0 ± 0.3V, 20MHz crystal oscillation, A/D off state (C1 = C2 = 10pF), sleep mode VDD = 3.0 ± 0.3V, 32kHz crystal oscillation, 20MHz oscillation stop, A/D off state (C1 = C2 = 47pF), sleep mode VDD = 3.0V, 32kHz crystal oscillation, 20MHz oscillation stop (C1 = C2 = 47pF), clock mode VDD = 3.0V, stop mode – 18 – 12 20 mA IDD2 25 50 µA IDDS1∗4 Supply current∗3 IDDS2 VDD, VSS 5 10 mA 10 25 µA IDDS3 IDDS4 5 15 10 µA µA CXP921064A Item Symbol Pins PA, PB0 to PB4, PB6, PB7, PC to PE, PF0 to PF3, PF5, PG, PH6, PH7, PI, PJ, AN1 to AN3, EXTAL, TEX, RST Conditions Min. Typ. Max. Unit Input CIN capacitance Clock 1MHz 0V for all pins excluding measured pins 10 20 pF ∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗2 PC specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗3 When all output pins are open. ∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (2 frequency dividing clock). – 19 – CXP921064A AC Characteristics (1) Clock timing Item Main clock base oscillation frequency Main clock base oscillation input pulse width Main clock base oscillation input rise time, fall time Sub clock base oscillation frequency Sub clock base oscillation input pulse width Sub clock base oscillation input rise time, fall time Symbol fEX Pins EXTAL, XTAL EXTAL Fig.1 Fig.1, Fig.2 External clock drive Fig.1, Fig.2 External clock drive Fig.1 Fig.1, Fig.2 External clock drive Fig.1, Fig.2 External clock drive (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions VDD = 3.0 ± 0.3V VDD = 3.0 ± 0.3V Min. 15 20 Typ. 20 Max. 20.5 Unit MHz ns tXH tXL tXR tXF fTEX EXTAL TEX, TX TEX VDD = 3.0 ± 0.3V 14 ns VDD = 2.2 to 3.3V 32.735 32.768 33.096 kHz VDD = 3.3V VDD = 2.2V VDD = 3.3V VDD = 2.2V 15.3 15.3 200 200 µs µs ns ns tTH tTL tTR tTF TEX Note) tsys indicates the four values below according to the upper two bits (PCK1,PCK0) of the clock control register (CLC: 0002FEh) during main mode and tsys = 2/fTEX = 61.04µs during sub mode. tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10), 16/fEX (PCK1, PCK0 = 11) 1/fc EXTAL 0.7VDD 0.3VDD tXH tXF 1/fTEX tXL tXR TEX 0.7VDD 0.3VDD tTH tTF tTL tTR Fig.1. Clock timing Oscillator connection example of main oscillation circuit Oscillator connection example of sub oscillation circuit Connection example of external clock (TEX) EXTAL (TX) XTAL EXTAL XTAL TEX TX 74HC04 Fig.2. Oscillator connection and clock applied conditions – 20 – CXP921064A (2) Event count input Item Event count input clock pulse width Symbol Pins EC (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Fig.3 Min. Max. Unit ns tEH, tEL tsys + 100 0.8VDD EC 0.2VDD tEH tEL Fig.3. Event count input timing (3) Interruption and reset input Item Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Min. Max. Unit ns External interruption high, low level width tIH, tIL Main mode Sub mode NMI INT0 to INT7 Sleep mode KS0 to KS15 Clock mode Stop mode φ Noise filter INT4 to INT7 selected PS4 PS6 tsys + 100 1 2tsys + 100 32/fEX + 100 128/fEX + 100 3tsys + 200 µs ns Reset input low level width tRST RST Fig.5 ns tIH 0.8VDD NMI INT0 to INT7 KS0 to KS15 tIL 0.2VDD Fig.4. Interruption input timing tRST RST 0.2VDD Fig.5. Reset input timing – 21 – CXP921064A (4) A/D converter characteristics (Topr = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 3.3V, Vss = AVss = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage VDD = AVDD = AVREF = 3.0V Symbol Pins Conditions Min. Typ. Max. 8 ±1 ±3 34tsys 9tsys AVREF AN0 to AN23 Main mode Sub mode Clock mode Stop mode during ADC off state VDD = AVDD = AVREF 2.7 0 1.1 3.3 AVREF 1.5 Unit Bits LSB LSB µs µs V V mA tCONV tSAMP VREF VIAN IREF AVREF current IREFS AVREF0 AVREF1 10 µA ∗ When Bit 14 (ADOFF) of A/D control status register (ADCS0: 00013Ch,ADCS1: 00014Ch) is specified to "1". Note) AVDD and AVREF must be the same voltage with VDD. FFh FEh Digital conversion value (100h) FFh FEh Digital conversion value Linearity error Absolute error 01h 00h Absolute error Analog input AVREF 01h 00h VZT∗1 Analog input VFT∗2 ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. Fig.6. Definition of A/D converter terms – 22 – CXP921064A (5) Serial transfer (CH0, CH1, CH2) Item CS ↓ → SCK delay time CS ↑ → SCK float delay time CS ↓ → SO delay time CS ↑ → SO float delay time Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Min. Max. 1.5tsys + 200 Unit ns tDCSK SCK0 External start transfer mode SCK1 (SCK = output mode) SCK2 SCK0 tDCSKF SCK1 External start transfer mode (SCK = output mode) SCK2 SO0 SO1 SO2 CS0 External start transfer mode 1.5tsys + 200 ns tDCSO External start transfer mode 1.5tsys + 200 ns tDCSOF CS1 CS2 1.5tsys + 200 ns CS high level width tWHCS CS0 CS1 CS2 External start transfer mode tsys + 100 2tsys + 200 16/fEX ns ns ns ns ns ns ns ns ns SCK cycle time tKCY tKH tKL tSIK SCK0 Input mode SCK1 SCK2 Output mode SCK0 Input mode SCK1 SCK2 Output mode SI0 SI1 SI2 SI0 SI1 SI2 SO0 SO1 SO2 SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK high, low pulse width SI input data setup time (for SCK ↑) SI input data hold time (for SCK ↑) SCK ↓ → SO delay time tsys + 100 8/fEX – 100 100 200 – tsys tKSI tsys + 100 tsys + 100 tsys + 150 100 3tsys + 100 8/fEX – 100 tKSO ns ns ns ns Minimum interval time tINT SCK0 SCK input mode SCK1 SCK2 SCK output mode Note) The load condition for the SCK output mode and SO output delay time is 100pF. – 23 – CXP921064A tWHCS CS0 CS1 CS2 0.2VDD 0.8VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 SCK1 SCK2 0.2VDD tSIK tKSI 0.8VDD SI0 SI1 SI2 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 SO1 SO2 Output data 0.2VDD tINT SCK0 SCK1 SCK2 0.8VDD Fig.7. Serial transfer CH0, CH1, CH2 timing – 24 – CXP921064A (6) Serial transfer (CH3) [SIO mode] Item SCK cycle time SCK high, low pulse width SI input data setup time (for SCK ↑) SI input data hold time (for SCK ↑) SCK ↓ → SO delay time Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Input mode Min. 2tsys + 200 16/fEX Max. Unit ns ns ns ns ns ns ns ns tKCY SCK3 Output mode Input mode Output mode SCK input mode tKH tKL tSIK SI3 tsys + 100 8/fEX – 100 100 200 SCK output mode SCK input mode SCK output mode tKSI tKSO SO3 tsys + 100 200 SCK input mode SCK output mode tsys + 150 100 ns ns Note) The load condition for the SCK output mode and SO output delay time is 100pF. tKCY tKL tKH SCK3 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI3 Input data 0.2VDD tKSO 0.8VDD SO3 0.2VDD Output data Fig.8. Serial transfer CH3 timing (SIO mode) – 25 – CXP921064A (7) Serial transfer (CH3) [Special mode] Item SO cycle time∗ SI input setup time SI input hold time Input start bit high level width SI → SO delay time Symbol Pins SO3 SI3 SI3 SI3 SI3 (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Min. Typ. Max. Unit 104 fEX = 20MHZ 2 2 1 Communication slave mode 1 µs tLCY tLSU tLHD tLSBH tLIO SO3 ∗ When lower 2 bits (SCK1, SCK0) of serial mode register (SIOM3: 0001A4h) is specified to "00". Note) The load condition for the SO output delay time is 100pF. tLCY tLCY SO3 Start bit Output data bit 0.5VDD tLCY/2 tLSU tLHD 0.8VDD SI3 Input data bit 0.2VDD Fig.9. Serial transfer CH3 timing (Special mode) tLSBH 0.8VDD SI3 tLSU tLCY/2 tLHD tLCY tLIO tLSU tLHD Input data bit 0.2VDD tLCY tLCY SO3 0.5VDD Output data bit Fig.10. Serial transfer CH3 timing (Special mode) – 26 – CXP921064A (8) I2C bus (CH0, CH1) Item SCK clock frequency Bus free time between stop and start conditions Hold time under (resend) start condition Hold time in SCL clock low state Hold time in SCL clock high state Setup time under (resend) start condition Data hold time Data setup time SCL, SDA signal output rise time SCL, SDA signal output fall time Setup time under stop condition Symbol Pins SCL0 SCL1 SDA0 SDA1 (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Standard mode Min. Max. 100 High-speed mode Min. 0 1.3 0.6 1.3 0.6 0.6 0 100 1000 300 4.0 20 + α∗ 20 + α∗ 0.6 300 300 0.9 Max. 400 kHz µs µs µs µs µs µs ns ns ns µs Unit tSCL tBUF tHD;STA tLow tHigh tSU;STA tHD;DAT tSU;DAT tRd tRc tFd tFc tSU;STO 0 4.7 4.0 4.7 4.0 4.7 0 250 SDA0, SDA1 SCL0, SCL1 SCL0 SCL1 SCL0 SCL1 SDA0, SDA1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1 ∗ Due to the total capacitance of the bus. tBUF SDA0 SDA1 tSU;DAT tHD;STA tRd tFd tSCL tRc tLow tFc SCL0 SCL1 tHD;STA tHD;DAT tHigh tSU;STA tSU;STO Fig.11. I2C bus timing – 27 – CXP921064A (9) Remote control reception Item Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference) Conditions Min. Max. Unit PS5 selected 128/fEX + 100 PS7 selected 512/fEX + 100 Remote control receive high, low level width Main mode tRMC RMC PS9 selected 2048/fEX + 100 32k selected 4/fTEX + 100 8/fTEX + 100 ns Sub mode 0.8VDD RMC 0.2VDD tRMC tRMC Fig.12. Remote control signal input timing – 28 – CXP921064A Appendix (i) Main oscillation circuit (ii) Main oscillation circuit (iii) Sub oscillation circuit EXTAL XTAL Rd EXTAL XTAL Rd TEX Rf C1 TX Rd C2 C1 C2 C1 C2 Fig.13. Recommended oscillation circuit Rd (Ω) Circuit example 0 0 0 0 0 220 1.0k 470 390 (i) CL = 12pF (i) CL = 10pF (ii) (i) Manufacturer Model CSA12.0MG CSA16.00MXZ040 fc (MHz) 12.0 16.0 20.00 12.0 16.0 12.00 12.0 C1 (pF) 30 15 10 30 15 10 12 12 12 C2 (pF) 30 15 10 30 15 10 12 12 12 Remarks MURATA MFG CO., LTD. CSA20.00MXZ040 CST12.0MTW∗ CST16.00MXW0C3∗ RIVER ELETEC HC-49/U03 CO., LTD. KINSEKI LTD. HC-49/U-S CCR12.0MSC5∗ CCR16.0MSC6∗ CCR20.0MSC6∗ VTC-200 SP-T 16.0 20.0 12.0 16.0 20.0 32.768kHZ 20 (±20%) 20 (±20%) 10 (±20%) 10 (±20%) 10 (±20%) 10 (±20%) 20 18 150k (iii) Rf = 10MΩ CL = 12.5pF 0 (ii) TDK Corporation Seiko Instruments Inc. ∗ Indicates types with on-chip grounding capacitor (C1, C2). CCR∗∗∗: Surface mounted type ceramic oscillator. CL : Load capacitor Mask option table Item Reset pin pull-up resistor Non-existent Content Existent – 29 – CXP921064A Notes on PF7 Usage FLASH EEPROM incorporated PF7 is also used as flash mode setting function. Note the followings: 1. "H" is output to PF7 during a reset. That is driven at comparatively high impedance (approximately 150 kΩ), and take care that VOH should not fall under 0.7 VDD by the partial pressure with external circuit load impedance. 2. When using software reset functions, PF7 may not rise enough during a reset. Switching PF7 to "H" output prior to software reset execution or connecting pull-up resistor is recommended. RST Normal operation PF7 Flash mode Keep PF7 above 0.7 VDD during this period. Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM incorporated type is used, above countermeasure should be performed. – 30 – CXP921064A Characteristics Curve (fEX = 20MHz, Topr = 25°C, Typical) 20 18 16 IDD – Supply current [mA] IDD – Supply current [mA] 14 12 10 8 6 4 2 2.1 2.4 8 frequency dividing mode 16 frequency dividing mode 4 frequency dividing mode 2 frequency dividing mode IDD vs. VDD (fEX = 20MHz, Topr = 25°C, Typical) 20 18 16 14 12 10 8 6 4 2 0 2.1 2.4 2.7 3 Sleep mode (2 frequency division) Sleep mode (4 frequency division) Sleep mode (8 frequency division) Sleep mode (16 frequency division) 3.3 3.6 3.9 IDD vs. VDD 3 3.3 3.6 2.7 VDD – Supply voltage [V] 3.9 VDD – Supply voltage [V] (fTEX = 32kHz, Topr = 25°C, Typical) 30 32kHz mode (instruction execution) IDD – Supply current [mA] 20 18 16 14 12 10 8 6 4 2 0 2.1 2.4 3 3.3 3.6 2.7 VDD – Supply voltage [V] 3.9 0 IDD vs. VDD (VDD = 3V, Topr = 25°C, Typical) IDD vs. fEX 25 IDD – Supply current [µA] 20 2 frequency dividing mode 15 32kHz sleep mode 10 32kHz clock mode 5 4 frequency dividing mode 8 frequency dividing mode 16 frequency dividing mode 0 5 10 15 20 25 fEX – Main clock base oscillation frequency [MHz] (VDD = 3V, Topr = 25°C, Typical) 20 18 16 IDD – Supply current [mA] 14 12 10 8 6 4 2 0 Sleep mode (2 frequency division) Sleep mode (4 frequency division) Sleep mode (8 frequency division) Sleep mode (16 frequency division) 15 20 25 5 10 0 fEX– Main clock base oscillation frequency [MHz] IDD vs. fEX – 31 – CXP921064A Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 80 51 + 0.1 0.15 – 0.05 81 50 + 0.4 14.0 – 0.1 17.9 ± 0.4 15.8 ± 0.4 A 100 31 1 0.65 + 0.15 0.3 – 0.1 30 0.13 M + 0.35 2.75 – 0.15 + 0.2 0.1 – 0.05 0.15 DETAIL A 0.8 ± 0.2 0° to 10° (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 75 76 14.0 ± 0.1 51 50 100 1 0.5 + 0.08 0.18 – 0.03 25 26 (0.22) 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.8g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 LQFP100-P-1414 – 32 – 0.5 ± 0.2 A (15.0) CXP921064A Package Outline Unit: mm 104PIN LFLGA 0.15 S A 12.0 1.4MAX 0.01 PIN 1 INDEX 12.0 x4 0.20 S 0.15 S B 0.20 S 0.8 N M L K J H G F E D C B A DETAIL X A 103 – φ0.40 ± 0.05 φ0.08 M S A B B 1 2 3 4 5 6 7 8 9 101 11213 0.4 1.6 1.2 1.2 0.8 PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.4g SONY CODE EIAJ CODE JEDEC CODE LFLGA-104P-02 LFLGA104-P-1212 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS – 33 – 0.10 S X 1.6 0.4