CXP922000

CXP922000 CMOS 16-bit Single Chip Microcomputer evaluation type For the availability of this product, please contact the sales office. Description The CXP922000 is a CMOS 16-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP922032. 100 pin PQFP (Ceramic) Piggy/ Features • An efficient instruction set as a controller ( QFP supported ) – Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C Ianguage and RTOS – Highly quadratic instruction system, general-purpose register of eight 16-bit × 16-bank configuration • Minimum instruction cycle time 100ns at 20MHz operation (3.0 to 5.5V) 167ns at 12MHz operation (2.7 to 5.5V) • Incorporated EPROM CXP27V1000K • Incorporated RAM capacity 7680 bytes • Peripheral functions – A/D converter 8-bit 8 analog input, successive approximation system (Conversion time: 12.4µs at 20MHz) – Serial interface Asynchronous serial interface (Simple UART) 128-byte buffer RAM, 3 channels – Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels – Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO – PWM output circuit 14-bit, 1 channel • Interruption 24 factors, 24 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin ceramic PQFP • Mask ROM CXP922032 • One time PROM incorporated type CXP922P032 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98Z32B9X-PS CXP922000 Pin Assignment in Piggyback Mode PJ6/KS6 PJ5/KS5 PJ4/KS4 PJ3/KS3 PJ2/KS2 PJ1/KS1 PJ0/KS0 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Vss PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A11 A12 D7 D6 D5 D4 D3 D2 D1 D0 Vss A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD CE NC D15 D14 D13 D12 D11 D10 D9 D8 Vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI7/RMC PI6/CINT PI5/EC1 PI4/EC0 PI3 PI2 PI1/RxD PI0/TxD PH7/SCK2 PH6/SO2 PH5/SI2 PH4/CS2 PH3/SCK1 PH2/SO1 PH1/SI1 PH0/CS1 Vss SCK0 SO0 SI0 CS0 PG7 PG6 PG5 PG4 AVDD AVREF AVSS PG3/AN7 PG2/AN6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC AN0 AN1 AN2 AN3 PG0/AN4 PF7/TO1/PWM PF3/INT3 PF1/INT1 Note) 1. Do not make any connections to NC (Pin 88 ). 2. Vss (Pins 15, 41, 64 and 90) are connected to GND. 3. VDD (Pins 44 and 89) are both connected to VDD. 4. A19 to A23 are always high level output. –2– PF0/INT0 PF2/INT2 PF4/INT4 PG1/AN5 PF6/TO0 PF5/NMI EXTAL XTAL RST PE7 VDD Vss CXP922000 Pin Assignment in Evaluator Mode PJ6/KS6 PJ5/KS5 PJ4/KS4 PJ3/KS3 PJ2/KS2 PJ1/KS1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Vss PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD AD11 AD12 I/T MON ERST C1 C2 QS0 QS1 QS2 Vss A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 Vss 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 VDD E/P ST0 ST1 ST2 ST3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 PI7/RMC PI6/CINT PI5/EC1 PI4/EC0 PI3 PI2 PI1/RxD PI0/TxD PH7/SCK2 PH6/SO2 PH5/SI2 PH4/CS2 PH3/SCK1 PH2/SO1 PH1/SI1 PH0/CS1 Vss SCK0 SO0 SI0 CS0 PG7 PG6 PG5 PG4 AVDD AVREF AVSS PG3/AN7 PG2/AN6 WTACK 65 JRQH JRQL ENMI MS Vss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AN0 AN1 AN2 AN3 PG0/AN4 PF7/TO1/PWM PF3/INT3 PF1/INT1 Note) 1. Do not make any connections to NC (Pin 88 ). 2. Vss (Pins 15, 41, 64 and 90) are connected to GND. 3. VDD (Pins 44 and 89) are both connected to VDD. –3– PF0/INT0 PF2/INT2 PF4/INT4 PG1/AN5 PF6/TO0 PF5/NMI EXTAL XTAL RST PE7 VDD Vss PJ0/KS0 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD Vss NC CXP922000 EPROM Read Timing (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V) Item Address → data Input delay time Address → data hold time Symbol Pins A0 to A23 D0 to D15 A0 to A23 D0 to D15 0 Min. Max. 100∗1 50∗2 Unit ns ns tACC tIH ∗1 At 12MHz operation (VDD = 3.0 to 5.5V) ∗2 At 12MHz operation (VDD = 2.7 to 5.5V), at 20MHz operation (VDD = 3.0 to 5.5V) 0.8VDD A0 to A23 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Product List Products Optional item Mask ROM CXP922032 Package ROM capacity Reset pin pull-up resistor 100-pin plastic QFP 128K bytes Existent/Non-existent Piggy/evaluation chip CXP922000-U01Q 100-pin ceramic PQFP ( QFP supported ) EPROM 128K bytes Existent –4– CXP922000 Switching of Piggyback Mode and Evaluator Mode Piggyback mode can be used by setting two LCC-type EPROM (for upper bytes, for lower byte) and connecting to the connector of top of the chip. Evaluator mode can be used by connecting in-circuit emulator CPU probe to the connector of top of the chip. Piggyback mode Pin 1 marking 0 1 For lower bytes For upper bytes EPROM adaptor Chip LCC-type PROM Evaluator mode CPU probe Chip –5– CXP922000 Package Outline Unit: mm 100PIN PQFP(CERAMIC) 24.7 ± 0.5 22.3 ± 0.25 80 81 51 50 18.0 1.5 ± 0.05 18.7 ± 0.5 16.3 ± 0.2 3.2 ± 0.2 31 1 0.8 ± 0.1 30 INDEX INDEX 3.57 ± 0.36 0.5 ± 0.25 + 0.05 0.15 – 0.02 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L04 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 4.9g –6– 8.6 MAX 0.3 ± 0.08 100 13.9 0.65 ± 0.05