CXP922P032

CXP922P032 CMOS 16-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP922P032 is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer, remote control receive circuit, PWM output circuit, and as well as basic configurations like a 16-bit CPU, PROM, RAM, and I/O port. This LSI also provides the sleep/stop functions that enable lower power consumption. The CXP922P032 is the PROM-incorporated version of the CXP922032 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic) Features • An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions • Instruction sets for C language and RTOS — Highly quadratic instruction system, general-purpose register of eight 16-bit × 16-bank configuration • Minimum instruction cycle 100ns/20MHz operation (3.0 to 5.5V) 167ns/12MHz operation (2.7 to 5.5V) • Incorporated PROM capacity 128K bytes • Incorporated RAM capacity 7680 bytes • Peripheral functions — A/D converter 8-bit 8 analog input, successive approximation system (Conversion time: 12.4µs at 20MHz) — Serial interface Asynchronous serial interface (Simple UART) 128-byte buffer RAM,3 channels — Timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels — Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO — PWM output circuit 14-bit, 1 channel • Interruption 24 factors, 24 vectors, multi-interruption and priority selection possible • Standby mode Sleep/stop • Package 100-pin plastic QFP • Piggy/evaluation chip CXP922000 • Mask ROM CXP922032 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99937-PS Block Diagram KS0 to KS6 NMI AVSS AVREF AVDD INT0 to INT4 EXTAL XTAL RST VDD VSS VPP 5 PORT A 8 7 PA0 to PA7 AN0 to AN7 2 SPC950 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROLLER 8 A/D CONVERTER RxD TxD UART 8 PB0 to PB7 RMC REMOCON FIFO PORT B PWM 14-BIT PWM GENERATOR SERIAL INTERFACE UNIT (CH0) PROM 128K BYTES RAM 7680 BYTES BUFFER RAM PORT C 8 PC0 to PC7 PORT E SERIAL INTERFACE UNIT (CH1) BUFFER RAM INTERRUPT CONTROLLER PORT D 8 PD0 to PD7 CS0 SI0 SO0 SCK0 CS1 SI1 SO1 SCK1 CS2 SI2 SO2 SCK2 EC0 2 4 PRESCALER/ TIME-BASE TIMER 8-BIT TIMER/COUNTER (CH0) 4CH 16-BIT TIMER PORT G TO0 8-BIT TIMER (CH1) PORT F CINT EC1 TO1 16-BIT CAPTURE TIMER/COUNTER (CH4) PORT H PORT I PORT J –2– 8 PE0 to PE7 SERIAL INTERFACE UNIT (CH2) BUFFER RAM 6 2 PF0 to PF5 PF6, PF7 8 PG0 to PG7 8 PH0 to PH7 8 PI0 to PI7 7 PJ0 to PJ6 CXP922P032 CXP922P032 Pin Assignment (Top View) 100-pin QFP package PJ6/KS6 PJ5/KS5 PJ4/KS4 PJ3/KS3 PJ2/KS2 PJ1/KS1 PJ0/KS0 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VPP PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI7/RMC PI6/CINT PI5/EC1 PI4/EC0 PI3 PI2 PI1/RxD PI0/TxD PH7/SCK2 PH6/SO2 PH5/SI2 PH4/CS2 PH3/SCK1 PH2/SO1 PH1/SI1 PH0/CS1 VSS SCK0 SO0 SI0 CS0 PG7 PG6 PG5 PG4 AVDD AVREF AVSS PG3/AN7 PG2/AN6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS VDD PG0/AN4 PF0/INT0 PF1/INT1 PF2/INT2 PF3/INT3 PF4/INT4 Notes) 1. Do not make any connections to VPP (Pin 88). 2. VSS (Pins 15, 41, 64 and 90) must be connected to GND. 3. VDD (Pins 44 and 89) must be connected to VDD. –3– PF7/TO1/PWM PG1/AN5 PE7 PF5/NMI AN0 AN1 AN2 XTAL PF6/TO0 EXTAL RST AN3 CXP922P032 Pin Functions Symbol I/O Functions (Port A) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) (Port B) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) (Port C) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) (Port D) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. Can drive 12mA sink current (VDD = 4.5 to 5.5V). (8 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. Can drive 12mA sink current (VDD = 4.5 to 5.5V). (8 pins) External interrupt inputs. (4 pins) Non-maskable interrupt input. 8-bit timer/counter output. 16-bit capture timer/ counter output. 14-bit PWM output. PA0 to PA7 I/O PB0 to PB7 I/O PC0 to PC7 I/O PD0 to PD7 I/O PE0 to PE7 I/O PF0/INT0 to PF4/INT4 PF5/NMI PF6/TO0 PF7/TO1/ PWM AN0 to AN3 PG0/AN4 to PG3/AN7 PG4 to PG7 CS0 SI0 SO0 SCK0 Input / Input (Port F) 8-bit port. Input / Input Lower 6 bits are for input; Output / Output upper 2 bits are for output. Output / Output / (6 pins) Output Input Analog input for A/D converter. (4 pins) (Port G) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) Serial chip select (CH0) input. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH0) I/O. –4– Analog input for A/D converter. (4 pins) I/O / Input I/O Input Input Output I/O CXP922P032 Symbol PH0/CS1 PH1/SI1 PH2/SO1 PH3/SCK1 PH4/CS2 PH5/SI2 PH6/SO2 PH7/SCK2 PI0/TxD PI1/RxD PI2 to PI3 PI4/EC0 PI5/EC1 PI6/CINT PI7/RMC I/O I/O / Input I/O / Input I/O / Output I/O / I/O I/O / Input I/O / Input I/O / Output I/O / I/O I/O / Output I/O / Input I/O I/O / Input I/O / Input I/O / Input I/O / Input (Port I) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) (Port H) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor is present or not through program in 4-bit units. (8 pins) Functions Serial chip select (CH1) input. Serial data (CH1) input. Serial data (CH1) output. Serial clock (CH1) I/O. Serial chip select (CH2) input. Serial data (CH2) input. Serial data (CH2) output. Serial clock (CH2) I/O. UART transmission data output. UART reception data input. External event input for 8-bit timer/counter. External event input for 16-bit capture timer/ counter. External capture input for 16-bit capture timer/ counter. Remote control receive circuit input. PJ0/KS0 to PJ6/KS6 I/O / Input (Port J) 7-bit I/O port. I/O can be specified in 1-bit units. Standby release input function can be specified Pull-up resistor is present in 1-bit units. or not through (7 pins) program in lower 4-bit units and upper 3-bit units. (7 pins) Connects a crystal for system clock oscillation. (When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL.) System reset. Active at "L" level. Positive power supply for A/D converter. EXTAL XTAL RST AVDD AVREF AVSS VDD VSS VPP Input Input Input Reference voltage input for A/D converter. GND for A/D converter. Positive power supply. (Connect both VDD pins to positive power supply.) GND (Connect all four VSS pins to GND.) Positive power supply pin used for writing inorporated PROM. (Do not make any cunnection to NC.) –5– CXP922P032 I/O Circuit Format for Pins Pin Circuit format After a reset PUL0 register "0" after a reset ∗ PA register Undefined after a reset PA0 to PA7 PAD register "0" after a reset Internal data bus ∗ Pull-up transistor IP Input protection circuit Hi-Z RD approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL0 register "0" after a reset ∗ PB register Undefined after a reset PB0 to PB7 PBD register "0" after a reset Internal data bus RD ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL0 register "0" after a reset ∗ PC register Undefined after a reset PC0 to PC7 PCD register "0" after a reset Internal data bus RD ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) –6– CXP922P032 Pin Circuit format After a reset PUL0 register "0" after a reset ∗1 PD register Undefined after a reset ∗2 IP PD0 to PD7 PDD register "0" after a reset Internal data bus RD Hi-Z ∗1 Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) ∗2 Large current drive 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 3.0 to 3.6V) PUL1 register "0" after a reset ∗1 PE register Undefined after a reset ∗2 IP PE0 to PE7 PED register "0" after a reset Internal data bus RD Hi-Z ∗1 Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) ∗2 Large current drive 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 3.0 to 3.6V) PF0/INT0 to PF4/INT4 PF5/NMI INT0, INT1, INT2, INT3, INT4, NMI Internal data bus RD IP CMOS Schmitt input Hi-Z –7– CXP922P032 Pin Circuit format After a reset TO0 PFSL register "0" after a reset PF6/TO0 PF register "1" after a reset Internal data bus RD "H" level RD Internal data bus PF register "1" after a reset TO1 Internal reset signal 00 01 1x MPX ∗ PF7/TO1/ PWM PWM PFSL register (Bit 7) PFSL register (Bit 6) "00" after a reset TO1 output enable ∗ Pull-up transistor approximately 150kΩ (VDD = 4.5 to 5.5V) approximately 200kΩ (VDD = 3.0 to 3.6V) "H" level ("H" level at ON resistance of pull-up transistor during a reset.) AN0 to AN3 A/D converter Input multiplexer IP Hi-Z –8– CXP922P032 Pin Circuit format ∗ After a reset PUL1 register "0" after a reset PG register Undefined after a reset PGD register "0" after a reset IP PG0/AN4 to PG3/AN7 PGSL register "0" after a reset Internal data bus RD A/D converter Input multiplexer ∗ Pull-up transistor Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL1 register "0" after a reset ∗ PG register Undefined after a reset PG4 to PG7 PGD register "0" after a reset Internal data bus RD ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) –9– CXP922P032 Pin Circuit format After a reset CS0 SI0 CS0 SI0 CMOS Schmitt input IP Hi-Z SO0 SO0 SO0 output enable Hi-Z SCK0 SCK0 SCK0 output enable IP "H" level (Hi-Z during a reset) SCK0 CMOS Schmitt input PUL1 register "0" after a reset PH register Undefined after a reset ∗ PH0/CS1 PH1/SI1 PH4/CS2 PH5/SI2 PHD register "0" after a reset Internal data bus RD CS1, SI1, CS2, SI2 IP Hi-Z CMOS Schmitt input ∗ Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) – 10 – CXP922P032 Pin Circuit format ∗ After a reset PUL1 register "0" after a reset SO1, SO2 SO1, SO2 output enable PHSL register PH2/SO1 PH6/SO2 "0" after a reset PH register Undefined after a reset PHD register "0" after a reset Internal data bus RD IP Hi-Z ∗ Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL1 register "0" after a reset SCK1, SCK2 SCK1, SCK2 output enable PHSL register "0" after a reset ∗ PH3/SCK1 PH7/SCK2 PH register Undefined after a reset PHD register "0" after a reset Internal data bus RD SCK1, SCK2 CMOS Schmitt input ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL2 register "0" after a reset TxD TxD output enable ∗ PI register PI0/TxD Undefined after a reset PID register "0" after a reset Internal data bus RD ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) – 11 – CXP922P032 Pin Circuit format After a reset PUL2 register "0" after a reset PI register Undefined after a reset ∗ PI1/RxD PI4/EC0 PI5/EC1 PI6/CINT PI7/RMC PID register "0" after a reset Internal data bus RD RxD, EC0, EC1, CINT, RMC IP Hi-Z CMOS Schmitt input ∗ Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL2 register "0" after a reset ∗ PI register Undefined after a reset PI2 to PI3 PID register "0" after a reset Internal data bus RD ∗ Pull-up transistor IP Hi-Z approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) PUL2 register "0" after a reset PJ register Undefined after a reset ∗ PJ0/KS0 to PJ6/KS6 PJD register "0" after a reset Internal data bus RD Standby release IP Hi-Z ∗ Pull-up transistor approximately 100kΩ (VDD = 4.5 to 5.5V) approximately 150kΩ (VDD = 3.0 to 3.6V) – 12 – CXP922P032 Pin Circuit format After a reset EXTAL IP EXTAL XTAL Oscillation stop control XTAL • Diagram shows circuit configuration during oscillation. • Feedback resistor is removed during stop mode, and XTAL is driven at "H" level. Oscillation Mask option ∗ OP RST IP CMOS Schmitt input ∗ Pull-up transistor "L" level (during a reset) approximately 300kΩ (VDD = 4.5 to 5.5V) approximately 500kΩ (VDD = 3.0 to 3.6V) – 13 – CXP922P032 Absolute Maximum Ratings Item Symbol VDD VPP Supply voltage AVDD AVREF AVSS Input voltage Output voltage High level output current High level total output current VIN VOUT IOH ∑IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ∑IOL Topr Tstg PD 20 130 –20 to +75 –55 to +150 600 mA mA °C °C mW Rating –0.3 to +7.0 –0.3 to +13.0 AVSS to +7.0∗1 AVSS to +7.0 –0.3 to +0.3 –0.3 to +7.0∗2 –0.3 to +7.0∗2 –5 –50 15 Unit V V V V V V V mA mA mA (VSS = 0V reference) Remarks Unique to version with incorporated PROM Output (value per pin) Total for all output pins All pins excluding large current output pins (value per pin) Large current output pins∗3 (value per pin) Total for all output pins QFP-100P-L01 ∗1 AVDD must be the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. ∗3 The large current drive transistor is N-ch transistor of PD and PE. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 14 – CXP922P032 Recommended Operating Conditions Item Symbol Min. 3.0 2.7 VDD Supply voltage 2.7 2.5 AVDD AVREF VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 2.7 2.7 0.7VDD 0.8VDD 0.8VDD 0.7VDD 0 0 0 –0.3 –0.3 –20 5.5 5.5 5.5 5.5 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.2VDD 0.3VDD 0.2VDD +75 V V V V V V V V V V V V V °C ∗2, ∗4 ∗2, ∗5 CMOS Schmitt input∗3 EXTAL ∗2, ∗4 ∗2, ∗5 CMOS Schmitt input∗3 EXTAL∗4 EXTAL∗5 Max. 5.5 5.5 Unit V V Remarks (VSS = 0V reference) fEX = 20MHz or less Guaranteed operation range for 2, 4 and 8 frequency fEX = 12MHz or less dividing clocks Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed data hold range during stop mode ∗1 ∗1 AVDD and VDD must be the same voltage. ∗2 PA, PB, PC, PD, PE, PG, PH2, PH6, PI0, PI2, PI3, PJ for normal input port. ∗3 PF0 to PF5, PH0, PH1, PH3 to PH5, PH7, PI1, PI4 to PI7, CS0, SI0, SCK0, RST. ∗4 When the supply voltage (VDD) is within the range of 4.5 to 5.5V. ∗5 When the supply voltage (VDD) is within the range of 2.7 to 5.5V. – 15 – CXP922P032 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PE, PF6, PF7, PG to PJ, SO0, SCK0 PA to PE, PF6, PF7, PG to PJ, SO0, SCK0 PD, PE IIHE IILE Input current IILR IIL EXTAL RST∗1 PA to PE∗2, PG to PJ∗2 Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIH = 4.0V –2.78 0.5 –0.5 –1.5 (Topr = –20 to +75°C, VSS = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 –400 –45 Typ. Max. Unit V V V V V µA µA µA µA µA VOL I/O leakage IIZ current PA to PE∗2, PF0 to PF5, PF7, PG to PJ∗2, VDD = 5.5V, VI = 0, 5.5V AN0 to AN3, CS0, SI0, SO0, SCK0, RST∗1 VDD = 5 ± 0.5V, 20MHz crystal oscillation (C1 = C2 = 10pF) VDD, VSS VDD = 5 ± 0.5V, 20MHz crystal oscillation (C1 = C2 = 10pF), sleep mode VDD = 5.5V, stop mode PA to PE, PF0 to PF5, PG to PJ, AN0 to AN3, CS0, SI0, SCK0, EXTAL, RST 45 ±10 µA IDD∗4 Supply current∗3 75 mA IDDS1 IDDS2 8 14 10 mA µA Input capacitance CIN Clock 1MHz 0V for all pins excluding measured pins 10 20 pF ∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗2 PA to PE and PG to PJ specify the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗3 When all output pins are open. ∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (2 frequency dividing clock). – 16 – CXP922P032 DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PE, PF6, PF7, PG to PJ, SO0, SCK0 PA to PE, PF6, PF7, PG to PJ, SO0, SCK0 PD, PE IIHE IILE Input current IILR IIL EXTAL RST∗1 PA to PE∗2, PG to PJ∗2 Conditions VDD = 3.0V, IOH = –0.15mA VDD = 3.0V, IOH = –0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5.0mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 0.3V VDD = 3.0V, VIH = 2.7V (Topr = –20 to +75°C, VSS = 0V reference) Min. 2.7 2.3 0.3 0.5 1.0 0.3 –0.3 –0.7 20 –20 –200 –30 –1.0 Typ. Max. Unit V V V V V µA µA µA µA µA VOL I/O leakage IIZ current PA to PE∗2, PF0 to PF5, PF7, PG to PJ∗2, VDD = 3.6V, VI = 0, 3.6V AN0 to AN3, CS0, SI0, SO0, SCK0, RST∗1 VDD = 3.3 ± 0.3V, 20MHz crystal oscillation (C1 = C2 = 10pF) VDD, VSS VDD = 3.3 ± 0.3V, 20MHz crystal oscillation (C1 = C2 = 10pF), sleep mode VDD = 3.6V, stop mode PA to PE, PF0 to PF5, PG to PJ, AN0 to AN3, CS0, SI0, SCK0, EXTAL, RST 25 ±10 µA IDD∗4 Supply current∗3 45 mA IDDS1 IDDS2 4.5 8 10 mA µA Input CIN capacitance Clock 1MHz 0V for all pins excluding measured pins 10 20 pF ∗1 RST specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗2 PA to PE and PG to PJ specify the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. ∗3 When all output pins are open. ∗4 When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (2 frequency dividing clock). – 17 – CXP922P032 AC Characteristics (1) Clock timing Item Main clock base oscillation frequency Main clock base oscillation input pulse width Main clock base oscillation input rise time, fall time Symbol fEX Pins XTAL EXTAL EXTAL EXTAL (Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Conditions VDD = 3.0 to 5.5V Fig.1, Fig.2 Min. 1 1 Typ. Max. 20 12 Unit MHz tXL, tXH tXR, tXF Fig.1, Fig.2 VDD = 3.0 to 5.5V 23 External clock drive 37.5 Fig.1, Fig.2 External clock drive 100 ns ns Note) tsys indicates the four values below according to the upper two bits (PCK1,PCK0) of the clock control register (CLC: 0002FEh). tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10), 16/fEX (PCK1, PCK0 = 11) 1/fEX EXTAL 0.7VDD 0.3VDD ( VDD = 4.5 to 5.5 V ) 0.2VDD ( VDD = 2.7 to 5.5 V ) tXH tXF tXL tXR Fig.1. Clock timing Oscillator connection example of main oscillation circuit Connection example of external clock EXTAL XTAL EXTAL XTAL 74HC04 C1 C2 Fig.2. Oscillator connection and clock applied conditions – 18 – CXP922P032 (2) Event count input Item Event count input clock pulse width Symbol Pins EC0, EC1 (Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Conditions Fig.3 Min. Max. Unit ns tEH, tEL tsys + 100 EC0 EC1 0.8VDD 0.2VDD tEH tEL Fig.3. Event count input timing (3) Interruption and reset input Item Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Conditions Min. Max. Unit ns µs External interruption high, low level width tIH, tIL Main mode NMI INT0 to INT4 Sleep mode KS0 to KS6 Stop mode φ INT0, INT1, INT4 Noise filter selected PS4 PS6 tsys + 100 1 2tsys + 100 32/fEX + 100 128/fEX + 100 3tsys + 200 ns Reset input low level width tRST RST Fig.5 ns tIH 0.8VDD NMI INT0 to INT7 KS0 to KS6 tIL 0.2VDD Fig.4. Interruption input timing tRST RST 0.2VDD Fig.5. Reset input timing – 19 – CXP922P032 (4) A/D converter characteristics (Topr = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, VSS = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage AVREF current IREFS VDD = AVDD = AVREF = 5.0V Symbol Pins Conditions Min. Typ. Max. 8 ±2 ±3 31/fADC∗ 10/fADC∗ AVREF AN0 to AN7 Main mode AVREF Sleep mode Stop mode AVDD – 0.5 0 0.6 1.0 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VREF VIAN IREF (Topr = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, VSS = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage AVREF current IREFS VDD = AVDD = AVREF = 3.3V Symbol Pins Conditions Min. Typ. Max. 8 ±2 ±3 31/fADC∗ 10/fADC∗ AVREF AN0 to AN7 Main mode AVREF Sleep mode Stop mode AVDD – 0.3 0 0.4 0.7 10 Unit Bits LSB LSB µs µs V V mA µA tCONV tSAMP VREF VIAN IREF – 20 – CXP922P032 ∗ fADC indicates the below values due to the contents of Bit 6 (CKS) of the A/D control register (ADC: 000131h). When PS3 is selected, fADC = fEX/8 When PS4 is selected, fADC = fEX/16 However, when PS3 is selected, fEX is 12MHz or less. FFh FEh Digital conversion value (100h) FFh FEh Digital conversion value Linearity error Absolute error 01h 00h Absolute error Analog input VREF 01h 00h VZT∗1 Analog input VFT∗2 ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. Fig.6. Definition of A/D converter terms – 21 – CXP922P032 (5) Serial transfer (CH0, CH1, CH2) Item CS ↓ → SCK delay time CS ↑ → SCK float delay time CS ↓ → SO delay time CS ↑ → SO float delay time Symbol Pins SCK0 SCK1 SCK2 SCK0 (Topr = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Conditions External start transfer mode (SCK = output mode) External start transfer mode (SCK = output mode) Min. Max. 1.5tsys + 100 Unit ns tDCSK tDCSKF SCK1 SCK2 SO0 SO1 SO2 SO0 1.5tsys + 100 ns tDCSO External start transfer mode 1.5tsys + 100 ns tDCSOF SO1 SO2 CS0 CS1 CS2 SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 SI0 SI1 SI2 SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 External start transfer mode 1.5tsys + 100 ns CS high level width tWHCS External start transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode tsys + 100 2tsys + 150 8/fEX ns ns ns ns ns ns ns ns ns SCK cycle time tKCY tKH tKL tSIK SCK high, low pulse width SI input data setup time (for SCK ↑) SI input data hold time (for SCK ↑) SCK ↓ → SO delay time tsys + 60 4/fEX – 25 50 100 tKSI tsys + 100 50 tKSO tsys + 100 50 3tsys + 100 8/fEX ns ns ns ns Minimum interval time tINT Note) The load condition for the SCK output mode and SO output delay time is 50pF+1TTL. – 22 – CXP922P032 (Topr = –20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference) Item CS ↓ → SCK delay time CS ↑ → SCK float delay time CS ↓ → SO delay time CS ↑ → SO float delay time Symbol Pins SCK0 SCK1 SCK2 SCK0 Conditions External start transfer mode (SCK = output mode) External start transfer mode (SCK = output mode) Min. Max. 1.5tsys + 200 Unit ns tDCSK tDCSKF SCK1 SCK2 SO0 SO1 SO2 SO0 1.5tsys + 200 ns tDCSO External start transfer mode 1.5tsys + 200 ns tDCSOF SO1 SO2 CS0 CS1 CS2 SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 SI0 SI1 SI2 SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 External start transfer mode 1.5tsys + 200 ns CS high level width tWHCS External start transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode tsys + 200 2tsys + 200 8/fEX ns ns ns ns ns ns ns ns ns SCK cycle time tKCY tKH tKL tSIK SCK high, low pulse width SI input data setup time (for SCK ↑) SI input data hold time (for SCK ↑) SCK ↓ → SO delay time tsys + 80 4/fEX – 50 80 150 tKSI tsys + 120 70 tKSO tsys + 200 80 3tsys + 150 8/fEX ns ns ns ns Minimum interval time tINT Note) The load condition for the SCK output mode and SO output delay time is 50pF. – 23 – CXP922P032 tWHCS CS0 CS1 CS2 0.2VDD 0.8VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 SCK1 SCK2 0.2VDD tSIK tKSI 0.8VDD SI0 SI1 SI2 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 SO1 SO2 Output data 0.2VDD tINT SCK0 SCK1 SCK2 0.8VDD Fig.7. Serial transfer CH0, CH1, CH2 timing – 24 – CXP922P032 (6) Remote control reception Item Remote control receive high, low level width Symbol Pins (Topr = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) Conditions PS5 selected Main mode Sleep mode Min. 128/fEX + 100 256/fEX + 100 ns Max. Unit tRMC RMC PS6 selected PS8 selected 1024/fEX + 100 0.8VDD RMC 0.2VDD tRMC tRMC Fig.8. Remote control signal input timing – 25 – CXP922P032 Appendix (i) Main oscillation circuit (ii) Main oscillation circuit EXTAL XTAL Rd EXTAL XTAL Rd C1 C2 C1 C2 Fig.9. Recommended oscillation circuit Manufacturer Model CSA4.00MG CSA8.00MTZ093 CSA10.0MTZ093 CSA12.0MTZ093 CST4.00MGW∗ CST8.00MTW093∗ CST10.0MTW093∗ CST12.0MTW093∗ CSA16.00MXZ040 CST16.00MXW0C1∗ CSA20.00MXZ040 CST20.00MXW0H1∗ fEX (MHz) 4 8 10 12 4 8 10 12 16 16 20 20 4 8 10 12 16 20 4 8 10 12 16 20 4 8 10 12 16 20 C1 (pF) C2 (pF) Rd (Ω) Circuit example Remarks (i) 30 30 0 (ii) MURATA MFG CO., LTD. 5 5 0 (i) (ii) (i) (ii) VDD = 4.0 to 5.5V RIVER ELETEC HC-49/U03 CO., LTD. 27 15 10 10 8 6 22 27 15 10 10 8 6 22 560 330 330 180 0 0 2.2k (i) CL = 18.5pF CL = 13.0pF CL = 10.5pF CL = 10.5pF CL = 10.0pF CL = 8.5pF CL = 16pF VDD = 3.0 to 5.5V KINSEKI LTD. HC49/U-S (i) 10 10 0 CL = 12pF VDD = 3.5 to 5.5V 38 (±20%) 0 20 (±20%) 0 20 (±20%) 0 TDK (ii) Corporation 20 (±20%) 0 10 (±20%) 0 VDD = 3.5 to 5.5V 10 (±20%) 0 ∗ Indicates types with on-chip grounding capacitor (C1, C2). CCR∗∗∗ : Surface mounted type ceramic oscillator. CL : Load capacitor Mask option table Item Reset pin pull-up resistor Non-existent – 26 – Content Existent CCR4.0MC3∗ CCR8.0MC5∗ CCR10.0MC5∗ CCR12.0MC5∗ CCR16.0MC6∗ CCR20.0MC6∗ 38 (±20%) 20 (±20%) 20 (±20%) 20 (±20%) 10 (±20%) 10 (±20%) CXP922P032 Characteristics Curve (fEX = 20MHz, Topr = 25°C, Typical) 50 40 30 25 20 15 10 8 6 5 4 3 2 3 4 5 VDD – Supply voltage [V] 6 4 frequency dividing mode 8 frequency dividing mode 16 frequency dividing mode 2 frequency dividing mode IDD vs. VDD IDD – Supply current [mA] Sleep mode (VDD = 5V, Topr= 25°C, Typical) 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0 fEX 2 frequency dividing mode IDD vs. fEX IDD – Supply current [mA] 4 frequency dividing mode 8 frequency dividing mode 16 frequency dividing mode Sleep mode 15 20 5 10 – Main clock base oscillation frequency [MHz] – 27 – CXP922P032 Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 80 51 + 0.1 0.15 – 0.05 81 50 + 0.4 14.0 – 0.1 17.9 ± 0.4 15.8 ± 0.4 A 100 31 1 0.65 + 0.15 0.3 – 0.1 30 0.13 M + 0.35 2.75 – 0.15 + 0.2 0.1 – 0.05 0.15 DETAIL A 0.8 ± 0.2 0° to 10° (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g – 28 –