CXR702F080

CXR702F080 CMOS 32-bit Single Chip Microcomputer Description The CXR702F080 is a CMOS 32-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer, bus interface unit, DMA controller, memory stick interface, and as well as basic configurations like a 32-bit RISC CPU, ROM, RAM, and I/O port. This also provides the idle/sleep/stop functions that enable lower power consumption. Features • CPU • Minimum instruction cycle • • • 176 pin LFLGA (Plastic) • • SR11 series 32-bit RISC CPU core 54.3ns (fSRC: 18.432MHz) 30.5µs (fTEX: 32.768kHz) Incorporated FLASH EEPROM 256K bytes Incorporated RAM 16K bytes Peripheral functions — Bus interface unit — DMA controller 4 channels — A/D converter 8-bit 4-analog input, successive approximation system — Serial interface Clock synchronization, 2 channels Clock synchronization, 1 channel (Incorporated 64-byte buffer RAM) Asynchronization, 2 channels — Timers 8-bit timer, 8 channels 16-bit capture timer, 3 channels 8-bit time-base timer Clock prescaler 16-bit watchdog timer — Memory stick interface — Beep output circuit — External interruption 11 channels (polarity selection and both edge detection possible) Standby mode Idle/sleep/stop Package 176-pin plastic LFLGA Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01739 AVDD AVREF AVSS MSINS INT0 to INT9 TDO TRST RTCK TCK TMS TDI 10 ∗1 24 16 8 AN0 to AN3 4 A/D CONVERTER CLOCK GENERATOR/ SYSTEM CONTROLLER EXTERNAL BUS SCS1 SI1 SO1 SCK1 BUS INTERFACE UNIT SERIAL INTERFACE UNIT (CH1) FLASH EEPROM 256K BYTES ARM7TDMI CPU CORE SCS0 SI0 SO0 SCK0 SERIAL INTERFACE UNIT (CH0) RAM TXOUT TX TEX XOUT XTAL EXTAL RST VDD VSS Block Diagram 19 8 2 TxD0 RxD0 2∗2 6 3∗1 ∗2 RAM 16K BYTES UART (CH0) 2∗2 DMAC (CH0) DMAC (CH1) DMAC (CH2) DMAC (CH3) 8∗1 16-BIT CAPTURE TIMER (CH0) WATCHDOG TIMER 16-BIT CAPTURE TIMER (CH1) TOKEI PRESCALER 16-BIT CAPTURE TIMER (CH2) INTERRUPT CONTROLLER SCS2 SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) A0 to A23 D0 to D15 CS0 to CS7 RD WE LWR/LB UWR/UB WAIT MA0 to MA18 MD0 to MD7 MCS0, MCS1 MRD MWE DACK0 DREQ0 DACK1 DREQ1 TxD1 RxD1 UART (CH1) –2– 6 8 6 4 8 6 6 4 8 MSBS MSDIO MSIDR MSSCLK EC0 MEMORY STICK INTERFACE 8-BIT TIMER/COUNTER (CH0) T1 EC2 8-BIT TIMER (CH1) 8-BIT TIMER/COUNTER (CH2) T3 8-BIT TIMER (CH3) 8-BIT TIMER (CH4) CT0ED0 CT0ED1 CT1ED0 CT1ED1 CT2ED0 CT2ED1 BEEP 8-BIT TIMER (CH5) 8-BIT TIMER (CH6) PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I PORT J PORT K PORT L PORT M PORT N PORT O 8-BIT TIMER (CH7) 8 8 7 3 8 4 CXR702F080 ∗1 The number of causes of interrupts generated from the module is as shown. But the number of causes input to the interrupt controller differs from the shown becauses of OR. ∗2 A part of the interrupt signals generated from UART, MEMORY STICK INTERFACE is input to the interrupt controller via DMA depending on applications. CXR702F080 Pin Assignment (Top View) 176-pin LFLGA package • Pin Assignment 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R P N M L K J H G F E D C B A 88 89 93 97 101 105 109 113 117 121 124 127 130 131 132 87 90 91 92 96 100 104 108 112 116 120 125 126 134 133 86 82 85 95 99 103 107 111 115 119 123 128 129 135 137 83 81 84 80 78 79 77 72 76 74 73 68 71 70 69 64 67 66 65 60 63 61 56 57 52 55 54 53 48 49 47 41 40 35 31 27 23 19 15 11 7 173 170 174 45 46 38 44 43 42 R P N M L K J H G F E D C B A 59 58 51 50 34 30 26 22 18 14 10 94 98 102 106 110 114 118 122 138 139 136 141 75 62 37 32 28 24 20 16 12 8 4 3 2 175 39 36 33 29 25 21 17 13 9 5 1 176 142 143 140 145 146 147 144 149 150 151 148 153 154 155 152 157 158 159 156 161 162 163 160 165 166 167 164 168 6 172 169 171 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 –3– CXR702F080 • Pin Assignment Table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Pin position B1 B2 C2 D2 C1 D4 D3 E2 D1 E4 E3 F2 E1 F4 F3 G2 F1 G4 G3 H2 G1 H4 H3 J2 H1 J4 J3 K2 J1 K4 K3 L2 K1 L4 L3 L1 M2 PB3 PB4 PB5 PB6 PB7 VDD VSS PC0 PC1 PC2 PC3 PC4 PC5 PD0 PD1 PD2 PD3 VDD VSS PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5 PE6/INT6 PE7/INT7 PF0/EC0 PF1/T1 PF2/EC2 PF3/T3 PF4/BEEP PF5/TXOUT VDD VSS PG0/CT0ED0 PG1/CT0ED1 Symbol Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Pin position N2 M1 M3 N3 N1 P1 R1 R2 P2 P3 P4 R3 M4 N4 P5 R4 M5 N5 P6 R5 M6 N6 P7 R6 M7 N7 P8 R7 M8 N8 P9 R8 M9 N9 P10 R9 M10 Symbol PG2/CT1ED0 PG3/CT1ED1 PG4/CT2ED0 PG5/CT2ED1 PH0/TxD0 PH1/RxD0 PH2/TxD1 PH3/RxD1 VDD VSS PI0/MD0 PI1/MD1 PI2/MD2 PI3/MD3 PI4/MD4 PI5/MD5 PI6/MD6 PI7/MD7 VDD VSS PJ0/D0 PJ1/D1 PJ2/D2 PJ3/D3 PJ4/D4 PJ5/D5 PJ6/D6 PJ7/D7 VDD VSS PK0/D8 PK1/D9 PK2/D10 PK3/D11 PK4/D12 PK5/D13 PK6/D14 –4– Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 Pin position M11 N10 R10 P11 N11 R11 P12 P13 R12 N12 N13 R13 R14 R15 P15 P14 N14 M14 N15 M12 M13 L14 M15 L12 L13 K14 L15 K12 K13 J14 K15 J12 J13 H14 J15 H12 H13 VDD TEX TX VSS CS0 CS1 RD LWR/LB UWR/UB MRD MWE/WE MCS0 VDD VSS MA0 MA1/A9 MA2/A10 MA3/A11 MA4/A12 MA5/A13 MA6/A14 MA7/A15 MA8/A16 PL0/MA9/A17 PL1/MA10/A18 PL2/MA11/A19 PL3/MA12/A20 PL4/MA13/A21 PL5/MA14/A22 PL6/MA15/A23 VDD VSS MA16 MA17 MA18/A0 A1 Symbol PK7/D15 CXR702F080 Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 Pin position G14 H15 G12 G13 F14 G15 F12 F13 E14 F15 E12 E13 E15 D14 C14 D15 D13 C13 C15 B15 A15 A14 A2 A3 A4 A5 A6 A7 A8 VDD Symbol Pin No. 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Pin position B14 B13 B12 A13 D12 C12 B11 A12 D11 C11 B10 A11 D10 C10 B9 A10 D9 C9 B8 A9 D8 C8 AN0 Symbol TEST1 PM0/AN1 PM1/AN2 PM2/AN3 AVSS AVREF AVDD TDI TMS TRST TCK RTCK TDO RST VDD VSS PN0/SCK0 PN1/SO0 PN2/SI0 PN3/SCS0/INT8 PN4/SCK1 Pin No. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin position B7 A8 D7 C7 B6 A7 D6 C6 B5 A6 D5 C5 A5 B4 B3 A4 C4 C3 A3 A2 A1 Symbol PN5/SO1 PN6/SI1 PN7/SCS1/INT9 PO0/SCK2 PO1/SO2 PO2/SI2 PO3/SCS2 XOUT/CKO VDD VSS PWE NC PA0/WAIT PA1/CS2 PA2/CS3 PA3/CS4 PA4/CS5 PA5/MCS1 PB0 PB1 PB2 EXTAL XTAL VSS MSDIO MSBS MSSCLK MSDIR MSINS DACK0 DACK1 DREQ0 DREQ1 TEST2 TEST0 –5– CXR702F080 Pin Functions Symbol PA0/WAIT PA1/CS2 to PA4/CS5 PA5/MCS1 I/O I/O / Input I/O / Output I/O / Output (Port A) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) Functions Wait input for external bus Chip select output for external S bus (4 pins) Chip select output for external M bus. PB0 to PB7 I/O (Port B) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port C) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) (Port D) 4-bit open drain port. Lower 2 bits are for output; upper 2 bits are for I/O. (4mA drive) Upper 2 bits can be specified in 1-bit units. (4 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port F) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) (Port G) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) PC0 to PC5 I/O PD0, PD1 Output PD2, PD3 I/O PE0/INT0 to PE7/INT7 I/O / Input External interruption request input. (8 pins) PF0/EC0 PF1/T1 PF2/EC2 PF3/T3 PF4/BEEP PF5/TXOUT I/O / Input I/O / Output I/O / Input I/O / Output I/O / Output I/O / Output External event input to 8-bit timer (CH0). 8-bit timer (CH1) output. External event input to 8-bit timer (CH2). 8-bit timer (CH3) output. Beep output. Sub oscillation output. PG0/CT0ED0 to PG5/ CT2ED1 I/O / Input Capture input of 16-bit capture timer. (6 pins) –6– CXR702F080 Symbol PH0/TxD0 PH1/RxD0 PH2/TxD1 PH3/RxD1 I/O I/O / Output I/O / Input I/O / Output I/O / Input (Port H) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins) (Port I) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port J) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port K) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) Functios UART (CH0) transmit data output. UART (CH0) receive data input. UART (CH1) transmit data output. UART (CH1) receive data input. PI0/MD0 to PI7/MD7 I/O / I/O Data bus for external M bus. (8 pins) PJ0/D0 to PJ7/D7 I/O / I/O Data bus for external S bus. (16 pins) PK0/D8 to PK7/D15 I/O / I/O A1 to A8 MA18/A0 MA1/A9 to MA8/A16 Output Output / Output Output / Output (Port L) 7-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (7 pins) Address bus output for external S bus. (24 pins) PL0/MA9/A17 to PL6/MA15/ A23 I/O / Output / Output Address bus output for external M bus (19 pins) MA0 MA16, MA17 AN0 PM0/AN1 to PM2/AN3 Output Output Input Input / Input (Port M) 3-bit input port. (3-pins) –7– Analog input to A/D converter. (4 pins) CXR702F080 Symbol PN0/SCK0 PN1/SO0 PN2/SI0 PN3/SCS0/ INT8 PN4/SCK1 PN5/SO1 PN6/SI1 PN7/SCS1/ INT9 PO0/SCK2 PO1/SO2 PO2/SI2 PO3/SCS2 CS0, CS1 RD LWR/LB UWR/UB MRD MWE/WE MCS0 DACK0 DREQ0 DACK1 DREQ1 MSDIR MSBS MSSCLK MSDIO MSINS TEST0 TEST1 TEST2 TDI I/O I/O / I/O I/O / Output I/O / Input I/O / Input / Input I/O / I/O I/O / Output I/O / Input I/O / Input / Input I/O / I/O I/O / Output I/O / Input I/O / Input Output Output Output / Output Output / Output Output Output Output Input Output Input Output Output Output I/O Input Input Input Input Input Test. (Connect to Vss.) (Port O) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins) (Port N) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) Functios Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input. Serial clock (CH1) I/O. Serial data (CH1) output. Serial data (CH1) input. Serial chip select (CH1) input. Serial clock (CH2) I/O. Serial data (CH2) output. Serial data (CH2) input. Serial chip select (CH2) input. External interruption request input. External interruption request input. Chip select output for external S bus. (2 pins) Read signal output for external S bus. Write strobe signal output for D0 to D7. Write strobe signal output for D8 to D15. Read signal output for external M bus. Chip select output for external M bus. Transfer request acknowledge signal output from DMA controller (CH0). Transfer request input to DMA controller (CH0). Transfer request acknowledge signal output from DMA controller (CH1). Transfer request input to DMA controller (CH1). Memory stick interface data I/O direction monitor. Memory stick interface bus state output. Memory stick interface clock output. Memory stick interface data I/O direction monitor. Memory stick interface card detection. Strobe signal output indicates access to D0 to D7. Strobe signal output indicates access to D8 to D15. Output / Output Write signal output for external M bus. Write signal output for external S bus. Data input for JTAG boundary scanning test. –8– CXR702F080 Symbol TMS TRST TCK RTCK TDO EXTAL XTAL XOUT/CKO TEX TX RST PWE NC AVDD AVREF AVSS VDD VSS Input Input Input Input I/O Functions Test mode control input for JTAG boundary scanning test. Reset input for JTAG boundary scanning test. Clock input for JTAG boundary scanning test. Clock output for JTAG boundary scanning test. Data output for JTAG boundary scanning test. Oscillation connector of main oscillation. (When a clock is supplied externally, input it to EXTAL; opposite phase clock should be input to XTAL.) System clock output. Output Output Input Output Output / Output Main oscillation output. Input Output I/O Input Oscillation connector of main oscillation. (When a clock is supplied externally, input it to TEX; opposite phase clock should be input to TX.) System reset. FLASH EEPROM miswriting protection signal input. NC. (Leave this pin open or connect to Vss.) Positive power supply for A/D converter. Reference voltage input for A/D converter. GND for A/D converter. Positive power supply (Connect all twelve VDD pins to positive power supply.) GND (Connect all twelve Vss pins to GND) –9– CXR702F080 I/O Circuit Format for Pins Pin Port A data Circuit format After a reset Port A direction "0" after a reset Pull-up resistor "0" after a reset PA0/WAIT Hi-Z Internal data bus RD MPX Input data latch WAIT IP CS2 to CS5 MPX Port A data Port A function select "0" after a reset S bus pin active PA1/CS2 to PA4/CS5 MPX Port A direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z MCS1 (M bus unused: CS7) MPX Port A data Port A function select "0" after a reset PA5/MCS1 Port A direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z – 10 – CXR702F080 Pin Port B data Circuit format After a reset Port B direction "0" after a reset PB0 to PB7 Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z Port C data Port C direction "0" after a reset PC0 to PC5 Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z Port D data PD0 PD1 Internal data bus RD Hi-Z Port D data Port D read select "0" after a reset Internal data bus RD MPX Input data latch IP PD2 PD3 Hi-Z – 11 – CXR702F080 Pin Circuit format After a reset Port E data Port E direction "0" after a reset PE0/INT0 to PE7/INT7 Pull-up resistor "0" after a reset Internal data bus RD INT0 to INT7 MPX Input data latch IP CMOS Schmitt input Hi-Z Port F data Port F direction "0" after a reset PF0/EC0 PF2/EC2 Pull-up resistor "0" after a reset Internal data bus RD EC0, EC2 MPX Input data latch IP CMOS Schmitt input Hi-Z T1, T3, BEEP, TXOUT MPX Port F data Port F function select "0" after a reset PF1/T1 PF3/T3 PF4/BEEP PF5/TXOUT Port F direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z – 12 – CXR702F080 Pin Port G data Circuit format After a reset Port G direction PG0/CT0ED0 PG1/CT0ED1 PG2/CT1ED0 PG3/CT1ED1 PG4/CT2ED0 PG5/CT2ED1 "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD CT0ED0, CT0ED1 CT1ED0, CT1ED1 CT2ED0, CT2ED1 MPX Input data latch IP CMOS Schmitt input Hi-Z TxD0, TxD1 MPX Port H data Port H function select "0" after a reset PH0/TxD0 PH2/TxD1 Port H direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z Port H data Port H direction "0" after a reset PH1/RxD0 PH3/RxD1 Pull-up resistor "0" after a reset Internal data bus RD RxD0, RxD1 MPX Input data latch IP CMOS Schmitt input Hi-Z – 13 – CXR702F080 Pin Circuit format MD0 to MD7 MPX Port I data Port I function select "1" after a reset M bus output enable MPX After a reset PI0/MD0 to PI7/MD7 Port I direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MD0 to MD7 D0 to D7 MPX Port J data Port J function select "1" after a reset S bus output enable MPX MPX Input data latch IP Hi-Z PJ0/D0 to PJ7/D7 Port J direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD D0 to D7 D8 to D15 MPX Port K data Port K function select "1" after a reset S bus output enable MPX MPX Input data latch IP Hi-Z PK0/D8 to PK7/D15 Port K direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD D8 to D15 MPX Input data latch IP Hi-Z – 14 – CXR702F080 Pin A1 to A8 Circuit format After a reset A1 to A8 S bus pin active Low MA18 MA18/A0 A0 S bus/M bus select MPX Low MA1/A9 to MA8/A16 MA1 to MA8 A9 to A16 S bus/M bus select MPX Low MA9 to MA15 A17 to A23 Port L data S bus/M bus select Port L function select MPX PL0/MA9/A17 to PL6/MA15/A23 "1" after a reset S bus pin high impedance Port L direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Low MA0 MA0 Low MA16 MA17 MA16, MA17 Low – 15 – CXR702F080 Pin Circuit format Analog input select ("1" after a reset) After a reset AN0 AN0 IP Hi-Z Internal data bus RD Input data latch Port M function select "1" after a reset Analog input select ("0" after a reset) AN1, AN2, AN3 IP PM0/AN1 to PM2/AN3 Hi-Z SCK0, SCK1 MPX Port N data Port N function select "0" after a reset SCKEN0, SCKEN1 MPX Port N direction PN0/SCK0 PN4/SCK1 "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD SCK0, SCK1 MPX Input data latch IP CMOS Scmitt input Hi-Z SO0, SO1 MPX Port N data Port N function select "0" after a reset SOEN0, SOEN1 MPX PN1/SO0 PN5/SO1 Port N direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z – 16 – CXR702F080 Pin Port N data Circuit format After a reset Port N direction "0" after a reset PN2/SI0 PN6/SI1 Pull-up resistor "0" after a reset Internal data bus RD SI0, SI1 MPX Input data latch IP Hi-Z Port N data Port N direction "0" after a reset PN3/SCS0/INT8 PN7/SCS1/INT9 Pull-up resistor "0" after a reset Internal data bus RD SCS0, SCS1 INT8, INT9 MPX Input data latch IP CMOS Schmitt input Hi-Z SCK2 MPX Port O data Port O function select "0" after a reset SCKEN2 MPX Port O direction PO0/SCK2 "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD SCK2 MPX Input data latch IP CMOS Schmitt input Hi-Z – 17 – CXR702F080 Pin Circuit format SO2 MPX Port O data Port O functon select "0" after a reset SOEN2 MPX After a reset PO1/SO2 Port O direction "0" after a reset Pull-up resistor "0" after a reset Internal data bus RD MPX Input data latch IP Hi-Z Port O data Port O direction "0" after a reset PO2/SI2 Pull-up resistor "0" after a reset Internal data bus RD SI2 MPX Input data latch IP Hi-Z Port O data Port O direction "0" after a reset PO3/SCS2 Pull-up resistor "0" after a reset Internal data bus RD SCS2 MPX Input data latch IP CMOS Schmitt input Hi-Z – 18 – CXR702F080 Pin CS0, CS1 Circuit format After a reset CS0 CS1 High S bus pin active RD RD S bus pin active High LWR, UWR LWR/LB UWR/UB LB, UB 16-bit SRAM access method select S bus pin active MPX High MRD MRD High MWE MWE/WE WE 16-bit SRAM access method select MPX High MCS0 MCS0 (M bus unused: CS6) High DACK0 DACK1 DACK0, DACK1 High DREQ0 DREQ1 IP DREQ0, DREQ1 Hi-Z – 19 – CXR702F080 Pin Circuit format After a reset MSDIR MSBS MSSCLK MSDIR, MSBS, MSSCLK Low MSDIO (output data) MSDIO MSDIO output enable Hi-Z IP MSDIO (input data) IP MSINS CMOS Schmitt input MSINS Hi-Z System clock XOUT/CKO XTAL Clock output enable Output clock select MPX Oscillation output EXTAL IP • Diagram shows circuit configuration during oscillation. • Feedback resistor is removed during stop mode, and XTAL is driven at “H” level. EXTAL XTAL XTAL Oscillation TEX IP • Diagram shows circuit configuration during oscillation. • Feedback resistor is removed during stop mode, and TEX is driven at “L” level; TX at “H” level. TEX TX TX Oscillation – 20 – CXR702F080 Pin Circuit format CMOS Schmitt input After a reset RST IP Internal reset signal RSTWD (from watchdog timer) Pull-up PWE IP PWE Hi-Z TDI TMS TCK Pull-up IP TDI, TMS, TCK (to CPU core) IP TRST TRST (to CPU core) Pull-down RTCK RTCK High TDO TDO TDO output enable Low TEST0 TEST1 IP TEST0, TEST1 (to test circuit) Hi-Z IP TEST2 (to test circuit) TEST2 Pull-down – 21 – CXR702F080 Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS AVREF Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VIN VOUT IOH ΣIOH IOL ΣIOL Topr Tstg PD Rating –0.3 to +4.6 AVSS to +4.6∗1 –0.3 to +0.3 AVSS to +4.6 –0.3 to +4.6∗2 –0.3 to +4.6∗2 –5 –40 10 80 –20 to +75 –55 to +150 380 Unit V V V V V V mA mA mA mA °C °C mW (Vss = 0V reference) Remarks Output (value per pin) Total for all output pins Output (value per pin) Total for all output pins ∗1 AVDD and VDD must be the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage Analog voltage High level input voltage Symbol VDD AVDD VIH VIHS VIHEX VIL Low level input voltage Hysteresis width Operating temperature VILS VILEX VIHS – VILS Topr –20 Min. 2.7 2.7 0.7VDD 0.7VDD 0.9VDD 0 0 –0.3 0.5 +75 Typ. Max. 3.6 3.6 VDD VDD VDD + 0.3 0.2VDD 0.2VDD 0.4 Unit V V V V V V V V V °C ∗1 CMOS input∗2 (Vss = 0V reference) Remarks CMOS Schmitt trigger input∗3 EXTAL∗4, TEX∗4 CMOS input∗2 CMOS Schmitt trigger input∗3 EXTAL∗4, TEX∗4 CMOS Schmitt trigger input∗3 ∗1 AVDD and VDD must be the same voltage. ∗2 Normal input port (PA to PC, PD2, PD3, PE, PF1, PF3 to PF5, PH0, PH2, PI to PM, PN1, PN2, PN5, PN6, PO1, PO2, DREQ0, DREQ1, MSDIO, TDI, TMS, TRST, TCK, PWE and TEST0 to TEST2). ∗3 Each pin of EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, SCK0 to SCK2, SCS0 to SCS2, INT8, INT9, MSINS and RST. ∗4 Specified only during external clock input. – 22 – CXR702F080 Electrical Characteristics DC Characteristics (VDD = 2.7 to 3.6V) Item Symbol Pins PA to PC, PE to PL, PN, PO, T1, T3, TxD0, TxD1, MCS0, MCS1, MA0 to MA18, MD0 to MD7, MRD, MWE, CS0 to CS5, A0 to A23, D0 to D15, RD, LWR, LB, UWR, UB, WE, RST BEEP TXOUT, SCK0 to SCK2, , SO0 to SO2, DACK0, DACK1, MSDIR, MSBS, MSSCLK, MSDIO, RTCK, TDO, XOUT, CKO PA to PC, PE to PL, PN, PO, T1, T3, TxD0, TxD1, MCS0, MCS1, MA0 to MA18, MD0 to MD7, MRD, MWE, CS0 to CS5, A0 to A23, D0 to D15, RD, LWR, LB, UWR, UB, WE, RST PD, BEEP TXOUT, , SCK0 to SCK2, SO0 to SO2, DACK0, DACK1, MSDIR, MSBS, MSSCLK, MSDIO, RTCK, TDO, XOUT, CKO IIHE IILE IIHT IILT IIH Input current EXTAL TEX TRST PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2∗1 TDI, TMS, TCK (Topr = –20 to +75°C, Vss = 0V reference) Conditions Min. Typ. Max. Unit IOH = –0.5mA VDD – 0.4 V High level output voltage VOH IOH = –4mA VDD – 0.4 V IOL = 1mA 0.4 V Low level output voltage VOL IOL = 4mA 0.4 V VIH = 3.6V VIL = 0.4V VIH = 3.6V VIL = 0.4V VIH = 3.6V 0.1 –0.1 0.1 –0.1 20 100 10 –10 10 –10 240 µA µA µA µA µA IIL VIL = Vss –20 –50 –120 µA VIL = Vss –20 –100 –240 µA ∗1 PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current when non-resistor is selected. – 23 – CXR702F080 Item Symbol Pins PD2, PD3, PM, AN0 to AN3, DREQ0, DREQ1, MSDIO, MSINS, PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2 PD2, PD3, PM, AN0 to AN3, DREQ0, DREQ1, MSDIO, MSINS, PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2∗1 Conditions Min. Typ. Max. Unit IZH VI = 3.6V 10 µA I/O leakage current IZL VI = 0V –10 µA IDD1 Main execution mode 18.432MHz crystal oscillation (C1 = C2 = 10pF) Main idle mode 18.432MHz crystal oscillation (C1 = C2 = 10pF) VDD Sub sleep mode 32.768kHz crystal oscillation (C1 = C2 = 10pF) Ta = –20 to +25°C Stop mode 32.768kHz oscillation stop Ta = –20 to +25°C PA to PC, PD2, PD3, PE to PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, AN0 to AN3, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2, MSDIO, EXTAL, TEX, RST, TEST0 DREQ0, DREQ1, MSINS, TDI, TMS, TRST, TCK, TEST1, TEST2, PWE 60 mA IDDI1 Supply current∗2 IDDS1 32 mA 500 80 500 50 µA µA µA µA IDDS2 11 Clock 1MHz 0V other than the measured pins pF Input capacity CIN 9 pF ∗1 PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current when non-resistor is selected. ∗2 When all output pins are left open and XOUT/CKO = “L” (POSL register SLCKO bit = “00” or “01”). – 24 – CXR702F080 AC Characteristics (1) Clock timing Item Main oscillation input clock frequency Main oscillation input clock pulse width Main oscillation input clock rise time, fall time Sub oscillation input clock frequency Event count input clock pulse width Event count input clock rise time, fall time Symbol fEX Pins XTAL EXTAL XTAL EXTAL XTAL EXTAL TEX TX EC0 EC2 EC0 EC2 (Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 2 32kHz clock applied condition Fig. 3 Fig. 3 2/fPS4 1 32.768 Min. 1 22.5 100/fEX Typ. Max. 20 Unit MHz ns ns kHz µs ms tXL, tXH tCR, tCF fTEX tEH, tEL tER, tEF Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit. 1/fEX 0.9VDD EXTAL XTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation 32kHz clock applied condition Crystal oscillation External clock EXTAL XTAL EXTAL XTAL TEX TX 74HC04 C1 C2 C1 C2 Fig. 2. System clock applied condition EC0 EC2 0.7VDD 0.2VDD tEH tEF tEL tER Fig. 3. Event count input timing – 25 – CXR702F080 (2) Serial transfer (CH0, CH1, CH2) Item SCS ↓ → SCK delay time SCS ↑ → SCK float delay time SCS ↓ → SO delay time SCS ↑ → SO float delay time SCS high level width Symbol Pins SCK0 SCK1 SCK2 SCK0 SCK2 (Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions External start transfer mode Input mode (SCKOE = “1”) Output mode External start transfer mode 100 ns SCKOE = “1”) External start transfer mode (SOEN = “1”) External start transfer mode (SOEN = “1”) External start transfer mode SCK input mode 200 100 ns 100 100 ns ns Min. Max. Unit tDCSK tDCSKF SCK1 (SCK = output mode, tDCSO SO0 SO1 SO2 SO0 tDCSOF SO1 SO2 100 ns tWHCS SCS0 SCS1 SCS2 ns SCK interval time tKINT SCK0 Internal start high6000 2000 + + speed transfer mode fSYS fSIO 6000 3000 External start high+ + fSIO speed transfer mode fSYS tKCY 2 ns ns ns ns ns ns ns ns ns ns 75 50 ns ns tKCY 2 SCK cycle time SCK high, low pulse width Input setup time (for SCK ↑) SI input hold time (for SCK ↑) SCK ↓ → SO delay time tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 SI0 SI1 SI2 SI0 SI1 SI2 SO0 SO1 SO2 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 400 1000/fSCK 200 500/fSCK – 50 50 75 100 50 Notes) 1. The load condition for the SCK output mode and SO output delay time is 50pF. 2. fSIO is fSRC/2 (MHz) for output fSRC of main oscillation circuit. As for fSCK and fSYS, see the following. Serial clock selection PS3∗1 PS4∗1 PS5 PS6 PS7∗2 PS8∗2 fSCK (MHz) fSRC/8 fSRC/16 fSRC/32 fSRC/64 fSRC/128 fSRC/256 Serial clock frequency division ratio No frequency division 2 frequency division 4 frequency division 16 frequency division ∗1 CH1, CH2 only – 26 – ∗2 CH0 only fSCK (MHz) No fSRC/2 fSRC/4 fSRC/16 CXR702F080 tWHCS SCS0 SCS1 SCS2 0.7VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF SCK0 SCK1 SCK2 0.7VDD 0.2VDD tSIK tKSI SI0 SI1 SI2 0.7VDD Input data 0.2VDD tDCSO tKSO tDCSOF SO0 SO1 SO2 0.7VDD Output data 0.2VDD 0.7VDD 0.2VDD tKINT SCK0 SCK1 SCK2 n byte n + 1 byte Fig. 4. Serial transfer CH0, CH1, CH2 timing – 27 – CXR702F080 (3) Serial transfer (memory stick) Item MSSCLK cycle time MSSCLK high, low pulse width MSBS output delay time MSDIO output delay time MSDIO input setup time MSDIO input hold time MSDIR output delay time Symbol Pins MSSCLK MSSCLK MSBS MSDIO MSDIO MSDIO MSDIR (Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference) Conditions Min. 1000/fMSCK 500/fMSCK – 5 For MSSCLK ↓ For MSSCLK ↓ For MSSCLK ↑ For MSSCLK ↑ For MSSCLK ↓ 18 5 10 10 10 Max. Unit ns ns ns ns ns ns ns tKCY tKH tKL tBSD tDIOD tDIOS tDIOH tDIRD Notes) 1. The load condition is 26pF. 2. fMSCK is as follows for output fSRC of main oscillation circuit. Shift clock frequency division ratio fMSCK (MHz) No frequency division 2 frequency division 4 frequency division 8 frequency division fSRC fSRC/2 fSRC/4 fSRC/8 – 28 – CXR702F080 tKCY 0.7VDD MSSCLK 0.2VDD tKL tKH MSBS Bus state output tBSD MSDIO (output) Output data tDIOD MSDIO (input) Input data tDIOS tDIOH MSDIR Serial data I/O direction output tDIRD Fig. 5. Memory stick transfer timing – 29 – CXR702F080 (4) A/D converter characteristics (Topr = –20 to +75°C, VDD = 2.7 to 3.6V, VDD = AVDD, Vss = AVss = 0V reference) Item Resolution Absolute error Conversion time Sampling time Reference input voltage Analog input voltage Symbol Pins Conditions Min. Typ. Max. 8 ±3 Unit Bits LSB µs µs AVDD AVREF V V tCONV tSAMP VREF VIAN AVREF AN0 to AN3 19/fPS4 5/fPS4 VDD = AVDD = 2.7V AVDD – 0.3 0 20/fPS4 Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit. Conversion time indicates the time required from conversion start to ADC interruption request occurrence when 1 channel is selected. This includes sampling time. FFh FEh Digital conversion value Absolute error 01h 00h AVREF Analog input Fig. 6. Definition of A/D converter terms (5) Interruption and reset input Item External interruption high, low level width Reset input high, low level width Symbol (Topr = –20 to +75°C, VDD = 2.7 to 3.6V, Vss = 0V reference) Pins INT0 to INT9 RST Conditions Min. 100 Typ. 200 32/fSRC Max. Unit ns µs tIH tIL tIH tIL Note) fSRC is output of main oscillation circuit. tIH INT0, INT1, INT2, INT3, INT4, INT5, INT6, INT7, INT8, INT9, RST tIL 0.7VDD 0.2VDD Fig. 7. Interruption input, RST input timing – 30 – CXR702F080 Appendix (i) (ii)∗1 EXTAL XTAL Rd1 TEX TX Rd2 C11 C21 C12 C22 Fig. 8. Recommended oscillation circuit Manufacturer Model fc (MHz) 18.432 C11 (pF) 12 C21 (pF) 12 Rd1 (Ω) 0 Circuit example (i) RIVER EIETEC CO., LTD. FCK-03 ∗1 As for (ii) sub oscillation circuit C12, C22 and Rd2, decide them by seeing matching with oscillator. – 31 – CXR702F080 Package Outline Unit: mm 176PIN LFLGA (PLASTIC) 0.2 SA 13.0 PIN 1 INDEX 1.4MAX 0.1MAX 13.0 x4 0.15 0.2 SB 0.2 S 3 – φ0.50 0.55 R P N M L K J H G F E D C B A 0.8 A DETAIL X 176 – φ0.40 ± 0.05 φ0.08 M S A B 0.55 B 0.55 0.5 0.5 0.55 0.90 0.90 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.8 PACKAGE STRUCTURE PACKAGE MATERIAL ORGANIC SUBSTRATE NICKEL & GOLD PLATING COPPER 0.5g SONY CODE EIAJ CODE JEDEC CODE LFLGA-176P-01 P-LFLGA176-13X13-0.8 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS S 0.10 S – 32 – X Sony Corporation