LCX005BK

LCX005BK 1.4cm (0.55-inch) NTSC/PAL Color LCD Panel For the availability of this product, please contact the sales office. Description The LCX005BK is a 1.4cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel provides full-color representation in NTSC/PAL mode. RGB dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. Features • The number of active dots: 113,578 (0.55-inch; 1.397cm in diagonal) • Horizontal resolution: 260 TV lines • High optical transmittance: 3.4% (typ.) • High contrast ratio with normally white mode: 270 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible) • High quality picture representation with RGB delta arranged color filters • Full-color representation • NTSC/PAL compatible • Right/left inverse display function Element Structure • Dots Total dots : 537 (H) × 222 (V) = 119,214 Active dots: 521 (H) × 218 (V) = 113,578 • Built-in peripheral driver using polycrystalline silicon super thin film transistors. Applications • Viewfinders • Super compact liquid crystal monitors etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Z24A5X-PS LCX005BK Block Diagram VCK2 VCK1 HCK2 BLUE GREEN 2 HCK1 16 15 14 13 HST VSS EN 12 11 10 9 8 7 6 5 RED 4 3 H Level Conversion Circuit H Shift Register V Level Conversion Circuit V Shift Register CS LC COM Pad –2– COM 1 RGT VDD CLR VST (NC) LCX005BK Absolute Maximum Ratings (VSS = 0V) • H and V driver supply voltages VDD • H driver input pin voltage HST, HCK1, HCK2 RGT • V driver input pin voltage VST, VCK1, VCK2 CLR, EN • Video signal input pin voltage GREEN, RED, BLUE • Operating temperature Topr • Storage temperature Tstg –1.0 to +17 –1.0 to +17 –1.0 to +17 –1.0 to +15 –10 to +70 –30 to +85 V V V V °C °C Operating Conditions (VSS = 0V) Supply voltage VDD 13.5 ± 0.5 V Input pulse voltage (Vp-p of all input pins except video signal input pins) Vin 2.8V (more than) Pin Description Pin No. 1 2 3 4 (5) 6 7 8 Symbol COM GREEN RED BLUE (NC) HCK1 HCK2 HST Description Common voltage of panel Video signal (G) to panel Video signal (R) to panel Video signal (B) to panel Not connected Clock pulse for H shift register drive Clock pulse for H shift register drive Start pulse for H shift register drive Pin No. 9 10 11 12 13 14 15 16 Symbol RGT CLR EN VCK1 VCK2 VST Vss VDD Description Drive direction pulse for H shift register (H: normal, L: reverse) Improvement pulse for uniformity Enable pulse for gate selection Clock pulse for V shift register drive Clock pulse for V shift register drive Start pulse for V shift register drive GND (H, V drivers) Power supply for H and V drivers –3– LCX005BK Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) Video signal input VDD From H driver Input 1MΩ (2) HCK1, HCK2 VDD 250Ω HCK1 250Ω HCK2 1MΩ 250Ω 250Ω 1MΩ Signal line Level conversion circuit (2-phase input) (3) HST VDD 250Ω Input 1MΩ 250Ω Level conversion circuit (singlephase input) (4) VCK1, VCK2 VDD 2.5kΩ VCK1 1kΩ VCK2 1MΩ 1kΩ 1MΩ 2.5kΩ Level conversion circuit (2-phase input) (5) RGT, VST, CLR, EN VDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (singlephase input) (6) COM Input 1MΩ LC –4– LCX005BK Level Conversion Circuit The LCX005BK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit voltage is stepped up to VDD inside the panel. This level conversion circuit meets the specifications of a 3.0V to 5.0V power supply of the externally-driven IC. Output voltage (inside panel) 1. I/O characteristics of level conversion circuit (For a single-phase input unit) An example of the I/O voltage characteristics of a level conversion circuit is shown in the figure to the right. The input voltage value that becomes half the output voltage (after voltage conversion) is defined as Vth. The Vth value varies depending on the VDD voltage. The Vth values under standard conditions are indicated in the table below. (HST, VST, EN, CLR, and RGT in the case of a single-phase input) VDD Example of single-phase I/O characteristics VDD 2 Vth Input voltage [V] VDD = 13.5V Item Vth voltage of circuit Symbol Vth Min. 0.4 Typ. 1.50 Max. 2.75 Unit V Output voltage (inside panel) (For a differential input unit) An example of I/O voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. Although the characteristics, including those of the Vth voltage, are basically the same as those for a single-phased input, the twophased input phase is defined. (Refer to clock timing conditions.) VDD Example of differential I/O characteristics VDD 2 Vth 2. Current characteristics at the input pin of level conversion circuit A slight pull-in current is generated at the input pin of the level conversion circuit. (The equivalent circuit is shown to the right.) The current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (Refer to electrical characteristics.) 0 0 Input pin voltage [V] 10 Input voltage [V] VDD output Input pin current Max. value HCK1 input HCK2 input Pull-in current characteristics at the input pin Level conversion equivalent circuit –5– LCX005BK Input Signals 1. Input signal voltage conditions (VSS = 0V) Item H driver input voltage (HST, HCK1, HCK2, RGT) V driver input voltage (VST, VCK1, VCK2, CLR, EN) Video signal center voltage Video signal input range∗1 Common voltage of panel (Low) (High) (Low) (High) Symbol VHIL VHIH VVIL VVIH VVC Vsig VCOM Min. –0.35 2.8 –0.35 2.8 5.8 VVC – 4.5 Typ. 0.0 5.0 0.0 5.0 6.0 Max. +0.35 5.5 +0.35 5.5 6.2 VVC + 4.5 Unit V V V V V V V VVC – 0.55 VVC – 0.40 VVC – 0.25 ∗1 Video input signal shall be symmetrical to VVC. 2. Clock timing conditions (Ta = 25°C, Input voltage = 5.0V) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn∗2 rise time HCK Hckn∗2 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time CLR Clr fall time Clr pulse width Clr fall to Hst rise time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time Vckn∗2 rise time VCK Vckn∗2 fall time Vck1 fall to Vck2 rise time Vck1 rise to Vck2 fall time En rise time EN En fall time Vck2 rise to En fall time Vck1 rise to En rise time Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr twClr toHst trVst tfVst tdVst thVst trVckn tfVckn to1Vck to2Vck trEn tfEn tdVck2 tdVck1 –100 –100 0 0 –100 –100 0 0 –50 –50 32 –32 3400 1100 3500 1200 –15 –15 0 0 –170 –455 135 –135 Min. Typ. Max. 100 100 170 –50 100 100 15 15 100 100 3600 1300 100 100 50 –20 100 100 100 100 100 100 100 100 ns µs ns Unit ∗2 Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 1.84MHz, fVckn = 7.865kHz) –6– LCX005BK Item Hst rise time Hst fall time HST Symbol trHst HST 10% trHst ∗3 50% HST HCK1 50% 50% Waveform 90% 90% 10% tfHst 50% Conditions HCKn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst Hst data set-up time tdHst Hst data hold time thHst tdHst thHst 90% 10% HCKn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn∗2 rise time Hckn∗2 fall time HCK trHckn 90% ∗2 HCKn 10% tfHckn ∗3 trHckn tfHckn HCKn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 135ns thHst = –135ns Hck1 fall to Hck2 rise time 50% 50% to1Hck HCK1 50% 50% tdHst = 135ns thHst = –135ns Hck1 rise to Hck2 fall time to2Hck HCK2 to2Hck to1Hck 90% CLR 10% 10% trClr tfClr 90% Clr rise time trClr Clr fall time CLR Clr pulse width tfClr HCKn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns twClr HST 50% CLR 50% twClr 50% toHst Clr fall to Hst rise time toHst HCKn∗2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns –7– LCX005BK Item Vst rise time Vst fall time VST Symbol trVst VST 10% trVst ∗3 50% VST 50% 50% Waveform 90% 90% 10% tfVst 50% Conditions VCKn∗2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns tfVst Vst data set-up time tdVst Vst data hold time thVst VCK1 tdVst thVst 90% 10% VCKn∗2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns Vckn∗2 rise time Vckn∗2 fall time VCK trVckn VCKn 90% 10% tfVckn ∗3 trVckn tfVckn VCKn∗2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32µs thVst = –32µs Vck1 fall to Vck2 rise time 50% 50% to1Vck VCK1 50% 50% tdVst = 32µs thVst = –32µs Vck1 rise to Vck2 fall time to2Vck VCK2 to2Vck to1Vck En rise time trEn EN 90% 10% 10% 90% En fall time EN Vck1 rise to En rise time Vck2 rise to En fall time ∗3 Definitions: tfEn ∗3 tfEn trEn VCKn∗2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVck1 VCK1 50% 50% 50% 50% tdVck2 EN tdVck2 tdVck1 VCKn∗2 duty cycle 50% to1Vck = 0ns to2Vck = 0ns The right-pointing arrow ( The left-pointing arrow ( The black dot at an arrow ( ) means +. ) means –. ) indicates the start of measurement. –8– LCX005BK Electrical Characteristics 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Symbol CHckn CHst IHck1 IHck2 IHst IRgt Csig –200 –500 –300 –100 Min. (Ta = 25°C, VDD = 13.5V, Input voltage = 5.0V) Typ. 5 5 –60 –260 –100 –15 30 45 Max. 10 10 Unit pF pF µA µA µA µA pF HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition 2. Vertical drivers Item Input pin capacitance VCKn VST Input pin current VCK1 VCK2 VST EN CLR Symbol CVckn CVst IVck1 IVck2 IVst IEn IClr –100 –400 –100 Min. Typ. 5 5 –30 –200 –15 Max. 10 10 Unit pF pF µA µA µA VCK1 = GND VCK2 = GND VST, EN, CLR = GND Condition 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) Symbol PWR Min. Typ. 35 Max. 55 Unit mW 4. VCOM input resistance Item VCOM – Vss input resistance Symbol Rcom Min. 0.5 Typ. 1 Max. Unit MΩ –9– LCX005BK Electro-optical Characteristics Item Contrast ratio Optical transmittance R X Y Chromaticity G X Y B X Y V90 V-T characteristics 25°C 60°C V50 25°C 60°C V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time 25°C 60°C R vs. G B vs. G 0°C 25°C 0°C 25°C 60°C 60 min. 25°C 60°C Symbol CR25 CR60 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT60 7 8 6 5 4 3 2 Measurement method 1 Min 80 80 2.6 0.560 0.300 0.275 0.541 0.120 0.040 1.1 1.0 1.5 1.4 2.2 2.1 — — — — — — — — (Ta = 25°C, NTSC mode) Typ. 270 270 3.4 0.630 0.345 0.310 0.595 0.148 0.088 1.6 1.5 2.0 1.8 2.5 2.4 –0.10 0.10 30 8 65 20 — — Max. — — — 0.670 0.390 0.347 0.650 0.187 0.122 2.2 2.1 2.5 2.4 3.2 3.1 –0.25 0.45 100 40 150 60 –40 20 dB s ms V V CIE standards % Unit — – 10 – LCX005BK Basic measurement conditions (1) Driving voltage VDD = 13.5V VVC = 6.0V, VCOM = 5.6V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of screen unless otherwise specified. (4) Measurement systems Two types of measurement system are used as shown below. (5) RGB input signal voltage (Vsig) Vsig = 6 ± VAC (V) (VAC: signal amplitude) ∗ Measurement system I 3.5mm Back Light Luminance Meter Measurement Equipment LCD panel Back light: color temperature 6500K, +0.004uV (25°C) ∗ Back light spectrum (reference) is listed on another page. ∗ Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ...(1) L (Black) L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.5V. Both luminosities are measured by System I. – 11 – LCX005BK 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) × 100 [%] ...(2) Luminance of Back Light L (White) is the same expression as defined in the "Contrast Ratio" section. 3. Chromaticity Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses Chromaticity of x and y on the CIE standards here. Signal amplitudes (VAC) supplied to each input R input R Raster G B 0.5 4.5 4.5 G input 4.5 0.5 4.5 B input 4.5 4.5 0.5 (Unit : V) 4. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (Transmittance at VAC = 0.5V is 100%.) Transmittance [%] 90 50 10 V90 V50 V10 5. Half Tone Color Reproduction Range Half tone color reproduction range of the LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G, B raster modes which correspond to 50% of transmittance, V50R, V50G and V50B respectively. V50RG and V50BG, the voltage differences between V50R and V50G, V50B and V50G, are simply given by the following formulas (3) and (4) respectively. V50RG = V50R – V50G ...(3) V50BG = V50B – V50G ...(4) VAC – Signal amplitude [V] 100 V50RG V50BG Transmittance [%] 50 R raster G raster B raster 0 V50R V50B V50G VAC – Signal amplitude [V] – 12 – LCX005BK 6. Response Time Response time ton and toff are defined by the formulas (5) and (6) respectively. 4.5V Input signal voltage (waveform applied to the measured pixels) ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 0.5V 6V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20log AC { DC component }...(7) component ∗ R, G, B input signal condition for gray raster mode is given by Vsig = 6 ± V50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 8. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 6 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 6 ± 4.5 or 6 ± 2.0 (V) (shown in the right figure) VCOM = 5.6V Black level 4.5V 2.0V 6V 2.0V 4.5V White level 0V Vsig waveform – 13 – LCX005BK Example of Back Light Spectrum (Reference) 0.4 0.3 0.2 0.1 0 400 500 600 Wavelength 380 – 780 [nm] 700 – 14 – LCX005BK Description of Operation 1. Color Coding Color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW Green is not connected for only final stage. G B R G B R G B R G B R G B R G B R B R G B R G B R G B R G B R G B R G G B R G B R G B R G B R G B R G B R B R G B R G B R G B R G B R G B R G 218 2 G B R G B R G B R G B R G B R G B R 2 B R G B R G B R Active area G B R G B R G B R G G B R G B R G B R G B R G B R G B R B R G B R G B R G B R G B R G B R G G B R G B R G B R G B R G B R G B R B R G B R G B R Photo-shielding G B R G B R G B R G 3 521 537 13 – 15 – 222 LCX005BK 2. LCD Panel Operations • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the gate lines from the top to bottom of the panel. • The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by controlling the enable and VCK1, VCK2 pins. The enable pin should be High when not in use. • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period. • Scanning direction of horizontal shift register can be switched with RGT pin. Scanning direction is left to right for RGT pin at High level; and right to left for RGT pin at Low level. (These scanning directions are from a front view.) Normally, set to High level. • Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 218 × 521 dots to display a picture in a single vertical scanning period. • Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is required to apply video signal to the panel. • The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While maintaining the CLR at High level, the VDD potential of gate output inverter drops to approximately 8.5V. This pin shall be grounded when not in use. • The video signal shall be input with polarity-inverted system in every horizontal cycle. • Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle are shown below: (1) Vertical display cycle VD VST VCK1 VCK2 ∗ VST is sampled at first for VCK2. 1 Vertical display cycle 218H (13.84ms) 2 217 218 (2) Horizontal display cycle (right scan) BLK HST 175 HCK1 1 2 3 4 5 174 HCK2 Horizontal display cycle (47.3µs) ∗ HST is sampled at first for HCK1. The horizontal display cycle consists of 521/3 = 174 clock pulses because of RGB simultaneous sampling. ∗ Refer to Description of Operation "3. RGB Simultaneous Sampling." – 16 – LCX005BK 3. RGB Simultaneous Sampling Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R, G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block diagrams are as follows. The LCX005BK has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between B and G signals. (1) Sample and hold (right scan) B S/H CKB S/H CKG S/H CKR S/H CKG S/H CKG AC Amp 4 BLUE R AC Amp 3 RED G AC Amp 2 GREEN (right scan) HCKn CKB CKR CKG (2) Delay circuit (right scan) B Delay Delay AC Amp 4 BLUE R Delay AC Amp 3 RED G AC Amp 2 GREEN – 17 – LCX005BK LCX005BK LCX005BK Example of Color Filter Spectrum (Reference) 100 Color Filter Spectrum R 80 G B 60 Transmittance [%] 40 20 0 400 500 Wavelength [nm] 600 700 – 18 – LCX005BK Color Display System Block Diagram (1) An example of single-chip display system is shown below. +12V +5V +13.5V RED Composite video GREEN Y/C BLUE Y/color difference VCOM LCD panel NTSC/PAL LCX005BK HST HCK1 HCK2 VST VCK1 VCK2 EN CLR CXA1854R (Refer to CXD1845R data sheet.) RGT – 19 – LCX005BK Color Display System Block Diagram (2) An example of dual-chip display system is shown below. +12V +5V +13.5V RED Composite video Decoder/Driver CXA1785AR GREEN Y/C BLUE Y/color difference SYNC FRP +5V VCOM LCD panel NTSC/PAL LCX005BK HST HCK1 HCK2 VST TG CXD2411R VCK1 VCK2 EN CLR (Refer to CXD2411R data sheet.) RGT – 20 – LCX005BK Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. – 21 – LCX005BK Package Outline Unit: mm 14.0 ± 0.3 8.5 ± 0.05 Thickness of the connector 0.3 ± 0.05 4 1.2 ± 0.3 1 S-C K1 4-R 1.0 5 3 25.5 ± 0.8 34.8 ± 0.8 6 17.8 ± 0.15 Active Area Incident light Active Area 6 7.7 ± 0.25 2 (11.2) 9.0 ± 0.25 18.0 ± 0.15 (8.3) 2.7 ± 0.15 No × 15 = 7.5 ± 0.03 Description FPC Molding material Outside frame Reinforcing board P 0.5 ± 0.02 1 0.5 ± 0.15 3.0 ± 0.3 4.0 ± 0.5 + 0.04 0.35 – 0.03 0.5 ± 0.1 2 3 4 PIN 1 PIN 16 5 Reinforcing material 6 Polarizing film weight 1.3g electrode (enlarged) – 22 –