LCX007BNB

LCX007BNB 3.4cm (1.35-inch) Black-and-White LCD Panel For the availability of this product, please contact the sales office. Description The LCX007BNB is a 3.4cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel, with polarizers on the both faces, displays black-and-white images suitable to videophotographic printers and other applications. This panel provides a wide aspect ratio of 16 : 9, such as those represented in HD. The built-in sideblack function also allows an aspect ratio of 4 : 3 in the NTSC/PAL mode. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing system and control signals. Features • The number of active dots: 512,880 (1.35-inch; 3.4cm in diagonal) • Horizontal resolution: 600 TV lines • High optical transmittance: 16.5% (typ.) • High contrast ratio with normally white mode: 190 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) • NTSC/NTSC-WIDE/HD (band: 20MHz) mode selectable (PAL/PAL-WIDE mode also available through conversion of scanned dot numbers by an external IC) • Up/down and/or right/left inverse display function • Side-black function • 16 : 9 and 4 : 3 aspect-ratio switching function Element Structure • Dots 16 : 9 display 4 : 3 display : 1068.5 (H) × 480 (V) = 512,880 : 799.5 (H) × 480 (V) = 383,760 • Built-in peripheral driver using polycrystalline silicon super thin film transistors. Applications Video-photographic printers etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95816A68-PS Block Diagram 1 Up/Down or Right/Left Inversion 4 : 3/16 : 9 Control Circuit SID HST HCK1 HCK2 WID 6 7 8 10 V Shift Register (Bidirectional Scanning) 11 Input Signal Level Shifter Side Black Control Circuit RGT 16 14 15 17 VST VCK PCG DWN 13 H Shift Register (Bidirectional Scanning) –2– COM Pad ENB 12 5 18 9 2 3 4 CLR HVDD VVDD VSS SIG1 (G) SIG2 (R) SIG3 (B) 19 V Shift Register (Bidirectional Scanning) COM LCX007BNB LCX007BNB Absolute Maximum Ratings (VSS = 0V) • H driver supply voltage HVDD • V driver supply voltage VVDD • Common pad voltage COM • H shift register input pin voltage HST, HCK1, HCK2 RGT, WID • V shift register input pin voltage VST, VCK, PCG CLR, ENB, DWN • Video signal input pin voltage SIG1, SIG2, SIG3, SID • Operating temperature Topr • Storage temperature Tstg –1.0 to +20 –1.0 to +20 –1.0 to +17 –1.0 to +17 –1.0 to +17 –1.0 to +15 –10 to +70 –30 to +85 V V V V V V °C °C Operating Conditions (VSS = 0V) Supply voltage HVDD 15.7 +0.3 V –0.4 +0.3 VVDD 15.7 –0.4 V Input pulse voltage (Vp-p of all input pins except video signal and side black signal input pins) Vin 5.0 ± 0.5 V Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol SID SIG1 (G) SIG2 (R) SIG3 (B) HVDD WID RGT HST Vss HCK1 Description Side black signal for 4:3 display Video signal (G∗1) to panel Video signal (R∗1) to panel Video signal (B∗1) to panel Power supply for H driver Aspect-ratio switching (H: 16:9, L: 4:3) Drive direction pulse for H shift register (H: normal, L: reverse) Start pulse for H shift register drive GND (H, V drivers) Clock pulse for H shift register drive Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol HCK2 CLR ENB VCK PCG VST DWN VVDD COM TEST Description Clock pulse for H shift register drive Improvement pulse (1) for uniformity Enable pulse for gate selection Clock pulse for V shift register drive Improvement pulse (2) for uniformity Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Power supply for V driver Common voltage of panel Test; Open ∗1 (R), (G) and (B) are indicated for convenience to show the correspondence with the dot arrangement diagram. –3– LCX007BNB Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) SIG1, SIG2, SIG3, SID HVDD Input 1MΩ (2) HCK1, HCK2 HVDD 250Ω Input 250Ω 250Ω 250Ω 1MΩ 1MΩ HVDD 2.5kΩ Input 1MΩ 2.5kΩ Signal line Level conversion circuit (2-phase input) (3) RGT, WID Level conversion circuit (single-phase input) (4) HST HVDD 250Ω Input 250Ω Level conversion circuit (single-phase input) 1MΩ (5) PCG, VCK VVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (6) VST, CLR, ENB, DWN VVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (7) COM VVDD Input 1MΩ LC –4– LCX007BNB Input Signals 1. Input signal voltage conditions (VSS = 0V) Item H driver input voltage WID, RGT, HST, HCK1, HCK2 Symbol (Low) VHIL (High) VHIH Min. –0.5 4.5 –0.5 4.5 6.5 VVC – 4.5 VVC – 0.5 Typ. 0.0 5.0 0.0 5.0 7.0 — VVC – 0.4 Max. 0.3 5.5 0.3 5.5 7.2 VVC + 4.5 VVC – 0.3 Unit V V V V V V V (Low) VVIL V driver input voltage CLR, ENB, VCK, PCG, VST, DWN (High) VVIH Video signal center voltage Video signal input range∗1 Common voltage of panel∗2 VVC Vsig Vcom ∗1 Video input signal shall be symmetrical to VVC. ∗2 Common voltage of the panel shall be adjusted to VVC – 0.4V. Level Conversion Circuit The LCX007BNB has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V. –5– LCX007BNB 2. Clock timing conditions (Ta = 25°C) (fHCKn = 7.5MHz, fVCK = 15.7kHz) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn∗3 rise time HCK Hckn∗3 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time CLR Clr fall time Clr pulse width Vck rise/fall to Clr fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time Enb rise time ENB Enb fall time Vck rise/fall to Enb rise time Enb pulse width Pcg rise time Pcg fall time PCG Pcg fall to Vck rise/fall time Pcg pulse width ∗3 Hckn means Hck1 and Hck2. Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr twClr tdClr trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb twEnb trPcg tfPcg toVck twPcg Min. — — 20 –40 — — –15 –15 — — 3000 –50 — — –25 5 — — — — 350 3450 — — 650 1150 Typ. — — 67 0 — — 0 0 — — 3100 0 — — 15 15 — — — — 400 3500 — — 700 1200 Max. 30 30 100 40 30 30 15 15 100 100 3200 50 100 100 25 25 100 100 100 100 450 3550 20 20 750 1250 ns µs ns Unit –6– LCX007BNB Item Hst rise time Hst fall time HST Symbol trHst Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions O Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst ∗4 Hst data set-up time tdHst 50% Hst Hck1 50% 50% 50% Hst data hold time thHst tdHst thHst 90% 10% O Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn∗3 rise time Hckn∗3 fall time HCK trHckn 90% ∗3 Hckn 10% tfHckn ∗4 to1Hck Hck1 trHckn tfHckn O Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hck1 fall to Hck2 rise time 50% 50% 50% 50% Hck1 rise to Hck2 fall time to2Hck Hck2 to2Hck 90% Clr 10% 10% tfClr to1Hck 90% Clr rise time trClr Clr fall time CLR Clr pulse width tfClr trClr O Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns twClr Vck 50% Vck rise/fall to Clr fall time Clr 50% twClr 50% tdClr tdClr ∗4 –7– LCX007BNB Item Vst rise time Vst fall time VST Symbol trVst Vst 10% trVst 10% tfVst Waveform 90% 90% Conditions tfVst ∗4 Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst 90% Vck 10% thVst 90% 10% Vck rise time VCK Vck fall time trVck tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time ENB tfEnb tfEn trEn Vck rise/fall to Enb rise tdEnb time Vck 50% Enb 50% twEnb 50% Enb pulse width twEnb tdEnb ∗4 Pcg rise time Pcg fall time PCG trPcg Vck 50% tfPcg Pcg 50% 50% twPcg toVck Pcg fall to Vck rise/fall toVck time Pcg pulse width twPcg ∗4 ∗4 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. –8– LCX007BNB Electrical Characteristics (Ta = 25°C, HVDD = 15.7V, VVDD = 15.7V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST WID, RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. — — –500 –1000 –500 –150 — — Typ. 7 7 –120 –450 –160 –30 250 7.5 Max. 10 10 — — — — — 10 Unit pF pF µA µA µA µA pF mA HCKn: HCK1, HCK2 (7.5MHz) HCK1 = GND HCK2 = GND HST = GND WID, RGT = GND Condition 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK Symbol CVck CVst Min. — — –1000 –150 IV — Typ. 7 7 –160 –30 1.5 Max. 10 10 — — 4 Unit pF pF µA µA mA VCK = GND PCG, VST, EN, CLR, DWN = GND VCK: (15.7kHz) Condition PCG, VST, EN, CLR, DWN Current consumption 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) 4. Pin input resistance Item Pin-VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. — Unit MΩ Symbol PWR Min. — Typ. 150 Max. 250 Unit mW 5. Side signal input pin capacitance Item Side signal input pin capacitance Symbol CSIDon Min. 8 Typ. 10 Max. 12 Unit nF –9– LCX007BNB Electro-optical Characteristics Item Contrast ratio Optical transmittance 60°C 60°C Symbol CR60 T RV90-25 25°C V90 60°C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25°C V-T characteristics V50 60°C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25°C V10 60°C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0°C 25°C 0°C 25°C 60°C 25°C 25°C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 Measurement method 1 2 Min. 130 14.0 1.2 1.4 1.7 1.1 1.2 1.4 1.7 1.8 2.0 1.5 1.6 1.8 2.3 2.4 2.6 2.1 2.2 2.4 — — — — — — — (Ta = 25°C, NTSC mode) Typ. 190 16.5 1.5 1.7 2.0 1.4 1.5 1.7 2.0 2.1 2.3 1.8 1.9 2.1 2.6 2.7 2.9 2.4 2.5 2.7 50 15 52 16 — — — Max. — — 1.8 2.0 2.3 1.7 1.8 2.0 2.3 2.4 2.6 2.1 2.2 2.4 2.9 3.0 3.2 2.7 2.8 3.0 100 40 150 60 –30 0 5 dB s % ms V Unit — % – 10 – LCX007BNB Basic measurement conditions (1) Driving voltage HVDD = 15.7V, VVDD = 15.7V VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of screen unless otherwise specified. (4) Measurement systems Two types of measurement system are used as shown below. (5) Video input signal voltage (Vsig) Vsig = 7.0 ± VAC [V] (VAC: signal amplitude) ∗ Measurement system I Back Light Luminance Meter 3.5mm LCD panel Measurement Equipment Back light: color temperature 6500 ± 700K (25°C) Polarizer: POLATECHNO Co., Ltd. THC-13U (Luminance meter side) ∗ Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). L (White) ... (1) L (Black) CR = L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.5V. Both luminosities are measured by System I. – 11 – LCX007BNB 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) × 100 [%] ... (2) Luminance of Back Light L (White) is the same expression as defined in the 'Contrast Ratio' section. 3. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. Transmittance [%] 90 50 10 V90 V50 V10 VAC – Signal amplitude [V] 4. Response Time Response time 'ton' and 'toff' are defined by the formula (5) and (6) respectively. 4.5V Input signal voltage (waveform applied to the measured pixels) 0.5V ton = t1 – tON ... (5) toff = t2 – tOFF ... (6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 7.0V 0V Light transmission output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff – 12 – LCX007BNB 5. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗1 mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20 log AC component { DC component } ... (7) ∗1 Each input signal condition for gray raster mode is given by Vsig = 7.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 6. Image Retention Time Image Retention time is given by following procedures. Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Hold VAC that maximizes image retention judging by sight. Measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 7.0 ± 4.5 or ± 2.0 [V] (shown in the right figure) Vcom = 6.6V 4.5V 2.0V 7.0V 2.0V 4.5V Black level White level 0V Vsig waveform 7. Cross talk Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i = 1 to 4) around black window (Vsig = 4.5V/1V). W1 W2 W2' W1' W4 W4' Cross talk CTK = Wi' – Wi Wi × 100 [%] W3 W3' – 13 – LCX007BNB Viewing angle characteristics 90 CR = 5 10 Phi 20 50 100 150 180 10 30 50 70 Theta 0 200 270 θ0° Z Marking θ φ90° φ180° φ Y φ0° X φ270° Measurment method – 14 – LCX007BNB Optical transmittance of LCD panel (Typical Value) 20 15 Trans. [%] 10 5 0 400 500 600 Wavelength [nm] 700 Measurement method: Measurement system II – 15 – Description of Operation 1. Dot Arrangement (1) (16:9 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively. ODD = 1094 dots EVEN = 1095 dots ODD = 1069 dots EVEN = 1068 dots (Effective 29.918mm) 2 356 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW ODD = 13 dots EVEN = 14 dots ODD = 13 dots EVEN = 13 dots DL1 DL2 DL3 DL4 1 357 DR1 DR2 DR3 DR4 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGB RG B RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB 3 dots RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR 480 dots (Effective 16.800mm) 3 dots – 16 – RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RG B RGB RGB RGB RG B RGB RGB RGB RG B RGB RGB RGB RG B RGB RGB RGB RG B RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RG B RG B RGB RGB RG B RGB RGB RGB 1 2 RG B RG B R G B RG B R GB RG B RG B RG B RG B RG B RG B RG B R G B RG B R G B RG B R G B R G B R G B R G B RG B R G B RG B GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB 3 RGB RGBRGB RGB RGB 4 GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RG B RG B R G B RG B R GB RG B RG B RG B RG B RG B RG B RG B R G B RG B R G B RG B R G B R G B R G B R G B RG B R G B RG B GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGB RGB 479 480 RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGB RGB RGB LCX007BNB Dot Arrangement (2) (4:3 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively. ODD = 1094 dots EVEN = 1095 dots ODD = 135 dots EVEN = 134 dots Side Black 2 44 45 46 47 48 311 312 313 314 356 4 : 3 Area Side Black 357 DR1 DR2 DR3 DR4 GATE SW ODD = 13 dots EVEN = 14 dots ODD = 799 dots EVEN = 800 dots (Effective 22.386mm) ODD = 135 dots EVEN = 134 dots ODD = 13 dots EVEN = 13 dots DL1 DL2 DL3 DL4 1 GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGB RGB RGBRGB RGB 3 dots RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR 480 dots (Effective 16.800mm) 3 dots – 17 – RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB RGB 1 2 RGB RGB RGB R GB RGB RGB RGB RGB RGB RGB R GB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGBRGB RGB RGB RGBRGB RGB RGB RGBRGB RGB RGB RGBRGB RGB 3 RGB RGBRGBRGBRGB RGB RGB 4 GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB R GB RGB RGB RGB RGB RGB RGB R GB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGBRGB RGBRGB RGB RGBRGB RGB RGB RGB RGB RGB RGBRGB RGB RGB RGBRGB RGB RGB RGBRGB RGB 479 480 RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGBRGBRGBRGB RGB RGB LCX007BNB LCX007BNB 2. LCD Panel Operations [Description of basic operations] The basic operations of the LCD panel are shown below based on the wide-display mode. • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 480 gate lines sequentially in every horizontal scanning period. • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period. • Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 480 × 1068.5 dots to display a picture in a single vertical scanning period. • The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold (S/H) pulses follow the same 1.5-bit offset scheme. • The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be grounded when not in use. • The video signal shall be input with polarity-inverted system in every horizontal cycle. • Timing diagrams of the vertical and the horizontal display cycle are shown below: (1) Vertical display cycle VD VST VCK 1 2 Vertical display cycle 480H 480 (2) Horizontal display cycle (16:9) BLK HST 356 HCK1 1 2 3 4 5 6 357 HCK2 Horizontal display cycle (3) Horizontal display cycle (4:3) BLK HST 267 HCK1 1 2 3 4 5 6 268 HCK2 Horizontal display cycle – 18 – LCX007BNB [Description of operating mode] The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. • Right/left inverse mode • Up/down inverse mode • 4:3 display mode with side-black display These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below: WID RGT H H L L H L H L Mode 16:9 right scan 16:9 left scan 4:3 right scan 4:3 left scan DWN H L Mode Down scan Up scan The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin block upside. • The analog signal (SID) to display side-black shall be input by 1H inversion synchronized with the signal. 3. 3-dot Simultaneous Sampling Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. The block diagram of the delaying procedure using sample-and-hold method is as follows. The LCX007 has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between SIG2 and SIG3 signals. SIG2 S/H CK2 S/H CK3 S/H CK1 S/H CK3 S/H CK3 AC Amp 3 SIG2 SIG1 AC Amp 2 SIG1 SIG3 AC Amp 4 SIG3 (right scan) HCKn CK2 CK1 CK3 – 19 – LCX007BNB LCX007BNB Display System Block Diagram An example of display system is shown below. SIG2 ∗ SIG1 ∗ SID SIG2 RGB Driver CXA1819Q SIG1 SIG3 COM SIG3 ∗ ∗ The SIG1, 2, 3 and H SYNC signals with double-speed processing shall be applied to those pins in the NTSC/PAL modes. FRP SH HST HCK1 HSYNC ∗ VSYNC TG CXD2412AQ VST VCK PCG ENB CLR HCK2 LCD Panel LCX007BNB WID RGT DWN – 20 – LCX007BNB Reliability test conditions Items High temperature operation High temperature storage High temperature & high humidity storage Temperature cycle Vibration Test conditions Ta = 70°C HVDD = 15.7V VVDD = 15.7V Ta = 85°C Ta = 40°C 95% RH Ta = –30 to +85°C X, Y, Z, 1.5mm 10 to 55Hz (1min. reciprocation) 250h 250h 250h 10cy 20min. for each direction Panel appearance and performance after those tests must conform with the standards. Time Anti-electrostatic discharge test results Conditions: C = 200pF, Rs = 0Ω Result: Breakdown voltage + – Up to 100V – – 101 to 200V – Pin 8 Pins except pin no.8 have the strength more than 200V. – 21 – LCX007BNB Important (1) Direction of incident light Allow incident light to hit upon an opposite side of a mark-indicated surface. Direction of incidence Marking side (2) Polarizer This LCD is attached with a polarizer. A suitable heat-dissipation method shall be incorporated to suppress optical degradation of a polarizer. (3) Light source • Use visible light (wavelength λ = 400 to 780nm) as a light source. Do not use a light source containing infrared or ultraviolet components. • Suppress leakage light (reflection light) into a backside of a panel to sufficiently weak level or shut it out completely. – 22 – LCX007BNB Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Handle in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. g) Minimum bent radius rating for flexible substrates is 1mm. h) Panel screw torque should not exceed 3kg · cm. – 23 – LCX007BNB Package Outline Unit: mm Except cover 3.4 ± 0.1 Thickness of the connector 0.3 ± 0.05 21.0 ± 0.15 9.75 ± 1.5 1.8 ± 0.1 31.4 ± 0.2 4.55 ± 0.1 4 1 2-R 0.5 (42.5) (40.5) 3 76.5 ± 1.3 2-φ3.5 5 2 6 Incident light 6 30.75 ± 0.2 34.0 ± 0.2 36.0 ± 0.15 Active Area Polarizing Axis 13.6 ± 0.25 0 φ2.5 – 0.1 (16.8) 7 (29.9) 20.25 ± 0.25 40.5 ± 0.15 1.5 ± 0.15 No 1 0.5 ± 0.15 4.0 ± 0.3 Description FPC Molding material Outside frame Reinforcing board P 1.0 × 19 = 19.0 ± 0.1 0.6 ± 0.05 1.0 ± 0.15 2 3 4 PIN1 PIN20 5 Reinforcing material 6 electrode (enlarged) The rotation angle of the active area relative to H and V is ± 1°. 7 Polarizing film Cover weight 7g – 24 – 2.0 ± 0.1