LCX012BL

LCX012BL 3.3cm (1.3-inch) Black-and-White LCD Panel Description The LCX012BL is a 3.3cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. Use of three panels in combination with the LCX012BL provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines. The adoption of advanced on-chip black matrix realizes high picture quality without cross talk by incorporating high luminance screen and cross talk free circuit. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals. Using Sony’s timing generator “CXD2442Q” sends timing signal necessary for LCD panel drive by identificating computer supporting VGA automatically, and supports double-speed processed NTSC/PAL. Features • The number of active dots: 312,000 (1.3-inch; 3.3cm in diagonal) • Accepts the computer requirements of VGA platform (640 x 480) • High optical transmittance: 25% (typ.) • Supports NTSC/PAL by processing the video signal at double speed • Built-in cross talk free circuit • High contrast ratio with normally white mode: 250 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) • Up/down and/or right/left inverse display function Element Structure • Dots: 644 (H) × 484 (V) = 311,696 • Built-in peripheral driver using polycrystalline silicon super thin film transistors. Applications • Liquid crystal data projectors • Liquid crystal projectors, etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96512-ST Block Diagram 1 2 NC PSIG HST HCK1 HCK2 Up/Down or Right/Left Inversion 11 12 V Shift Register (Bidrectional Scanning) 13 17 Input Signal Level Shifter Uniformity Improvement Signal Control Circuit NC 10 19 18 21 20 RGT VST VCK PCG DWN 16 H Shift Register (Bidrectional Scanning) –2– COM PAD ENB 15 9 22 14 8 7 6 5 4 CLR HVDD VVDD Vss SIG1 SIG2 SIG3 SIG4 V Shift Register (Bidrectional Scanning) SIG5 SIG6 3 23 COM LCX012BL LCX012BL Absolute Maximum Ratings (VSS = 0V) • H driver supply voltage HVDD • V driver supply voltage VVDD • Common pad voltage COM • H shift register input pin voltage HST, HCK1, HCK2, RGT • V shift register input pin voltage VST, VCK, PCG, CLR, ENB, DWN • Video signal input pin voltage SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG • Operating temperature Topr • Storage temperature Tstg –1.0 to +20 –1.0 to +20 –1.0 to +17 –1.0 to +17 –1.0 to +17 –1.0 to +15 –10 to +70 –30 to +85 V V V V V V °C °C Operating Conditions (VSS = 0V) Supply voltage HVDD 15.5 ±0.5 V VVDD 15.5 ±0.5 V Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 ±0.5 V Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol NC PSIG SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 HVDD RGT HST HCK1 NC; Open Uniformity improvement signal Video signal 6 to panel Video signal 5 to panel Video signal 4 to panel Video signal 3 to panel Video signal 2 to panel Video signal 1 to panel Power supply for H driver Driver direction pulse for H shift register (H: normal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive Description Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 –3– Symbol HCK2 VSS CLR ENB NC VCK VST DWN PCG VVDD COM TEST Description Clock pulse for H shift register drive GND (H, V drivers) Improvement pulse (1) for uniformity Enable pulse for gate selection NC; Open Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Improvement pulse (2) for uniformity Power supply for V driver Common voltage of panel Test; Open LCX012BL Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to VSS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG HVDD Input 1MΩ (2) HCK1, HCK2 HVDD 250Ω Input 250Ω 1MΩ 250Ω 250Ω 1MΩ Signal line Level conversion circuit (2-phase input) (3) RGT HVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (4) HST HVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (5) PCG, VCK VVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (6) VST, CLR, ENB, DWN VVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (7) COM VVDD Input 1MΩ LC –4– LCX012BL Input Signals 1. Input signal voltage conditions Item H driver input voltage (Low) (High) V driver input voltage (Low) (High) Symbol VHIL VHIH VVIL VVIH Min. –0.5 4.5 –0.5 4.5 6.8 VVC – 4.5 VVC – 0.5 VVC ± 3.3 Typ. 0.0 5.0 0.0 5.0 7.0 7.0 VVC – 0.4 VVC ± 3.5 Max. 0.4 5.5 0.4 5.5 7.2 VVC + 4.5 VVC – 0.3 VVC ± 3.7 (VSS = 0V) Unit V V V V V V V V VVC Video signal center voltage Video signal input range∗1 (SIG1 to 6) Vsig Common voltage of panel∗2 Uniformity improvement signal input voltage (PSIG)∗3 Vcom Vpsig ∗1 input signal shall be symmetrical to VVC. ∗2 The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. ∗3 Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below). Input waveform of uniformity improvement signal PSIG 90% PSIG VVC 10% trPSIG tfPSIG PCG Level Conversion Circuit The LCX012BL has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V. –5– LCX012BL 2. Clock timing conditions Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn rise time∗4 HCK Hckn fall time∗4 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time CLR Clr fall time Vck rise/fall → Clr fall time Clr pulse width Vst rise time Vst fall time VST Vst data set-up time Vst data hold time Vck rise time VCK Vck fall time Enb rise time Enb fall time ENB Vck rise/fall to Enb rise time Enb pulse width Pcg rise time Pcg fall time PCG Pcg rise to Vck rise/fall time Pcg pulse width ∗4 Hckn means Hck1 and Hck2. (Ta = 25°C) (VGA mode: fHCKn = 2.5MHz, fVCK = 15.7kHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr Tdclr twClr trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb toEnb twEnb trPcg tfPcg toVck twPcg Min. — — 30 30 — — –15 –15 — — –100 2400 — — 5 5 — — — — 400 2400 — — 500 900 Typ. — — 100 100 — — 0 0 — — 0 2500 — — 15 15 — — — — 500 2500 — — 800 1000 Max. 30 30 170 170 30 30 15 15 100 100 100 2600 100 100 25 25 100 100 100 100 600 2600 30 30 1000 1100 ns µs ns Unit –6– LCX012BL Item Hst rise time Hst fall time HST Symbol trHst Hst 10% trHst ∗5 Waveform 90% 90% 10% tfHst Conditions O Hckn∗4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst Hst data set-up time tdHst 50% Hst Hck1 50% Hst data hold time thHst tdHst 50% 50% thHst 90% 10% O Hckn∗4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn rise time∗4 Hckn fall time∗4 HCK Hck1 fall to Hck2 rise time trHckn 90% ∗4 Hckn 10% tfHckn trHckn ∗5 50% tfHckn 50% O Hckn∗4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns to1Hck Hck1 50% Hck2 50% Hck1 rise to Hck2 fall time to2Hck to2Hck to1Hck Clr rise time trClr 90% Clr 10% 90% 10% Clr fall time CLR Clr pulse width tfClr trClr tfClr O Hckn∗4 duty cycle 50% to1Hck = 0ns to2Hck = 0ns twClr Vck 50% Clr 50% 50% twClr tdClr Vck rise/fall → Clr fall time tdClr ∗5 ∗5 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. –7– LCX012BL Item Vst rise time Vst fall time Symbol trVst Vst 10% trVst ∗5 Waveform 90% 90% 10% tfVst Conditions tfVst VST Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst thVst Vck rise time VCK Vck fall time trVck Vck 90% 10% 90% 10% tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time tfEnb tfEn trEn ENB Vck rise/fall to Enb rise time Vck 50% tdEnb Enb 50% twEnb to3Vck 50% Enb pulse width twEnb ∗5 tdEnb Pcg rise time trPcg Pcg 90% 10% 90% 10% Pcg fall time PCG tfPcg trPcg tfPcg Pcg rise to Vck rise/fall time toVck Vck toVck 50% 50% 50% twPcg Pcg pulse width twPcg Pcg ∗5 –8– LCX012BL Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. — — –500 Typ. 10 10 –250 Max. Unit 15 15 — — — — 150 6.0 pF pF µA µA µA µA pF mA HCKn: HCK1, HCK2 (2.5MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition –1000 –300 –500 –150 — — –150 –25 100 4.0 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK Symbol CVck CVst Min. — — Typ. 10 10 Max. Unit 15 15 — — 3.0 pF pF µA µA VCK = GND PCG, VST, ENB, CLR, DWN = GND Condition –1000 –150 –150 IV — –25 2.0 PCG, VST, ENB, CLR, DWN Current consumption mA VCK: (15.7kHz) 3. Total power consumption of the panel Item Total power consumption of the panel (VGA) Symbol PWR Min. — Typ. 100 Max. Unit 150 mW 4. Pin input resistance Item Pin – VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. — Unit MΩ 5. Uniformity improvement signal Item Input pin capacitance for uniformity improvement signal Symbol CPSIGon Min. — Typ. 6.5 Max. Unit 7.0 nF –9– LCX012BL Electro-optical Characteristics Item Contrast ratio Optical transmittance 25°C 25°C Symbol CR T RV90-25 25°C V90 60°C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25°C V-T characteristics V50 60°C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25°C V10 60°C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0°C 25°C 0°C 25°C 60°C 25°C 25°C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 Measurement method 1 2 (Ta = 25°C, VGA mode) Min. 150 22 1.1 1.2 1.3 1.0 1.1 1.1 1.5 1.6 1.7 1.5 1.5 1.6 2.0 2.1 2.1 2.1 2.1 2.2 — — — — — — — Typ. 250 25 1.5 1.7 1.8 1.4 1.5 1.6 1.9 2.0 2.1 1.8 1.9 2.0 2.4 2.5 2.5 2.3 2.4 2.5 36 14 106 30 –74 0 — Max. — — 1.8 2.0 2.1 1.7 1.8 1.9 2.2 2.3 2.4 2.1 2.2 2.3 2.7 2.8 2.8 2.6 2.7 2.8 80 40 200 70 –40 0 5 dB s % ms V Unit — % Reflection Preventive Processing When a phase substrate which rotates polarization axis is used to adjust to the polarization direction of polarization screen or prism, use the phase substrate with reflection preventive processed on the surface. This prevents characteristic deterioration caused by luminous reflection. – 10 – LCX012BL Basic measurement conditions (1) Driving voltage HV DD = 15.5V, VVDD = 15.5V VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of screen unless otherwise specified. (4) Measurement systems Two typed of measurement system are used as shown below. (5) Video input signal voltage (Vsig) Vsig = 7.0 ±V AC [V] (VAC: signal amplitude) • Measurement system I approx. 2000mm Screen Luminance Meter LCD Projector Measurement Equipment Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or an equivalent Projection lens: The focal distance 80mm, F1.9 Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500) (× 24, Sensor area: 7mmφ) Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent • Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ... (1) L (Black) L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 4.5V. Both luminosities are measured by System Ι. – 11 – LCX012BL 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= White luminance x 100 [%] ... (2) Luminance of light source "White luminance" means the maximum luminance at the input signal amplitude VAC = 0.5V on Mesurement System II. 3. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V90, V50, and V10 correspond to the each voltage which defines 90%, 50%, and 10% of transmittance respectively. Transmittance [%] 90 50 10 V90 V50 V10 VAC – Signal amplitude [V] 4. Respons Time Response time ton and toff are defined by the formula (5) and (6) respectively. 4.5V Input signal voltage (Waveform applied to the measured pixels) ton = t1 – tON ... (5) toff = t2 – tOFF ... (6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 0.5V 7.0V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff – 12 – LCX012BL 5. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC VGA: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analizer in System II. F [dB] = 20log { AC component } ... (7) DC component ∗ Each input signal condition for gray raster mode is given by Vsig = 7.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 6 Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 7.0 ± 4.5 or ± 2.0 [V] (shown in the right figure) Vcom = 6.6V 4.5V 2.0V 7.0V 2.0V 4.5V Black level White level 0V Vsig waveform 7. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented Wi' and Wi (i = 1 to 4) around black window (Vsig = 4.5V/1V) W1 W2 W2’ W1’ W4 W4’ Cross talk value CTK = Wi' – Wi × 100 [%] Wi W3 W3’ – 13 – LCX012BL Viewing angle characteristics (Typical Value) 90 Phi 0 180 10 30 50 70 Theta 270 θ0° Z θ φ90° Marking φ Y φ180° φ0° X φ270° Measurement method – 14 – LCX012BL Optical transmittance of LCD panel (Typical Value) 30 20 Trans. [%] 10 0 400 500 600 Wavelength [nm] 700 Measurement method: Measurement system II – 15 – LCX012BL 1. Dot Arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW Photo-shielding Active area 484 dots 5 dots 644 dots 5 dots 654 dots 1 dot – 16 – 1 dot 486 dots LCX012BL 2. LCD Panel Operations [Description of basic operations] The basic operations of the LCD panel are shown below based on the VGA mode. • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 484 gate lines sequentially in every horizontal scanning period. Two lines of horizontal electrodes are sequentially selected in NTSC/PAL mode. • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 644 signal electrodes sequentially in a single horizontal scanning period. • Vertical and horizontal shift registers address one pixel, and then Thin film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 484 × 644 dots to display a picture in a single vertical scanning period. • To change the combination of the horizontal electrode in NTSC/PAL mode, the phase of VCK need to be inverted. Normally, switching every field maximizes vertical resolution. • The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be grounded when not in use. • The video signal shall be input with 1H-inverted system. • Timing diagrams of the vertical for VGA mode and NTSC/PAL mode and the horizontal display cycle are shown below: (1) Vertical display cycle (VGA) VD VST (DWN = High level) VST (DWN = Low level) VCK 1 2 Vertical display cycle 480H 480 (2) Horizontal display cycle HD HST 108 HCK1 1 2 3 4 5 6 109 HCK2 Horizontal display cycle – 17 – LCX012BL [Description of operating mode] The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. • Right/left inverse mode • Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The setting mode is shown below. RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin block upside. • To improve uniformity, the analog signals PSIG shall be input by synchronizing with SIG1 to SIG6. • When the up-scan mode (DWN = Low level) is set, the phase of VST shall be inverted 3. 6-dot Simultaneous Sampling and Dot-inverted Drive Horizontal driver samples SIG1 to SIG6 signal simultaneously. Which requires the phase matching between SIG1 to SIG6 signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. The block diagram of the delaying procedure using sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between SIG1 to SIG6 signals. SIG1 SIG2 S/H CK1 S/H CK2 S/H S/H AC Amp 8 7 SIG1 SIG2 LCX012BL AC Amp SIG3 SIG4 S/H CK3 S/H CK4 S/H S/H AC Amp AC Amp AC Amp AC Amp 6 5 4 3 SIG3 SIG4 SIG5 SIG6 SIG5 SIG6 S/H CK5 S/H S/H CK6 (right scan) HCKn CK1 CK2 CK3 CK4 CK5 CK6 – 18 – LCX012BL Display System Block Diagram An example of display system is shown below. Discrete Buff. R G B FRP RGB Driver CXA1853Q S/H CXA2504N LCX012BL R S/H CXA2504N LCX012BL G S/H CXA2504N LCX012BL B HD VD C.SYNC HCK, VCK TG CXD2442Q SH – 19 – LCX012BL Notes on Handling (1) Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionozed air to discharge the panels. (2) Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages. g) Minimum bent radius rating for flexible substrates is 1mm. h) Panel screw torque should not exceed 3kg · cm. – 20 – LCX012BL Package Outline Unit: mm 3.7 ± 0.1 Thickness of the connector 0.3 ± 0.05 25.0 ± 0.15 1.8 ± 0.1 4 1 (62.0) 37.0 ± 0.1 42.0 ± 0.15 104.0 ± 1.4 (20.03) 21.0 ± 0.25 2.5 ± 0.1 2.1 ± 0.05 0.5 ± 0.15 4.0 ± 0.4 The rotation angle of the active area relative to H and V is ± 1°. 2. R 4- 3-φ2.3 ± 0.05 C0.8 3 2 5 6 Incident light Polarizing Axis PIN1 5 Active Area 7 φ2.1 ± 0.05 (26.65) 30.0 ± 0.1 38.0 ± 0.15 19.0 ± 0.25 4.0 ± 0.1 No 1 2 3 4 Description FPC Molding material Outside frame Reinforcing board P 1.0 × 23 = 23.0 ± 0.1 1.0 ± 0.15 0.6 ± 0.05 PIN24 5 Reinforcing material 6 electrode (enlarged) 7 Polarizing film Cover weight 7.5g – 21 –