LCX017DLT

LCX017DLT 4.6cm (1.8 Type) Black-and-White LCD Panel Description The LCX017DLT is a 4.6cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. Use of three LCX017DLT panels provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines. The adoption of DMS (Dual Metal Shield) structure realizes a high luminance screen. And new cross talk free and ghost free structures contribute to high picture quality. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals. The panel contains an active area variable circuit which supports S-XGA 5:4 and PC-98 8:5 data signals by changing the active area according to the type of input signal. Features • Number of active dots: 786,432 (1.8 Type, 4.6cm in diagonal) • Accepts the computer requirements of XGA, SVGA, VGA, NTSC and PAL • Supports SXGA with simple display • High optical transmittance: 23% (typ.) • New high light resistance DMS (Dual Metal Shield) structure adopted • New cross talk free and ghost free structures • High contrast ratio with normally white mode: 350 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) • Up/down and/or right/left inverse display function • Antidust glass used Element Structure • Dots: 1024 (H) × 768 (V) = 786,432 • Built-in peripheral driver using polycrystalline silicon super thin film transistors Applications • Liquid crystal data projectors • Liquid crystal rear-projector TVs, etc. ∗ The company's name and product's name in this data sheet is a trademark or a registered trademark of each company. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00212A15 1 PSIG VSSGL VSSGR HST HCK1 HCK2 BLK RGT VST Block Diagram Up/Down and/or Right/Left Inversion Control Circuit 21 2 17 19 18 Input Signal Level Shifter Circuit V Shift Register (Bidirectional Scanning) Black Frame Control Circuit 22 16 Precharge Control Circuit 25 24 29 26 23 27 28 VCK PCG DWN ENB HB VB 15 H Shift Register (Bidirectional Scanning) Side-Black Control Circuit –2– Black Frame Control Circuit V Shift Register (Bidirectional Scanning) HVDD VVDD Vss 30 20 3 4 5 6 VSIG1 VSIG2 VSIG3 VSIG4 7 COM PAD VSIG5 8 9 10 11 12 13 14 31 VSIG6 VSIG7 VSIG8 VSIG9 VSIG10 VSIG11 VSIG12 COM LCX017DLT LCX017DLT Absolute Maximum Ratings (VSS = 0V) • H driver supply voltage HVDD • V driver supply voltage VVDD • Common pad voltage COM • H shift register input pin voltage HST, HCK1, HCK2, RGT • V shift register input pin voltage VST, VCK, PCG, BLK, ENB, DWN HB, VB • Video signal input pin voltage SIG1 to 12, PSIG • Operating temperature∗ Topr • Storage temperature Tstg ∗ Panel temperature inside the antidust glass –1.0 to +20 –1.0 to +20 –1.0 to +17 –1.0 to +17 –1.0 to +17 V V V V V –1.0 to +15 –10 to +70 –30 to +85 V °C °C Operating Conditions (VSS = 0V) • Supply voltage 13.5 ± 0.5V HVDD VVDD 15.5 ± 0.5V • Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 ± 0.5V –3– LCX017DLT Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol PSIG VSSGR VSIG1 VSIG2 VSIG3 VSIG4 VSIG5 VSIG6 VSIG7 VSIG8 VSIG9 VSIG10 VSIG11 VSIG12 HVDD RGT HST HCK2 HCK1 VSS VSSGL BLK ENB VCK VST DWN HB VB PCG VVDD COM TEST Uniformity improvement signal GND for right V gate Video signal 1 to panel Video signal 2 to panel Video signal 3 to panel Video signal 4 to panel Video signal 5 to panel Video signal 6 to panel Video signal 7 to panel Video signal 8 to panel Video signal 9 to panel Video signal 10 to panel Video signal 11 to panel Video signal 12 to panel Power supply for H driver Drive direction pulse for H shift register (H: nomal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive 2 Clock pulse for H shift register drive 1 GND (H, V drivers) GND for left V gate Input for PC98 mode Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: nomal, L: reverse) Display switch for S-XGA Display switch for PC98 mode Improvement pulse for uniformity Power supply for V driver Common voltage of panel Test pin, leave this pin open Description –4– LCX017DLT Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.) (1) VSIG1 to VSIG12, PSIG HVDD Input 1MΩ (2) HCK1, HCK2 HVDD 250Ω Input 250Ω 1MΩ 250Ω 250Ω 1MΩ Signal line Level conversion circuit (2-phase input) (3) RGT HVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (4) HST Input HVDD 250Ω 250Ω 1MΩ Level conversion circuit (single-phase input) (5) PCG, VCK VVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (6) VST, BLK, ENB, DWN, HB, VB VVDD 2.5kΩ Input 1MΩ ∗ 2.5kΩ Level conversion circuit (single-phase input) ∗ DWN is 400kΩ. (7) COM VVDD Input 1MΩ LC (8) HVDD, VSSGR, VSSGL, VVDD Input 1MΩ are all Vss. –5– LCX017DLT Input Signals 1. Input signal voltage conditions (VSS = 0V) Item H shift register input voltage (Low) HST, HCK1, HCK2, RGT (High) V shift register input voltage (Low) HB, VB, BLK, VST, VCK, PCG, ENB, DWN (High) Video signal center voltage Video signal input range∗1 Common voltage of panel∗2 Uniformity improvement signal input voltage (PSIG)∗3 ∗1 ∗2 Symbol VHIL VHIH VVIL VVIH VVC Vsig Vcom VpsigB VpsigG Min. –0.5 4.5 –0.5 4.5 6.9 VVC – 4.5 VVC – 0.5 VVC ± 4.4 VVC ± 1.8 Typ. 0.0 5.0 0.0 5.0 7.0 7.0 VVC – 0.4 VVC ± 4.5 VVC ± 1.9 Max. 0.4 5.5 0.4 5.5 7.1 VVC + 4.5 VVC – 0.3 VVC ± 4.6 VVC ± 2.0 Unit V V V V V V V V ∗3 Input video signal shall be symmetrical to VVC. The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 450ns (as shown in a diagram below). Input waveform of uniformity improvement signal PSIG 90% PsigB PSIG PsigG VVC 10% trPSIG tfPSIG PCG PRG∗4 ∗4 PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel. Level Conversion Circuit The LCX017DLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V. –6– LCX017DLT 2. Clock timing conditions (Ta = 25°C) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn rise HCK time∗5 Hckn fall time∗5 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time Enb rise time Enb fall time ENB Horizontal video period completed to Enb fall time Enb rise to PRG∗4 fall time Enb fall to Pcg rise time Enb pulse width Pcg rise time Pcg fall time PCG Pcg rise to Vck rise/fall time Pcg fall to horizontal video period start time Pcg pulse width PRG∗4 rise to Pcg rise time PRG∗4 PRG∗4 fall to Pcg fall time PRG∗4 pulse width Blk rise time BLK∗5 Blk fall time Blk rise to Enb fall time Blk fall to Pcg rise time ∗5 ∗6 (XGA mode: fHckn = 3.9MHz, fVck = 34.3kHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb toPRG∗4 toPcg twEnb trPcg tfPcg toVck toVideo twPcg toPcgr toPcgf twPRG∗4 trBlk tfBlk toEnb toPcg Min. — — 55 55 — — –15 –15 — — 2 2 — — — — 760 110 830 1650 — — –100 170 1400 –10 570 830 — — 2 –1 Typ. — — 65 65 — — 0 0 — — 7 7 — — — — 800 120 1000 — — — 0 200 1700 0 700 1000 — — 1 0 Max. 30 30 75 75 30 30 15 15 100 100 12 12 100 100 100 100 — 130 — — 30 30 100 — — 10 — — 100 100 0 1 µs ns µs ns Unit Hckn means Hck1 and Hck2. Blk is the timing during PC98 mode, which keeps "H" level in other modes. –7– LCX017DLT Item Hst rise time Hst fall time HST Symbol trHst Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions • Hckn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst ∗7 Hst data set-up time tdHst 50% 50% Hst Hck1 Hst data hold time thHst tdHst 50% 50% thHst 90% 10% • Hckn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn rise time∗5 trHckn 90% ∗5 Hckn 10% Hckn fall time∗5 HCK Hck1 fall to Hck2 rise time tfHckn ∗7 to1Hck Hck1 • Hckn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns trHckn tfHckn 50% 50% 50% 50% Hck1 rise to Hck2 fall time to2Hck Hck2 to2Hck to1Hck ∗7 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. –8– LCX017DLT Item Vst rise time Vst fall time VST Symbol trVst Vst 10% trVst ∗7 Waveform 90% 90% 10% tfVst Conditions tfVst Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst 90% Vck 10% thVst 90% 10% Vck rise time VCK Vck fall time trVck tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time Horizontal video period completed to Enb fall time ENB Enb rise to PRG∗4 fall time tfEnb tfEnb trEnb tdEnb H. Video period H. Blanking period ∗7 twEnb 50% 50% toPRG∗4 Enb PRG∗4 tdEnb 50% toPRG∗4 50% 50% Enb fall to Pcg rise time toPcg toPcg PCG Enb pulse width twEnb –9– LCX017DLT Item Pcg rise time Symbol trPcg Pcg 10% Waveform 90% 90% 10% tfpcg Conditions Pcg fall time tfPcg trpcg PCG∗8 Pcg rise to Vck rise/fall time toVck ∗7 H. blanking period twPcg H. video period toVideo Pcg fall to horizontal video period start time toVideo Pcg 50% 50% toVck Vck 50% Pcg pulse width twPcg PRG∗4 rise to Pcg rise time toPcgr ∗7 ∗4 PRG∗4 PRG fall to Pcg fall time ∗8 twPRG∗4 toPcgf 50% 50% toPcgr PRG∗4 toPcgf Pcg 50% 50% PRG∗4 pulse width twPRG∗4 Blk rise time trBlk tfBlk 90% 10% 10% trBlk 90% Blk fall time tfBlk BLK Blk rise to Enb fall time toEnb ∗7 Blk 50% toPcg 50% toEnb Pcg 50% Blk fall to Pcg rise time toPcg Enb 50% ∗8 PCG input pin and PRG∗4 should be "H" level during the horizontal 1H period, where the above BLK is low more than 10ns. – 10 – LCX017DLT Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. — — –500 Typ. 30 35 –220 Max. 35 40 — — — — 250 20.0 Unit pF pF µA µA µA µA pF mA HCKn: HCK1, HCK2 (3.9MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition –1000 –390 –500 –150 — — –120 –30 200 14.0 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK,PCG Symbol CVck CVst Min. — — Typ. 15 15 Max. 20 20 — — 6.0 Unit pF pF µA µA mA VCK = GND, PCG = GND VST, ENB, DWN,BLK, HB VB = GND VCK: (34.3kHz) Condition –1000 –180 –150 IV — –40 4.0 VST, ENB, DWN, BLK, HB, VB Current consumption 3. Total power consumption of the panel Item Symbol Min. — Typ. 250 Max. 400 Unit mW Total power consumption of the panel PWR 4. Pin input resistance Item Pin – VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. — Unit MΩ 5. Uniformity improvement signal Item Symbol Min. — Typ. 13 Max. 16 Unit nF Input pin capacitance for uniformity CPSIGo improvement signal 6. COM pin capacitance Item COM pin capacitance Symbol COM Min. — Typ. 20 Max. 25 Unit nF – 11 – LCX017DLT Electro-optical Characteristics Item Contrast ratio Optical transmittance 25°C 25°C Symbol Measurement method Min. CR T RV90-25 25°C V90 60°C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25°C V-T characteristics V50 60°C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25°C V10 60°C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0°C 25°C 0°C 25°C 60°C 25°C 25°C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 1 2 200 20 0.7 0.9 1.0 0.7 0.8 1.0 1.1 1.2 1.3 1.1 1.2 1.3 1.6 1.7 1.8 1.6 1.7 1.8 — — — — — — — Typ. 350 23 1.1 1.3 1.4 1.1 1.2 1.4 1.5 1.6 1.7 1.5 1.6 1.7 2.0 2.1 2.2 2.0 2.1 2.2 37 17 100 30 –65 0 — (XGA mode) Max. — — 1.5 1.6 1.7 1.4 1.5 1.7 1.8 1.9 2.0 1.8 1.9 2.0 2.3 2.4 2.5 2.3 2.4 2.5 80 40 200 70 –40 — 5 dB s % ms V Unit — % Reflection Preventive Processing When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection. – 12 – LCX017DLT Basic measurement conditions (1) Driving voltage HVDD = 13.5V, VVDD = 15.5V VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Two types of measurement systems are used as shown below. (5) Video input signal voltage (Vsig) (VAC = signal amplitude) Vsig = 7.0 ± VAC [V] • Measurement system I Approx. 2000mm Screen Luminance Meter LCD Projector Measurement Equipment Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent Projection lens: Focal distance 80mm, F1.9 Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500) (× 24, Sensor area: 7mmφ) Polarizer: Side of incidence - Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent Side of output light - Polatechno’s SHC-128 or equivalent • Measurement system II Optical fiber Light receptor lens Polarizer Drive Circuit LCD panel Polarizer Light Source Light Detector Measurement Equipment 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ... (1) L (Black) L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 4.5V. Both luminosities are measured by System I. – 13 – LCX017DLT 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= White luminance Luminance of light source × 100 [%] ... (2) "White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V on Measurement System I. Transmittance [%] 3. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 90 50 10 V90 V50 V10 VAC – Signal amplitude [V] 4. Response Time Response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. Input signal voltage (Waveform applied to the measured pixels) 4.5V 7.0V 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff – 14 – LCX017DLT 5. Flicker Flicker (F) is given by formula (7). DC and AC (XGA/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20log { AC component } ...(7) DC component ∗ Each input signal voltage for gray raster mode is given by Vsig = 7.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. 6. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 7.0 ± 4.5 or ± 2.0 [V] (shown in the right figure) Vcom = 6.6V Black level 4.5V 2.0V 7.0V 2.0V 4.5V White level 0V Vsig waveform 7. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V). Cross talk value CTK = Wi' – Wi × 100 [%] Wi W4 W4' W3 W3' W2 W2' W1 W1' – 15 – LCX017DLT Viewing angle characteristics (Typical Value) 90 CR = 5 10 20 50 100 180 150 250 200 10 30 50 70 0 Theta Phi 270 θ0° Z Marking θ φ90° φ180° φ Y φ0° X φ270° Measurement method – 16 – 1. Dot Arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. Gate SW Gate SW Photo-Shielding Active area 2 dots 1024 dots (Effective 36.86mm) 4 dots 1032dots LCX017DLT 4 dots 2 dots 768 dots (Effective 27.65mm) 772 dots – 17 – LCX017DLT 2. LCD Panel Operations [Description of basic operations] • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 768 gate lines sequentially in a single horizontal scanning period. (XGA mode) • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 1024 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. • Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 768 × 1024 dots to display a picture in a single vertical scanning period. • The data and video signals shall be input with the 1H-inverted system. [Description of operating mode] This LCD panel can change the active area by displaying a black frame to support various computer or video signals. The active area is switched by HB, VB and BLK. However, the center of the screen is not changed. The active area setting modes are shown below. HB H L H ∗1 ∗2 VB H H L BLK H H ∗1 Screen aspect ratio 4:3 1024 × 768 5:4∗2 960 × 768 8:5 1024 × 640 Input BLK pulse (refer to drive waveform and vertical blanking period of PC98 made). For only aspect ratio 5:4 mode, set Psig and COM voltage as shown below. The value of PsigG and COM voltage is typical value. It is necessary to optimize the voltage for each set construction. VVC + 4.5 [V] VVC + 1.0 [V] VVC Psig Psig B Psig G VVC – 1.0 [V] VVC – 4.5 [V] PRG∗3 VCOM + 2.0 COM VCOM – 2.0 VCOM ∗3 PRG shows the time of the 1st step of Psig signal, and it is not input to the panel. – 18 – LCX017DLT This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. • Right/left inverse mode • Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below. RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside. To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the H and V systems must be varied. The phase relationship between the start pulse and the clock for each mode is shown below. (1) Vertical direction display cycle (1.1) XGA, SXGA VD VST VCK 1 (DWN = H, L) 2 3 4 765 766 767 768 Vertical display cycle 768H (1.2) PC98 VD VST VCK 1 2 3 4 637 638 639 640 Vertical display cycle 640H – 19 – LCX017DLT (2) Horizontal direction display cycle (2.1.1) XGA, PC98 (RGT = H) HD HST HCK1 HCK2 1 2 3 4 83 84 85 86 Horizontal display cycle (2.1.2) XGA, PC98 (RGT = L) HD HST HCK1 HCK2 1 2 3 4 83 84 85 86 Horizontal display cycle (2.2.1) SXGA (RGT = H) HD HST HCK1 HCK2 1 2 3 4 77 78 79 80 Horizontal display cycle (2.2.2) SXGA (RGT = L) HD HST HCK1 HCK2 1 2 3 4 77 78 79 80 Horizontal display cycle – 20 – LCX017DLT (3) Vertical blanking cycle of PC98 mode The input waveforms of PCG, PRG∗1 and PSIG should be changed as shown below when BLK pulse is input. Vertical blanking cycle BLK VCK ENB PCG PRG∗1 PSIG ∗1 PRG shows the period of PSIG black level, it is not input to the panel. – 21 – LCX017DLT 3. 12-dot Simultaneous Sampling The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel. The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed. VSIG1 S/H CK1 S/H 3 VSIG1 VSIG2 S/H CK2 S/H 4 VSIG2 VSIG3 S/H CK3 S/H 5 VSIG3 VSIG4 S/H CK4 S/H 6 VSIG4 VSIG5 S/H CK5 S/H 7 VSIG5 VSIG6 S/H CK6 S/H 8 VSIG6 VSIG7 S/H CK7 S/H 9 VSIG7 VSIG8 S/H CK8 S/H 10 VSIG8 VSIG9 S/H CK9 S/H 11 VSIG9 VSIG10 S/H CK10 S/H 12 VSIG10 VSIG11 S/H CK11 S/H 13 VSIG11 VSIG12 S/H CK12 14 VSIG12 – 22 – LCX017DLT LCX017DLT (right scan) HCKn CK1 CK2 CK3 CK4 CK5 CK6 CK7 CK8 CK9 CK10 CK11 CK12 – 23 – LCX017DLT Display System Block Diagram An example of display system is shown below. CXA3512R S/H Driver 6 LCX017 CXA3512R S/H Driver 6 CXA3512R S/H Driver R G B CXA2111R Gamma CXA3512R S/H Driver PRG, CLP L.P.F. 6 LCX017 6 CXD3503R Color Shading Correction VST CXA3512R S/H Driver 6 LCX017 HSYNC CXA3106AQ PLL MCLK/2 DSYNC CXD3500R Timing Generator CXA3512R S/H Driver 6 ENB, PRG, FRP Timing Pulses VSYNC – 24 – LCX017DLT Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the glass panel. c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a cleanroom wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow dust off the glass panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 0.294N · m or less. i) Use appropriate filter to protect a panel. j) Do not pressure the portion other than mounting hole (cover). – 25 – LCX017DLT Package Outline Unit: mm 16.5 ± 0.05 4 1 5.4 ± 0.1 Thickness of the connector 0.3 ± 0.05 2.35 ± 0.1 (51.6) 107.6 ± 1.4 Incident light Polarizing Axis 56.0 ± 0.15 50.0 ± 0.1 2.2 ± 0.1 25.0 ± 0.25 (27.6) 3.0 ± 0.1 0.5 ± 0.15 P 0.5 ± 0.02 × 31 = 15.5 ± 0.03 0.5 ± 0.1 0.35 ± 0.03 4.0 ± 0.4 3.0 4-R 3-φ2.3 ± 0.05 C0.8 2 3 5 7 6 Incident light 9 8 Active Area Output light Polarizing Axis φ2.2 ± 0.1 (36.9) 40.0 ± 0.1 50.0 ± 0.15 25.0 ± 0.25 5.0 ± 0.1 No 1 2 3 4 Description FPC Molding material Outside frame Reinforcing board PIN1 PIN32 5 Reinforcing material 6 7 electrode (enlarged) The rotation angle of the active area relative to H and V is ± 1°. 8 9 Glass 1 Glass 2 Cover 1 Cover 2 Mass 25g – 26 – Sony Corporation