LCX026ALE

LCX026ALE 2.3cm (0.9-inch) Black-and-White LCD Panel For the availability of this product, please contact the sales office. Description The LCX026ALE is a 2.3cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. Use of three LCX026ALE panels provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines. The adoption of an advanced on-chip black matrix realizes a high luminance screen. And cross talk free circuit and ghost free circuit contribute to high picture quality. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals. The panel contains an active area variable circuit which supports SVGA/VGA/PC98∗1 data signals by changing the active area according to the type of input signal. In addition, double-speed processed NTSC/PAL can also be supported. ∗1 “PC98” is a treadmark of NEC Corporation. Features • Number of active dots: 485,000 (0.9-inch, 2.3cm in diagonal) • Accepts the computer requirements of SVGA (804 × 604), VGA (644 × 484) and PC98 (644 × 404) platforms • Supports NTSC (644 × 484) and PAL (762 × 572) by processing the video signal at double speed • High optical transmittance: 17% (typ.) • Built-in cross talk free circuit and ghost free circuit • High contrast ratio with normally white mode: 350 (typ.) • Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) • Up/down and/or right/left inverse display function • High durable polarizer used • Built-in λ/2 retardation film for blue light (V) Element Structure • Dots: 804 (H) × 604 (V) = 485,616 • Built-in peripheral driver using polycrystalline silicon super thin film transistors Applications • Liquid crystal data projectors • Liquid crystal projectors, etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97Z39-PS Block Diagram 1 PSIG HST HCK1 HCK2 Up/Down and/or Right/Left Inversion Control Circuit 13 14 15 V Shift Register (Bidirectional Scanning) Black Frame Control Circuit 17 Input Signal Level Shifter Circuit 9 BLK RGT 20 Precharge Control Circuit VST 19 21 22 18 12 VCK PCG DWN ENB MODE1 MODE2 MODE3 8 11 10 H Shift Register (Bidirectional Scanning) Black Frame Control Circuit –2– COM PAD HVDD 23 16 7 5 3 2 VVDD Vss SIG1 SIG2 SIG3 SIG4 Black Frame Control Circuit 4 6 24 SIG5 SIG6 V Shift Register (Bidirectional Scanning) COM LCX026ALE LCX026ALE Absolute Maximum Ratings (VSS = 0V) • H driver supply voltage HVDD • V driver supply voltage VVDD • Common pad voltage COM • H shift register input pin voltage HST, HCK1, HCK2, RGT • V shift register input pin voltage VST, VCK, PCG, BLK, ENB, DWN MODE1, MODE2, MODE3 • Video signal input pin voltage SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG • Operating temperature Topr • Storage temperature Tstg –1.0 to +20 –1.0 to +20 –1.0 to +17 –1.0 to +17 –1.0 to +17 V V V V V –1.0 to +15 –10 to +70 –30 to +85 V °C °C Operating Conditions (VSS = 0V) • Supply voltage HVDD 15.5 ± 0.5V VVDD 15.5 ± 0.5V • Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 ± 0.5V Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol PSIG SIG4 SIG3 SIG5 SIG2 SIG6 SIG1 HVDD RGT MODE3 MODE2 MODE1 Description Uniformity improvement signal Video signal 4 to panel Video signal 3 to panel Video signal 5 to panel Video signal 2 to panel Video signal 6 to panel Video signal 1 to panel Power supply for H driver Drive direction pulse for H shift register (H: normal, L: reverse) Display area switching 3 Display area switching 2 Display area switching 1 Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 –3– Symbol HST HCK1 HCK2 Vss BLK ENB VCK VST PCG DWN VVDD COM Description Start pulse for H shift register drive Clock pulse for H shift register drive Clock pulse for H shift register drive GND (H, V drivers) Black Frame display pulse Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Improvement pulse for uniformity Drive direction pulse for V shift register (H: normal, L: reverse) Power supply for V driver Common voltage of panel LCX026ALE Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.) (1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG HVDD Input 1MΩ (2) HCK1, HCK2 HVDD 250Ω Input 250Ω 1MΩ 250Ω 250Ω 1MΩ Signal line Level conversion circuit (2-phase input) (3) RGT HVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (4) HST HVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (5) PCG, VCK VVDD 250Ω Input 1MΩ 250Ω Level conversion circuit (single-phase input) (6) VST, BLK, ENB, DWN, MODE1, MODE2, MODE3 VVDD 2.5kΩ Input 1MΩ 2.5kΩ Level conversion circuit (single-phase input) (7) COM VVDD Input 1MΩ LC –4– LCX026ALE Input Signals 1. Input signal voltage conditions (VSS = 0V) Item H shift register input voltage (Low) HST, HCK1, HCK2, RGT (High) V shift register input voltage (Low) MODE1, MODE2, MODE3, BLK, VST, VCK, PCG, (High) ENB, DWN Video signal center voltage Video signal input range∗1 Common voltage of panel∗2 Uniformity improvement signal input voltage (PSIG)∗3 Symbol VHIL VHIH VVIL VVIH VVC Vsig Vcom Vpsig Min. –0.5 4.5 –0.5 4.5 6.8 VVC – 4.5 VVC – 0.5 VVC ± 4.3 Typ. 0.0 5.0 0.0 5.0 7.0 7.0 VVC – 0.4 VVC ± 4.5 Max. 0.4 5.5 0.4 5.5 7.2 VVC + 4.5 VVC – 0.3 VVC ± 4.7 Unit V V V V V V V V ∗1 Input video signal shall be symmetrical to VVC. ∗2 The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. ∗3 Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below). The optimum input voltage of PSIG may be changed according as drive conditions of the drive side. Input waveform of uniformity improvement signal PSIG 90% PSIG VVC 10% trPSIG tfPSIG PCG Level Conversion Circuit The LCX026ALE has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V. –5– LCX026ALE 2. Clock timing conditions (Ta = 25°C) Item Hst rise time HST Hst fall time Hst data set-up time Hst data hold time Hckn rise time∗4 HCK Hckn fall time∗4 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data set-up time Vst data hold time VCK Vck rise time Vck fall time Enb rise time ENB Enb fall time Vck rise/fall to Enb rise time Enb pulse width Pcg rise time PCG Pcg fall time Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time BLK∗5 Blk fall time Blk fall to Vst rise time Blk pulse width (SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb twEnb trPcg tfPcg toVck twPcg trBlk tfBlk toVst twBlk Min. — — 50 50 — — –15 –15 — — 5 5 — — — — 400 2400 — — 900 1100 — — 32 20 Typ. — — 60 60 — — 0 0 — — 10 10 — — — — 500 2500 — — 1000 1200 — — 33 21 Max. 30 30 70 70 30 30 15 15 100 100 15 15 100 100 100 100 600 2600 30 30 1100 1300 100 100 34 22 µs ns µs ns Unit ∗4 Hckn means Hck1 and Hck2. ∗5 Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz). –6– LCX026ALE Item Hst rise time Hst fall time HST Symbol trHst Hst 10% trHst Waveform 90% 90% 10% tfHst Conditions • Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst ∗6 Hst data set-up time tdHst 50% 50% Hst Hck1 Hst data hold time thHst tdHst 50% 50% thHst 90% 10% • Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns Hckn rise time∗3 Hckn fall time∗3 HCK Hck1 fall to Hck2 rise time trHckn 90% ∗3 Hckn 10% tfHckn ∗6 to1Hck Hck1 • Hckn∗3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns trHckn tfHckn 50% 50% 50% 50% Hck1 rise to Hck2 fall time to2Hck Hck2 to2Hck to1Hck ∗6 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. –7– LCX026ALE Item Vst rise time Vst fall time VST Symbol trVst Vst 10% trVst Waveform 90% 90% 10% tfVst Conditions tfVst ∗6 Vst data set-up time tdVst 50% Vst 50% 50% 50% Vck Vst data hold time thVst tdVst 90% Vck 10% thVst 90% 10% Vck rise time VCK Vck fall time trVck tfVck trVckn tfVckn Enb rise time trEnb Enb 90% 10% 10% 90% Enb fall time tfEnb tfEn trEn ENB Vck rise/fall to Enb rise time tdEnb Vck 50% Enb 50% twEnb 50% Enb pulse width twEnb ∗6 tdEnb Pcg rise time Pcg fall time PCG∗7 Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time Blk fall time BLK Blk fall to Vst rise time Blk pulse width trPcg tfPcg Vck toVck 50% toVck trPcg twBlk Vst Pcg 50% 50% twPcg ∗6 tfBlk toVst twBlk Blk 50% 50% twBlk toVst 50% ∗6 ∗7 Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin. –8– LCX026ALE Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. — — –500 Typ. 7 7 –250 Max. 12 12 — — — — 200 15.0 Unit pF pF µA µA µA µA pF mA HCKn: HCK1, HCK2 (4.0MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition –1000 –300 –500 –150 — — –150 –30 130 10.0 2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK Symbol CVck CVst Min. — — Typ. 7 7 Max. 12 12 — — 6.0 Unit pF pF µA µA mA VCK = GND PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 = GND VCK: (24.0kHz) Condition –1000 –150 –150 IV — –30 3.0 PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 Current consumption 3. Total power consumption of the panel Item Total power consumption of the panel Symbol Min. PWR — Typ. 200 Max. 300 Unit mW 4. Pin input resistance Item Pin – VSS input resistance Symbol Rpin Min. 0.4 Typ. 1 Max. — Unit MΩ 5. Uniformity improvement signal Item Symbol Min. — Typ. 8 Max. 12 Unit nF Input pin capacitance for uniformity CPSIGo improvement signal –9– LCX026ALE Electro-optical Characteristics Item Contrast ratio Optical transmittance 25°C 25°C Symbol Measurement method Min. CR T RV90-25 25°C V90 60°C GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 25°C V-T characteristics V50 60°C GV50-25 BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 25°C V10 60°C GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ON time Response time OFF time Flicker Image retention time Cross talk 0°C 25°C 0°C 25°C 60°C 25°C 25°C ton0 ton25 toff0 toff25 F YT60 CTK 5 6 7 4 3 1 2 150 15 1.0 1.1 1.2 1.0 1.0 1.1 1.4 1.5 1.6 1.4 1.4 1.5 1.9 2.0 2.1 1.9 1.9 1.9 — — — — — — — Typ. 350 17 1.3 1.5 1.6 1.3 1.4 1.5 1.7 1.8 1.9 1.6 1.7 1.8 2.2 2.3 2.4 2.1 2.2 2.3 30 12 100 30 –65 — — (SVGA mode) Max. — — 1.7 1.9 2.0 1.6 1.7 1.9 2.0 2.1 2.2 1.9 2.0 2.1 2.5 2.6 2.7 2.4 2.5 2.6 80 40 200 70 –40 0 5 dB s % ms V Unit — % Reflection Preventive Processing When a retardation film which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a retardation film with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection. – 10 – LCX026ALE Basic measurement conditions (1) Driving voltage HVDD = 15.5V, VVDD = 15.5V VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Two types of measurement systems are used as shown below. (5) Video input signal voltage (Vsig) Vsig = 7.0 ± VAC [V] (VAC = signal amplitude) • Measurement system I Approx. 2000mm Screen Luminance Meter LCD Projector Measurement Equipment Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent Projection lens: Focal distance 80mm, F1.9 Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500) (× 24, Sensor area: 7mmφ) Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-1824ZT or equivalent • Measurement system II Optical fiber Light receptor lens Light Detector Measurement Equipment Drive Circuit LCD panel Light Source 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) L (Black) ... (1) L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 4.5V. Both luminosities are measured by System I. – 11 – LCX026ALE 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= White luminance Luminance of light source × 100 [%] ... (2) "White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V on Measurement System I. Transmittance [%] 3. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 90 50 10 V90 V50 V10 VAC – Signal amplitude [V] 4. Response Time Response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. Input signal voltage (Waveform applied to the measured pixels) 4.5V 7.0V 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff – 12 – LCX026ALE 5. Flicker Flicker (F) is given by formula (7). DC and AC (SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. AC { DC component } ...(7) component ∗ Each input signal voltage for gray raster mode is given by Vsig = 7.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. F [dB] = 20log 6. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct. ∗ Monoscope signal conditions: Vsig = 7.0 ± 4.5 or ± 2.0 [V] (shown in the right figure) Vcom = 6.6V Black level 4.5V 2.0V 7.0V 2.0V 4.5V White level 0V Vsig waveform 7. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V). Cross talk value CTK = Wi' – Wi × 100 [%] Wi W4 W4' W3 W3' W2 W2' W1 W1' – 13 – LCX026ALE Viewing angle characteristics (Typical Value) 90 Phi 0 180 10 30 50 70 Theta 270 θ0° Z θ φ90° Marking φ Y φ180° φ0° X φ270° Measurement method – 14 – LCX026ALE Optical transmittance of LCD panel (Typical Value) 30 20 Trans. [%] 10 0 400 500 600 Wavelength [nm] 700 Measurement method: Measurement system ΙΙ – 15 – LCX026ALE 1. Dot Arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW Photo-Shielding Active area 604 dots (Effective 13.89mm) 6 dots 4 dots 6 dots 804 dots (Effective 18.49mm) 816 dots – 16 – 4 dots 612 dots LCX026ALE 2. LCD Panel Operations [Description of basic operations] • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 604 gate lines sequentially in a single horizontal scanning period. (in SVGA mode) • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 804 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. • Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 604 × 804 dots to display a picture in a single vertical scanning period. • The data and video signals shall be input with the 1H-inverted system. [Description of operating mode] This LCD panel can change the active area by displaying a black frame to support various computer or video signals. The active area is switched by MODE1, 2 and 3. However, the center of the screen is not changed. The active area setting modes are shown below. MODE1 L L L H MODE2 L H H L MODE3 H L H L Display mode SVGA 804 × 604 PAL 762 × 572 VGA/NTSC 644 × 484 PC98 644 × 404 This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems. • Right/left inverse mode • Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below. RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside. To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the H and V systems nust be varied. The phase relationship between the start pulse and the clock for each mode is shown on the following pages. – 17 – LCX026ALE (1) Vertical direction display cycle (1.1) SVGA VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 601 602 603 604 Vertical display cycle 604H (1.2) PAL VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 569 570 571 572 Vertical display cycle 572H (1.3) VGA/NTSC VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 481 482 483 484 Vertical display cycle 484H (1.4) PC98 VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 401 402 403 404 Vertical display cycle 404H – 18 – LCX026ALE (2) Horizontal direction display cycle (2.1.1) SVGA, RGT = H HD HST HCK1 HCK2 (2.1.2) SVGA, RGT = L HD HST HCK1 HCK2 1 2 3 4 131 132 133 134 1 2 3 4 131 132 133 134 Horizontal display cycle Horizontal display cycle (2.2.1) PAL, RGT = H HD HST HCK1 HCK2 1 2 3 4 125 126 127 128 Horizontal display cycle (2.2.2) PAL, RGT = L HD HST HCK1 HCK2 1 2 3 4 125 126 127 128 Horizontal display cycle – 19 – LCX026ALE (2.3.1) VGA/NTSC/PC98, RGT = H HD HST HCK1 HCK2 1 2 3 4 105 106 107 108 Horizontal display cycle (2.3.2) VGA/NTSC/PC98, RGT = L HD HST HCK1 HCK2 1 2 3 4 105 106 107 108 Horizontal display cycle – 20 – LCX026ALE 3. 6-dot Simultaneous Sampling The horizontal shift register samples signals SIG1 to SIG6 simultaneously. This requires phase matching between signals SIG1 to SIG6 to prevent the horizontal resolution from deteriorating. Thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel. The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low level), the phase settings for signals SIG1 to SIG6 are exactly reversed. SIG1 SIG2 S/H CK1 S/H CK2 S/H S/H 8 6 SIG1 SIG2 SIG3 SIG4 S/H CK3 S/H CK4 S/H S/H 4 3 5 7 SIG3 SIG4 SIG5 SIG6 SIG5 SIG6 S/H CK5 S/H S/H CK6 (right scan) HCKn CK1 CK2 CK3 CK4 CK5 CK6 – 21 – LCX026ALE LCX026ALE Display System Block Diagram An example of display system is shown below. R-IN G-IN B-IN Pre Driver CXA2111R S/H Driver CXA2112R 6 LCX026 R CLP, PRG S/H Driver CXA2112R 6 LCX026 G Vsync Hsync Timing Generator CXD2464R S/H Driver CXA2112R 6 LCX026 B FRP, S/H Control PLL CXA3106Q MCK1 HST, HCK, VST, VCK, PCG, ENB – 22 – LCX026ALE Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the panel. c) Do not touch the panel surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow dust off the panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 3kg · cm or less. – 23 – LCX026ALE Package Outline Unit: mm 3.7 ± 0.1 Thickness of the connector 12.5 ± 0.05 0.3 ± 0.05 2.2 ± 0.1 4 1 (74.0) 2 3 27.0 ± 0.1 32.0 ± 0.15 106.0 ± 1.4 26.0 ± 0.1 31.0 ± 0.15 (18.5) 15.5 ± 0.25 2.5 ± 0.1 15.5 ± 0.25 2.5 ± 0.1 (13.9) P 0.5 ± 0.02 × 23 = 11.5 ± 0.03 0.5 ± 0.1 0.35 ± 0.03 0.5 ± 0.15 4.0 ± 0.4 PIN1 The rotation angle of the active area relative to H and V is ± 1°. weight 5.3g 2. R 80 Active Area 5-φ2.2 ± 0.05 5 Transmittance Axis Polarizing Axis Incident light 7 6 8 No 1 2 3 4 Description FPC Molding material Outside frame Reinforcing board PIN24 5 Reinforcing material 6 7 electrode (enlarged) 8 λ/2 retardation film Cover 1 Cover 2 + Polarizing film – 24 –