Am49PDL127BH/ Am49PDL129BH
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 30452 Revision A
Amendment +3 Issue Date December 16, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am49PDL127BH/Am49PDL129BH
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt ■ High performance
— Access time as fast as 65 ns initial / 25 ns page
■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector
■ Package
— 73-Ball FBGA
PERFORMANCE CHARACTERISTICS
■ High Performance
— Page access times as fast as 25 ns — Random access times as fast as 65 ns
■ Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■ 128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random locations within the page
■ Power consumption (typical values at 10 MHz)
— 45 mA active read current — 25 mA program/erase current — 1 µA typical standby mode current
■ Dual Chip Enable inputs (PDL129 only)
— Two CE# inputs control selection of each half of the memory space
SOFTWARE FEATURES
■ Software command-set compatible with JEDEC 42.4 standard
— Backward compatible with Am29F and Am29LV families
■ Single power supply operation
— Full Voltage range: 2.7 to 3.3 volt read, erase, and program operations for battery-powered applications
■ CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
■ Simultaneous Read/Write Operation
— Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations
■ Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program operations in other sectors of same bank
■ FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations per device — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — Bank C: 48 Mbit (32 Kw x 96) — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
■ Unlock Bypass Program command
— Reduces overall programming time when issuing multiple program command sequences
■ SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 30452 Rev: A Amendment +3 Issue Date: December 16, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
ADVANCE HARDWARE FEATURES
■ Ready/Busy# pin (RY/BY#)
INFORMATION
pSRAM FEATURES
■ Power dissipation
— Operating: 40 mA maximum — Standby: 70 µA maximum — Deep power-down standby: 5 µA
— Provides a hardware method of detecting program or erase cycle completion
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■ CE1s# and CE2ps Chip Select ■ Power down features using CE1s# and CE2ps ■ Data retention supply voltage: 2.7 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) ■ 8-word page mode access
■ WP#/ACC (Write Protect/Acceleration) input
— At VIL, hardware level protection for the first and last two 4K word sectors. — At VIH, allows removal of sector protection — At VHH, provides accelerated programming in a factory setting
■ Persistent Sector Protection
— A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level
■ Password Sector Protection
— A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
2
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
GENERAL DESCRIPTION
T he Am29PDL127H/Am29PDL129H are 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory devices organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. The devices can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The devices offer fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the devices have separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space. ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows:
PDL127 Configuration
Chip Enable Control Bank A CE#f1 B C D Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31)
PDL129H Configuration
Chip Enable Control Bank CE#f1 CE#f2 A B C D Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally gener-
December 16, 2003
Am49PDL127BH/Am49PDL129BH
3
ADVANCE
INFORMATION
TABLE OF CONTENTS
PDL127 Configuration ........................................................... 3 PDL129H Configuration ......................................................... 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram–PDL129 . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Connection Diagram–PDL127 . . . . . . . . . . . . . . . . 8 Special Package Handling Instructions .................................... 8 Look Ahead Ballout Diagram . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12 MCP Device Bus Operations . . . . . . . . . . . . . . . . 13 Requirements for Reading Array Data ................................... 15 Random Read (Non-Page Read) ........................................ 15 Page Mode Read ................................................................ 15
Table 2. Page Select .......................................................................15
Write Pulse “Glitch” Protection ............................................ 42 Logical Inhibit ....................................................................... 42 Power-Up Write Inhibit ......................................................... 42 Common Flash Memory Interface (CFI) . . . . . . . 42 Command Definitions . . . . . . . . . . . . . . . . . . . . . 46 Reading Array Data ................................................................ 46 Reset Command ..................................................................... 46 Autoselect Command Sequence ............................................ 46 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 47 Word Program Command Sequence ...................................... 47 Unlock Bypass Command Sequence .................................. 47
Figure 5. Program Operation ......................................................... 48
Chip Erase Command Sequence ........................................... 48 Sector Erase Command Sequence ........................................ 48
Figure 6. Erase Operation.............................................................. 49
Simultaneous Operation ......................................................... 15
Table 3. Bank Select (PDL129H) ....................................................15 Table 4. Bank Select (PDL127H) ....................................................15
Writing Commands/Command Sequences ............................ 16 Accelerated Program Operation .......................................... 16 Autoselect Functions ........................................................... 16 Standby Mode ........................................................................ 16 Automatic Sleep Mode ........................................................... 16 RESET#: Hardware Reset Pin ............................................... 17 Output Disable Mode .............................................................. 17
Table 5. Am29PDL127H Sector Architecture ..................................18 Table 6. Am29PDL129H Sector Architecture ..................................25 Table 7. SecSiTM Sector Addresses ................................................32 Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................33 Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................34
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 35 Persistent Sector Protection ................................................... 35 Persistent Protection Bit (PPB) ............................................ 35 Persistent Protection Bit Lock (PPB Lock) .......................... 35 Dynamic Protection Bit (DYB) ............................................. 35
Table 10. Sector Protection Schemes .............................................36
Erase Suspend/Erase Resume Commands ........................... 49 Password Program Command ................................................ 49 Password Verify Command .................................................... 50 Password Protection Mode Locking Bit Program Command .. 50 Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 50 SecSi Sector Protection Bit Program Command .................... 50 PPB Lock Bit Set Command ................................................... 50 DYB Write Command ............................................................. 50 Password Unlock Command .................................................. 50 PPB Program Command ........................................................ 51 All PPB Erase Command ........................................................ 51 DYB Write Command ............................................................. 51 PPB Lock Bit Set Command ................................................... 51 PPB Status Command ............................................................ 51 PPB Lock Bit Status Command .............................................. 51 Sector Protection Status Command ....................................... 51 Command Definitions Tables .................................................. 52
Table 15. Memory Array Command Definitions ............................. 52 Table 16. Sector Protection Command Definitions ........................ 53
Persistent Sector Protection Mode Locking Bit ................... 36 Password Protection Mode ..................................................... 36 Password and Password Mode Locking Bit ........................ 37 64-bit Password ................................................................... 37 Write Protect (WP#) ................................................................ 37 Persistent Protection Bit Lock .............................................. 37 High Voltage Sector Protection .............................................. 38
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 39
Write Operation Status . . . . . . . . . . . . . . . . . . . . 54 DQ7: Data# Polling ................................................................. 54
Figure 7. Data# Polling Algorithm .................................................. 54
RY/BY#: Ready/Busy# ............................................................ 55 DQ6: Toggle Bit I .................................................................... 55
Figure 8. Toggle Bit Algorithm........................................................ 55
DQ2: Toggle Bit II ................................................................... 56 Reading Toggle Bits DQ6/DQ2 ............................................... 56 DQ5: Exceeded Timing Limits ................................................ 56 DQ3: Sector Erase Timer ....................................................... 56
Table 17. Write Operation Status ................................................... 57
Temporary Sector Unprotect .................................................. 40
Figure 2. Temporary Sector Unprotect Operation........................... 40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 58
Figure 9. Maximum Negative Overshoot Waveform ...................... 58 Figure 10. Maximum Positive Overshoot Waveform...................... 58
SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 40 Factory-Locked Area (64 words) ......................................... 40 Customer-Lockable Area (64 words) ................................... 40
Figure 3. PDL127H/129H SecSi Sector Protection Algorithm......... 41
ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 59 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. Test Setup.................................................................... 61 Figure 12. Input Waveforms and Measurement Levels ................. 61
SecSi Sector Protection Bits ................................................ 41
Figure 4. SecSi Sector Protect Verify.............................................. 42
Hardware Data Protection ...................................................... 42 Low VCC Write Inhibit ......................................................... 42 4
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 62 CE#1ps Timing ....................................................................... 62
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION Read Cycle ............................................................................. 75
Figure 27. Pseudo SRAM Read Cycle........................................... 75 Figure 28. Page Read Timing ........................................................ 76
Figure 13. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................. 62
Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 63 Read-Only Operations – Am29PDL127H ............................... 63 Read-Only Operations – Am29PDL129H ............................... 63
Figure 14. Read Operation Timings ................................................ 64 Figure 15. Page Read Operation Timings....................................... 64
Write Cycle ............................................................................. 77
Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 77 Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 78 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 79
Hardware Reset (RESET#) .................................................... 65
Figure 16. Reset Timings ................................................................ 65
Erase and Program Operations .............................................. 66
Figure 17. Program Operation Timings........................................... 67 Figure 18. Accelerated Program Timing Diagram........................... 67 Figure 19. Chip/Sector Erase Operation Timings ........................... 68 Figure 20. Back-to-back Read/Write Cycle Timings ....................... 69 Figure 21. Data# Polling Timings (During Embedded Algorithms).. 69 Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 70 Figure 23. DQ2 vs. DQ6.................................................................. 70
Erase And Programming Performance . . . . . . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . Package Pin Capacitance. . . . . . . . . . . . . . . . . . . Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . pSRAM Power on and Deep Power Down . . . . .
80 80 80 80 81 81
Figure 32. Deep Power-down Timing............................................. 81 Figure 33. Power-on Timing........................................................... 81
Temporary Sector Unprotect .................................................. 71
Figure 24. Temporary Sector Unprotect Timing Diagram ............... 71 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 72
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 82
Figure 34. Read Address Skew ..................................................... 82 Figure 35. Write Address Skew...................................................... 82
Alternate CE#f1 Controlled Erase and Program Operations .. 73
Figure 26. Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings........................................................................... 74
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 83 TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 83 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 84
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 75
December 16, 2003
Am49PDL127BH/Am49PDL129BH
5
ADVANCE
INFORMATION
PRODUCT SELECTOR GUIDE
Part Number Speed Option Standard Voltage Range: VCC = 2.7–3.3 V Am49PDL127BH/Am49PDL129BH Flash Memory 66 65 25 65 25 85 85 30 85 30 Pseudo SRAM 66 70 30 70 25 85 85 35 85 30
Max Access Time, ns Page Access Time, ns CE#f1 Access, ns OE# Access, ns
MCP BLOCK DIAGRAM
A21 to A0 (A22 PDL127 only) WP#/ACC RESET# CE#f1 CE#f2 (PDL129 only) (A22) A21 to A0
RY/BY# 128 MBit Flash Memory DQ15 to DQ0 DQ15 to DQ0
VCCs
VSS
A20 to A0 LB#s UB#s WE# OE# CE1#ps CE2ps 32 MBit Pseudo SRAM
DQ15 to DQ0
6
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
CONNECTION DIAGRAM–PDL129
73-Ball FBGA Top View
A1
NC
A10
NC
B1
NC
B5
NC
B6
NC
B10
NC
Pseudo SRAM Only Flash Only
C1
NC
C3
A7
C4 D4
UB#
C5 D5 E5
RY/BY#
C6 D6 E6
A20
C7
A8
C8
A11
LB# WP#/ACC WE#
D2
A3
D3
A6
D7
A19
D8
A12
D9
A15
Shared
RESET# CE2ps
E2
A2
E3
A5
E4
A18
E7
A9
E8
A13
E9
A21
F1
NC
F2
A1
F3
A4
F4
A17
F7
A10
F8
A14
F9
CE#f2
F10
NC
G1
NC
G2
A0
G3
VSS
G4
DQ1
G7
DQ6
G8
NC
G9
A16
G10
NC
H2
CE#f1
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
NC
J2
CE#1ps
J3
DQ0
J4
DQ10
J5
VCCf
J6
VCCps
J7
DQ12
J8
DQ7
J9
VSS
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8
DQ14
L1
NC
L5
NC
L6
NC
L10
NC
M1
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged periods of time.
December 16, 2003
Am49PDL127BH/Am49PDL129BH
7
ADVANCE
INFORMATION
CONNECTION DIAGRAM–PDL127
73-Ball FBGA Top View
A1
NC
A10
NC
B1
NC
B5
NC
B6
NC
B10
NC
Pseudo SRAM Only Flash Only
C1
NC
C3
A7
C4 D4
UB#
C5 D5 E5
RY/BY#
C6 D6 E6
A20
C7
A8
C8
A11
LB# WP#/ACC WE#
D2
A3
D3
A6
D7
A19
D8
A12
D9
A15
Shared
RESET# CE2ps
E2
A2
E3
A5
E4
A18
E7
A9
E8
A13
E9
A21
F1
NC
F2
A1
F3
A4
F4
A17
F7
A10
F8
A14
F9
A22
F10
NC
G1
NC
G2
A0
G3
VSS
G4
DQ1
G7
DQ6
G8
NC
G9
A16
G10
NC
H2
CE#f1
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
NC
J2
CE#1ps
J3
DQ0
J4
DQ10
J5
VCCf
J6
VCCps
J7
DQ12
J8
DQ7
J9
VSS
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8
DQ14
L1
NC
L5
NC
L6
NC
L10
NC
M1
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
8
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
PIN DESCRIPTION
A20–A0 A21 A22 DQ15–DQ0 CE#f1 CE#f2 CE#1ps CE2ps OE# WE# RY/BY# = 21 Address Inputs (Common) = Address Inputs (Flash) = Address Input (PDL127 only) (Flash) = 16 Data Inputs/Outputs (Common) = Chip Enable 1 (Flash) = Chip Enable 2 (Flash) (PDL 129 only) = Chip Enable 1 (pSRAM) = Chip Enable 2 (pSRAM) = Output Enable (Common) = Write Enable (Common) = Ready/Busy Output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. = Upper Byte Control (pSRAM) = Lower Byte Control (pSRAM) = Hardware Reset Pin, Active Low = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = pSRAM Power Supply = Device Ground (Common) = Pin Not Connected Internally
LOGIC SYMBOL
21 A20–A0 A21 A22 (PDL127 Only) CE#f1 DQ15–DQ0 16
CE#f2 (PDL129 Only) CE#1ps CE2ps OE# WE# WP#/ACC RESET# UB#s LB#s RY/BY#
UB#s LB#s RESET# WP#/ACC
VCCf
VCCs VSS NC
December 16, 2003
Am49PDL127BH/Am49PDL129BH
9
ADVANCE
INFORMATION
LOOK AHEAD BALLOUT DIAGRAM
A1
NC
A2
NC
A9
NC
A10
NC
LEGEND
B1
NC
B2
NC
B9
NC
B10
NC
Data Storage
C2
AVD#
C3
VSS
C4
CLK
C5
CE#f2
C6
VCC
C7
RST#
C8
CLK
C9
RY/BY#
1st RAM
D2
WP#
D3
A7
D4
LB#
D5
ACC or WP#/ACC
D6
WE#
D7
A8
D8
A11
D9
CE#1
E2
A3
E3
A6
E4
UB#
E5
RESET#
E6
CE2
E7
A19
E8
A12
E9
A15
2nd RAM
F2
A2
F3
A5
F4
A18
F5
RY/BY#
F6
A20
F7
A9
F8
A13
F9
A21
FASL Standard MCP Packages 7.0 x 9.0 mm 8.0 x 10.0 mm 8.0 x 11.6 mm 9.0 x 12.0 mm
G2
A1
G3
A4
G4
A17
G5
CE#1
G6
A23
G7
A10
G8
A14
G9
A22
H2
A0
H3
VSS
H4
DQ1
H5
VCC
H6
CE2
H7
DQ6
H8
A24
H9
A16
J2
CE#f1
J3
OE#
J4
DQ9
J5
DQ3
J6
DQ4
J7
DQ13
J8
DQ15
J9
CREs or VCCf
K2
CE1#
K3
DQ0
K4
DQ10
K5
VCCf
K6
VCC
K7
DQ12
K8
DQ7
K9
VSS
L2
NC
L3
DQ8
L4
DQ2
L5
DQ11
L6
A25 or VCCQ
L7
DQ5
L8
L9
DQ14 LOCK or WP#/ACC
M2
IRQ/A27
M3
A26
M4
NC
M5
VCC/VCCQ
M6
CE#2
M7
VCCQ
M8
VCCQ
M9
NC
N1
NC
N2
NC
N9
NC
N10
NC
P1
NC
P2
NC
P9
NC
P10
NC
Note: The future ballouts shown in this diagram represent possible future products with densities up to 4 Gbits of Flash plus 4 Gbits of SRAM. Device combinations include NOR Flash plus SRAM, NOR Flash plus pSRAM, and NOR Flash plus pSRAM plus data storage. Contact a sales representative for device specifications, planned production, and availability before designing in any future product.
10
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION The signal locations of the resultant MCP device are shown in the diagram. Note that for different densities, the actual package outline may vary. However, any ballout in any MCP will be a subset of the ballout diagram shown. In some cases, there may be outrigger balls in locations outside the grid shown. Do not connect these outrigger balls to any signal. For further information regarding the look-ahead ballout, contact the appropriate AMD or Fujitsu sales office.
To provide customers with a migration path to higher densities, as well as the option of stacking more die in o ne pa cka ge, th e pre ce ding diagram s how s a look-ahead ballout that supports: ■ NOR Flash and SRAM densities up to 4 Gigabits ■ NOR Flash and PSRAM densities up to 4 Gigabits ■ NOR Flash and PSRAM and DATA STORAGE densities up to 4 Gigabits
December 16, 2003
Am49PDL127BH/Am49PDL129BH
11
ADVANCE
INFORMATION
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am49PDL12 7 B H 66 I T
TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5. PROCESS TECHNOLOGY H = 0.13 µm PSEUDO SRAM DEVICE DENSITY B = 32 Mbits CONTROL PINS 7 = 1 CE Flash 9 = 2 CE Flash AMD DEVICE NUMBER/DESCRIPTION Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) Pseudo Static RAM with Page Mode
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations Order Number Am49PDL127BH66I Am49PDL127BH85I Am49PDL129BH66I Am49PDL129BH85I T, S T, S T, S T, S Package Marking M490000028 M490000029 M490000030 M490000031
12
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information
December 16, 2003
Am49PDL127BH/Am49PDL129BH
13
ADVANCE Table 1.
Operation (Notes 1, 2)
Read from Active Flash Write to Active Flash Standby Deep Power-down Standby Output Disable (Note 9) Flash Hardware (Note 7) Reset (Note 8) (Note 7) Sector Protect (Notes 6, 10) (Note 9) (Note 7) (Note 8) (Note 7) (Note 8) X L (H) H (L) L (H) H (L) (Note 7) (Note 8) (Note 7) (Note 8)
INFORMATION
Device Bus Operations
Addr. LB#s UB#s WP#/ (Note (Note RESET# ACC 3) 3) (Note 4)
X X H L/H
CE#f2 CE#f1 (PDL129 CE#1ps CE2ps OE# WE# Active only)
L (H) H (L) H H H H H H L H H H H H H H H H L H L H L H H L H L H L H L X X H L H L L H
DQ7– DQ0
DOUT DIN High-Z High-Z High-Z
DQ15– DQ8
DOUT DIN High-Z High-Z High-Z
AIN AIN X X X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = H, A1 = H, A0 = L X
L (H)
H (L)
H X X H H X
L X X H H X
X X X X X X
X X X X X X
H VCC ± 0.3 V VCC ± 0.3 V H
(Note 4)
H H L/H
VCC ± 0.3 V VCC ± 0.3 V L (H) H (L)
X
L
L/H
High-Z
High-Z
X
X
VID
L/H
DIN
X
Sector Unprotect (Notes 5, 9) Temporary Sector Unprotect
X
X
VID
(Note 6)
DIN
X
X L
X L L H L L H
VID
(Note 6)
DIN DOUT
High-Z DOUT DOUT High-Z DIN DIN High-Z
Read from pSRAM
H
H
L
H
L
H
AIN
H L L
H
X
High-Z DOUT DIN
Write to pSRAM
H
H
L
H
X
L
AIN
H L
H
X
High-Z DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f1 or 2 = VIL, CE#1ps = VIL and CE2ps = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM.
9. Both CE#f1 inputs may be held low for this operation.
14
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION page mode accesses are obtained by keeping A22–A3 (A21–A3 for PDL129) constant and changing A2 to A0 to select the specific word within that page.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE#f1/CE#f2 (PDL129 only) pins to VIL. CE#f1 and CE#f2 are the power control and for PDL129 select the lower (CE#f1) or upper (CE#f2) halves of the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Flash AC Characteristics table for timing specifications and to Figure 14 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE#f1 to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A22–A3 (A21–A3 for PDL129) select an 8-word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC o r tCE a nd subsequent page read accesses (as long as the locations specified by the microprocessor fall within that page) are t PACC. When CE#f1 and CE#f2 (PDL129 only) are deasserted (CE#f1=CE#f2=VIH), the reassertion of CE#f1 or CE#f2 (PDL129 only) for subsequent access has access time of t ACC o r t CE . Here again, CE#f1/CE#f2 (PDL129 only) selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast
Table 2.
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Page Select
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Simultaneous Operation
In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank addresses (A22–A20) (A21–A20 for PDL129) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3.
Bank Bank A Bank B Bank C Bank D CE#f1 0 0 1 1
Bank Select (PDL129H)
CE#f2 1 1 0 0 A21–A20 00, 01, 10 11 00 01, 10, 11
Table 4.
Bank Bank A Bank B Bank C Bank D
Bank Select (PDL127H)
A22–A20 000 001, 010, 011 100, 101, 110 111
December 16, 2003
Am49PDL127BH/Am49PDL129BH
15
ADVANCE
INFORMATION Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Command Sequence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL 129 only) to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The Flash AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f1, CE#f2 (PDL129 only) and RESET# pins are all held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f1, CE#f2 (PDL129 only), and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 i n the DC Characteristics table represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#f1/CE#f2 (PDL129 only), WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.
16
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY ( not during Embedded Algorithms). The system can read data tRH a fter the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state
December 16, 2003
Am49PDL127BH/Am49PDL129BH
17
ADVANCE Table 5.
Bank Sector
INFORMATION
Am29PDL127H Sector Architecture
Sector Size (Kwords) Address Range (x16)
Sector Address (A22-A12)
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank A SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank Sector
00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Sector Address (A22-A12)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Sector Size (Kwords)
000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh
Address Range (x16)
18
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 5.
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
INFORMATION
Am29PDL127H Sector Architecture (Continued)
00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
December 16, 2003
Am49PDL127BH/Am49PDL129BH
19
ADVANCE Table 5.
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank B SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
INFORMATION
Am29PDL127H Sector Architecture (Continued)
01001000XXX 01001001XXX 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
20
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 5.
SA119 SA120 SA121 SA122 SA123 SA124 SA125 Bank B SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank C SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
INFORMATION
Am29PDL127H Sector Architecture (Continued)
01110000XXX 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh 400000h–407FFFh 408000h–40FFFFh 410000h–417FFFh 418000h–41FFFFh 420000h–427FFFh 428000h–42FFFFh 430000h–437FFFh 438000h–43FFFFh 440000h–447FFFh 448000h–44FFFFh 450000h–457FFFh 458000h–45FFFFh 460000h–467FFFh 468000h–46FFFFh 470000h–477FFFh 478000h–47FFFFh 480000h–487FFFh 488000h–48FFFFh 490000h–497FFFh 498000h–49FFFFh 4A0000h–4A7FFFh 4A8000h–4AFFFFh 4B0000h–4B7FFFh 4B8000h–4BFFFFh
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
December 16, 2003
Am49PDL127BH/Am49PDL129BH
21
ADVANCE Table 5.
SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 Bank C SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
INFORMATION
Am29PDL127H Sector Architecture (Continued)
10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX 10111111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4C0000h–4C7FFFh 4C8000h–4CFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 4F0000h–4F7FFFh 4F8000h–4FFFFFh 500000h–507FFFh 508000h–50FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 530000h–537FFFh 538000h–53FFFFh 540000h–547FFFh 548000h–54FFFFh 550000h–557FFFh 558000h–15FFFFh 560000h–567FFFh 568000h–56FFFFh 570000h–577FFFh 578000h–57FFFFh 580000h–587FFFh 588000h–58FFFFh 590000h–597FFFh 598000h–59FFFFh 5A0000h–5A7FFFh 5A8000h–5AFFFFh 5B0000h–5B7FFFh 5B8000h–5BFFFFh 5C0000h–5C7FFFh 5C8000h–5CFFFFh 5D0000h–5D7FFFh 5D8000h–5DFFFFh 5E0000h–5E7FFFh 5E8000h–5EFFFFh 5F0000h–5F7FFFh 5F8000h–5FFFFFh
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
22
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 5.
SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank C SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
INFORMATION
Am29PDL127H Sector Architecture (Continued)
11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 600000h–607FFFh 608000h–60FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh 670000h–677FFFh 678000h–67FFFFh 680000h–687FFFh 688000h–68FFFFh 690000h–697FFFh 698000h–69FFFFh 6A0000h–6A7FFFh 6A8000h–6AFFFFh 6B0000h–6B7FFFh 6B8000h–6BFFFFh 6C0000h–6C7FFFh 6C8000h–6CFFFFh 6D0000h–6D7FFFh 6D8000h–6DFFFFh 6E0000h–6E7FFFh 6E8000h–6EFFFFh 6F0000h–6F7FFFh 6F8000h–6FFFFFh
December 16, 2003
Am49PDL127BH/Am49PDL129BH
23
ADVANCE Table 5.
Bank Sector
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16)
SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 Bank D SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
700000h–707FFFh 708000h–70FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h–76FFFFh 770000h–777FFFh 778000h–77FFFFh 780000h–787FFFh 788000h–78FFFFh 790000h–797FFFh 798000h–79FFFFh 7A0000h–7A7FFFh 7A8000h–7AFFFFh 7B0000h–7B7FFFh 7B8000h–7BFFFFh 7C0000h–7C7FFFh 7C8000h–7CFFFFh 7D0000h–7D7FFFh 7D8000h–7DFFFFh 7E0000h–7E7FFFh 7E8000h–7EFFFFh 7F0000h–7F7FFFh 7F8000h–7F8FFFh 7F9000h–7F9FFFh 7FA000h–7FAFFFh 7FB000h–7FBFFFh 7FC000h–7FCFFFh 7FD000h–7FDFFFh 7FE000h–7FEFFFh 7FF000h–7FFFFFh
24
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 6.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f1
INFORMATION
Am29PDL129H Sector Architecture
CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE#f2 Sector Address (A21-A12) 0000000000 0000000001 0000000010 0000000011 0000000100 0000000001 0000000010 0000000011 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX Sector Address (A21-A12) Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) Address Range (x16) 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh Address Range (x16)
Bank A
SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank
Sector
December 16, 2003
Am49PDL127BH/Am49PDL129BH
25
ADVANCE Table 6.
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f1
INFORMATION
Am29PDL129H Sector Architecture (Continued)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE#f2 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX Sector Address (A21-A12) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh Address Range (x16)
Bank B
SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
Bank
Sector
26
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 6.
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank B SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 Bank Sector 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f1
INFORMATION
Am29PDL129H Sector Architecture (Continued)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE#f2 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX Sector Address (A21-A12) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh Address Range (x16)
December 16, 2003
Am49PDL127BH/Am49PDL129BH
27
ADVANCE Table 6.
SA119 SA120 SA121 SA122 SA123 SA124 SA125
Bank B
INFORMATION
Am29PDL129H Sector Architecture (Continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh
SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
28
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 6.
SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank C SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 Bank Sector 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE#f1
INFORMATION
Am29PDL129H Sector Architecture (Continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f2 0000000XXX 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX Sector Address (A21-A12) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) 000000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh Address Range (x16)
December 16, 2003
Am49PDL127BH/Am49PDL129BH
29
ADVANCE Table 6.
SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176
Bank C (continued)
INFORMATION
Am29PDL129H Sector Architecture (Continued)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f2 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX Sector Address (A21-A12) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh Address Range (x16)
SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
Bank
Sector
CE#f1
30
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 6.
SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212
Bank C (continued)
INFORMATION
Am29PDL129H Sector Architecture (Continued)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f2 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX Sector Address (A21-A12) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sector Size (Kwords) 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh Address Range (x16)
SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
Bank
Sector
CE#f1
December 16, 2003
Am49PDL127BH/Am49PDL129BH
31
ADVANCE Table 6.
SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249
Bank D
INFORMATION
Am29PDL129H Sector Architecture (Continued)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh
SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
Table 7.
SecSi Sector Area
SecSiTM Sector Addresses
Sector Size 64 words Address Range 000000h-00003Fh
SecSi Sector Area Customer-Lockable Area
Sector Size 64 words
Address Range 000040h-00007Fh
Factory-Locked Area
32
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
SA135–SA138 SA139–SA142 SA143–SA146 SA147–SA150 SA151–SA154 SA155–SA158 SA159–SA162 SA163–SA166 SA167–SA170 SA171–SA174 SA175–SA178 SA179–SA182 SA183–SA186 SA187–SA190 SA191–SA194 SA195–SA198 SA199–SA202 SA203–SA206 SA207–SA210 SA211–SA214 SA215–SA218 SA219–SA222 SA223–SA226 SA227–SA230 SA231–SA234 SA235–SA238 SA239–SA242 SA243–SA246 SA247–SA250 SA251–SA254 SA255–SA258 SA259–SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 96 (3x32) Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8–SA10 SA11–SA14 SA15–SA18 SA19–SA22 SA23–SA26 SA27–SA30 SA31–SA34 SA35–SA38 SA39–SA42 SA43–SA46 SA47–SA50 SA51–SA54 SA55–SA58 SA59–SA62 SA63–SA66 SA67–SA70 SA71–SA74 SA75–SA78 SA79–SA82 SA83–SA86 SA87–SA90 SA91–SA94 SA95–SA98 SA99–SA102 SA103–SA106 SA107–SA110 SA111–SA114 SA115–SA118 SA119–SA122 SA123–SA126 SA127–SA130 A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 96 (3x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords Sector/ Sector Block Size 128 (4x32) Kwords
Sector SA131–SA134
A22-A12 011111XXXXX
December 16, 2003
Am49PDL127BH/Am49PDL129BH
33
ADVANCE
INFORMATION
Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 96 (3x32) Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
Sector
CE#f1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CE#f2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A21–A12 11110XXXXX 11111XXXXX 00000XXXXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8–SA10 SA11–SA14 SA15–SA18 SA19–SA22 SA23–SA26 SA27–SA30 SA31–SA34 SA35–SA38 SA39–SA42 SA43–SA46 SA47–SA50 SA51–SA54 SA55–SA58 SA59–SA62 SA63–SA66 SA67–SA70 SA71–SA74 SA75–SA78 SA79–SA82 SA83–SA86 SA87–SA90 SA91–SA94 SA95–SA98 SA99–SA102 SA103–SA106 SA107–SA110 SA111–SA114 SA115–SA118 SA119–SA122 SA123–SA126 CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21–A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 96 (3x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
SA127–SA130 SA131–SA134 SA135–SA138 SA139–SA142 SA143–SA146 SA147–SA150 SA151–SA154 SA155–SA158 SA159–SA162 SA163–SA166 SA167–SA170 SA171–SA174 SA175–SA178 SA179–SA182 SA183–SA186 SA187–SA190 SA191–SA194 SA195–SA198 SA199–SA202 SA203–SA206 SA207–SA210 SA211–SA214 SA215–SA218 SA219–SA222 SA223–SA226 SA227–SA230 SA231–SA234 SA235–SA238 SA239–SA242 SA243–SA246 SA247–SA250 SA251–SA254 SA255–SA258 SA259–SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
34
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
SECTOR PROTECTION
The Am29PDL127H/Am29PDL129H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: ■ Dynamically Locked—The sector is protected and can be changed by a simple command. ■ Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does 35
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted.
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. The WP# Hardware Protection feature is always available, regardless of which of the other two methods are chosen.
Selecting a Sector Protection Mode
The device defaults to the Persistent Sector Protection mode. However, to prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode, it is recommended that either of two one-time programmable non-volatile bits that permanently define which sector protection method be set before the device is first programmed. The Persistent Sector Protection Mode Locking Bit p ermanently sets the device to the Persistent Sector Protection mode. The Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Command Sequence for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection method in previous AMD flash devices. This new method provides three different sector protection states: ■ Persistently Locked—The sector is protected and cannot be changed.
December 16, 2003
Am49PDL127BH/Am49PDL129BH
ADVANCE
INFORMATION Table 10. Sector Protection Schemes
PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable
n ot prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL.
DYB 0 0 0 1 1 0 1 1
PPB 0 0 1 0 1 1 0 1
Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable
Table 10 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i v e n s e c t o r c a n b e ve r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differ-
36
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.
e nces between the Persistent Sector Protection and the Password Sector Protection Mode: ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set.
December 16, 2003
Am49PDL127BH/Am49PDL129BH
37
ADVANCE
INFORMATION
If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID ) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
38
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
START PLSCNT = 1 RESET# = VID Wait 4 µs Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 µs
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A7-A0 = 00000010 Set up next sector address
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes Remove VID from RESET#
Data = 00h? Yes
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Yes Remove VID from RESET#
No
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms
December 16, 2003
Am49PDL127BH/Am49PDL129BH
39
ADVANCE
INFORMATION i nd i cato r bi ts ( D Q6 , D Q7 ) to in di ca te the factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words)
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 24 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h–00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD’s ExpressFlash service. N ote that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h–00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: ■ Follow the SecSi Sector protection algorithm as shown in Figure 3. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector.
Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 268, 269 will remain protected). 2. All previously protected sectors are protected once again.
Figure 2.
Temporary Sector Unprotect Operation
SecSi™ (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h–00007Fh in both Persistent Protection mode and Password Protection mode. It uses
40
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
START
SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to address 555h
SecSi Sector Entry
SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to address 555h
PLSCNT = 1
Protect SecSi Sector: write 68h to sector address with A7–A0 = 00011010
Time out 256 µs
SecSi Sector Protection
Increment PLSCNT
Verify SecSi Sector: write 48h to sector address with A7–A0 = 00011010
Read from sector address with A7–A0 = 00011010 No No PLSCNT = 25? Data = 01h?
Yes Device Failed
Yes SecSi Sector Protection Completed
SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h
SecSi Sector Exit
Figure 3.
PDL127H/129H SecSi Sector Protection Algorithm unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the
■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 4. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for December 16, 2003
Am49PDL127BH/Am49PDL129BH
41
ADVANCE
INFORMATION Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#f1, CE#f2 or WE# do not initiate a write cycle. Logical Inhibit
S ecSi Sector memory area contents are non-modifiable.
START RESET# = VIH or VID Wait 1 µs Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected.
Write cycles are inhibited by holding any one of OE# = V IL, CE#f1 =CE#f2 = VIH o r WE# = VIH . To initiate a write cycle, CE#f1/CE#f2 and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit
Remove VIH or VID from RESET#
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0
If WE# = CE#f1 = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Write reset command SecSi Sector Protect Verify complete
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 11–14. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 11–14. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.
Figure 4.
SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC i s greater than VLKO.
42
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 11.
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
INFORMATION
CFI Query Identification String
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 12.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
December 16, 2003
Am49PDL127BH/Am49PDL129BH
43
ADVANCE Table 13.
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
INFORMATION
Device Geometry Definition
Description
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
44
Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE Table 14.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch
INFORMATION
Primary Vendor-Specific Extended Query
Description
Query-unique ASCII string “PRI” Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
0002h 0001h 0001h 0007h 00E7h 0000h 0002h 0085h
Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag
4Eh
0095h
4Fh
0001h
00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4
50h
0001h
57h
0004h
58h
0027h
59h
0060h
5Ah
0060h
5Bh
0027h
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INFORMATION
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 15 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens later. All data is latched on the rising edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens first. Refer to the Flash AC Characteristics section for timing diagrams. erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur ns th a t ba nk to the e ra s e- s us pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding ban k enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the MCP Device Bus Operations section for more information. The Read-Only Operations – Am29PDL127H and Read-Only Operations – Am29PDL129H tables provide the read parameters, and Figure 14 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 15 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before
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INFORMATION Programming is allowed in any sequence and across sector boundaries. A b it cannot be programmed from “0” back to a “1.” A ttempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 15 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH a ny operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figures 17 and 18 for timing diagrams.
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 15 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. N ote that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 15 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity.
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INFORMATION
START
available when the SecSi Sector is enabled. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 for timing diagrams.
Write Program Command Sequence
Sector Erase Command Sequence
Embedded Program algorithm in progress Data Poll from System
Verify Data?
No
Yes No
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 15 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 15 for program command sequence.
Figure 5. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 15 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. N ote that the SecSi sector, autoselect, and CFI functions are un-
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INFORMATION ing the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 15 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 6.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written durDecember 16, 2003
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Four Password Program commands are required to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the pass-
Am49PDL127BH/Am49PDL129BH
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INFORMATION Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
word program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password.
SecSi Sector Protection Bit Program Command
The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. E xiting the VCC -level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode).
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits A22–A12 for PDL127 and A21–A12 for PDL129H are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac-
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INFORMATION the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µ s execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written.
A fter programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The PPB Program command does not follow the Embedded Program algorithm.
PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin,
Sector Protection Status Command
The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.
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INFORMATION
Command Definitions Tables
Table 15.
Command (Notes) Read (5) Reset (6) Manufacturer ID Device ID (10) Autoselect (Note 7) SecSi Sector Factory Protect (8) Sector Group Protect Verify (9) Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) CFI Query (13) Accelerated Program (15) Unlock Bypass Entry (15) Unlock Bypass Program (15) Unlock Bypass Erase (15) Unlock Bypass CFI (13, 15) Unlock Bypass Reset (15) Cycles
Memory Array Command Definitions
Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data
Addr Data Addr Data Addr Data RA XXX 555 555 555 555 555 555 555 BA BA 55 XX 555 XX XX XX XXX RD F0 AA AA AA AAA AA AA AA B0 30 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 90 90 90 90 A0 80 80
1 1 4 6 4 4 4 6 6 1 1 1 2 3 2 2 1 2
(BA)X00 (BA)X01 X03 (SA)X02 PA 555 555
01 7E (see note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X0E (Note 10) (BA)X0F 00
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A22:A20, (A21:A20 for PDL129) see Tables 4 and 7 for more detail. PA = Program Address (A22:A0) (A21:A0 for PDL129). Addresses latch on falling edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information.
RA = Read Address (A22:A0) (A21:A0 for PDL129). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A22:A12) (A21:A12 for PDL129) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care
8. The data is C0h for factory or customer locked and 80h for factory locked. 9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. Data is 20 for Am29PDL127H and 21 for Am29PDL129H. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array.
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Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (5, 6) SecSi Protection Bit Status Password Program (5, 7, 8) Password Verify (6, 8, 9) Password Unlock (7, 10, 11) PPB Program (5, 6, 12, 17) PPB Status All PPB Erase (5, 6, 13, 14) PPB Lock Bit Set (17) PPB Lock Bit Status (15) DYB Write (7) DYB Erase (7) DYB Status (6, 18) PPMLB Program (5, 6, 12) PPMLB Status (5) SPMLB Program (5, 6, 12) SPMLB Status (5) Cycles
INFORMATION
Sector Protection Command Definitions
Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data Addr Data
Addr Data Addr Data F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
1 XXX 3 4 6 5 4 4 7 6 5 6 3 4 4 4 4 6 5 6 5 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555
555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555
88 90 60 60 38 C8 28 60 60 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 48 68 48 PL PL SL SL 48 RD(0) 48 RD(0) SL RD(0) PL RD(0) XX OW OW XX[0-3] PWA[0] (SA)WP (SA)WP WP 00 68 48 PD[0-3] PWD[0] 68 48 60 PWA[1] (SA)WP (SA)WP (SA) PWD[1] 48 RD (0) 40 (SA)WP RD(0) PWA[2] (SA)WP PWD[2] RD(0) PWA[3] PWD[3] OW OW 48 RD(0) OW RD(0)
PWA[0-3] PWD[0-3]
Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit.
1. See Table 1 for description of bus operations. 2. All values are in hexadecimal.
RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits A21:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) (Note 16) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For PDL128G and PDL640G, the WP address is 0111010. The EP address (PPB Erase Address) is 1111010. 17. Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary.
3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password. 9. Command sequence returns FFh if PPMLB is set.
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ADVANCE
INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 17 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles. Table 17 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. Figure 7 in the Flash AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has comSTART
Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
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Am49PDL127BH/Am49PDL129BH
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ADVANCE
INFORMATION DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 17 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 22 in the “Flash AC Characteristics” section shows the toggle bit timing diagrams. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 17 shows the outputs for RY/BY#.
START
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f1 to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.
Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7–DQ0) Address = VA
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 8.
Toggle Bit Algorithm
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ADVANCE
INFORMATION The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f1 to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 17 to compare outputs for DQ2 and DQ6. Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” O nly an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits.
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ADVANCE Table 17.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
INFORMATION Write Operation Status
Standard Mode Erase Suspend Mode
DQ7 (Note 2) DQ7# 0 1 Data DQ7#
DQ6 Toggle Toggle No toggle Data Toggle
DQ5 (Note 1) 0 0 0 Data 0
DQ3 N/A 1 N/A Data N/A
DQ2 (Note 2) No toggle Toggle Toggle Data N/A
RY/BY# 0 0 1 1 0
Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . –40°C to +85°C Voltage with Respect to Ground VCCf, VCCs (Note 1) . . . . . . . . . . . . –0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS t o –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins RESET#, and WP# /ACC is –0 .5 V. D ur ing volt age trans itions, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
+0.8 V –0.5 V –2.0 V 20 ns 20 ns 20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 10. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VCCf/VCCs Supply Voltages VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
devices that are developed by a third party (‘third-party components”). Spansion components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory Qualification Database. Third-party components are neither tested nor guaranteed by FASL LLC for ESD immunity. However, ESD test results for third-party components may be available from the component manufacturer. Component manufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash memory Qualification Database and Spansion MCP Qualification Report are available from AMD and Fujitsu sales offices.
ESD IMMUNITY
Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are developed by FASL LLC (“Spansion components”) and component
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Am49PDL127BH/Am49PDL129BH
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ADVANCE
INFORMATION
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VHH VID VOL VOH VLKO Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes 1, 2, 3) VCC Active Write Current (Notes 1, 3, 4) VCC Standby Current (Note 3) VCC Reset Current (Note 3) Automatic Sleep Mode (Notes 3, 5) VCC Active Read-While-Program Current (Notes 1, 2, 3) VCC Active Read-While-Erase Current (Notes 1, 2, 3) VCC Active Program-While-EraseSuspended Current (Notes 1, 3, 6) Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 6) Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE#f1, CE#f2 (PDL129 only), RESET#, WP/ACC# = VIO ± 0.3 V RESET# = VSS ± 0.3 V, CE# = VSS VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V, CE# = VSS OE# = VIH OE# = VIH OE# = VIH VIO = 2.7–3.6 V VIO = 2.7–3.6 V VCC = 3.0 V ± 10% VCC = 3.0 V ± 10% IOL = 2.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min 2.4 2.3 2.5 –0.5 2.0 8.5 11.5 Word Word 5 MHz 10 MHz 20 45 15 1 1 1 21 21 17 Min Typ Max ±1.0 35 35 ±1.0 30 55 25 5 5 5 45 45 25 0.8 VCC+0.3 9.5 12.5 0.4 Unit µA µA µA µA mA mA µA µA µA mA mA mA V V V V V V V
Notes: 1. Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2= VIL) 2. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 µA.
6. Not 100% tested.
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ADVANCE
INFORMATION
pSRAM DC & OPERATING CHARACTERISTICS
Parameter Symbol ILI ILO Parameter Description Input Leakage Current Output Leakage Current Test Conditions VIN = VSS to VCC CE#1ps = VIH, CE2ps = VIL or OE# = VIH or WE# = VIL, VIO = VSS to VCC Cycle time = Min., IIO = 0 mA, 100% duty, CE#1ps = VIL, CE#2ps = VIH, VIN = VIL = VIH, tRC = Min Min –1.0 –1.0 Typ Max 1.0 1.0 Unit µA µA
ICC1s
Operating Current
40
mA
ICC2s VOL VOH ISB IDSB VIL VIH
Cycle time = Min., IIO = 0 mA, 100% Page Access Operating Current duty, CE#1ps = VIL, CE#2ps = VIH, VIN = VIL = VIH, tPC = Min Output Low Voltage Output High Voltage Standby Current (CMOS) Deep Power-down Standby Input Low Voltage Input High Voltage IOL = 1.0 mA IOH = –0.5 mA CE#f1 = VCCS –0.2 V, CE2 = VCCS = 0.2 V CE2 = 0.2 V –0.3 (Note 1) 2.4 2
25 0.4
mA V V
70 5 0.4 VCC + 0.3 (Note 2)
µA µA V V
Notes: 1. VCC–1.0 V for a 10 ns pulse width. 2. VCC+1.0 V for a 10 ns pulse width.
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Am49PDL127BH/Am49PDL129BH
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ADVANCE
INFORMATION
TEST CONDITIONS
Table 18.
3.3 V 2.7 kΩ Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 kΩ Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
66, 85 1 TTL gate 30 5 0.0–3.0 1.5 1.5 pF ns V V V Unit
Device Under Test
Note: Diodes are IN3064 or equivalent
Figure 11.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
KS000010-PAL
3.0 V 0.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
Figure 12.
Input Waveforms and Measurement Levels
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ADVANCE
INFORMATION
pSRAM AC CHARACTERISTICS CE#1ps Timing
Parameter Test Setup JEDEC — Std tCCR Description CE#1ps Recover Time — Min 0 ns All Speeds Unit
CE#1ps
tCCR CE2ps
tCCR
Figure 13. Timing Diagram for Alternating Between Pseudo SRAM and Flash
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Am49PDL127BH/Am49PDL129BH
December 16, 2003
ADVANCE
INFORMATION
FLASH AC CHARACTERISTICS Read-Only Operations – Am29PDL127H
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Note 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE#f1 or OE#, Whichever Occurs First (Notes 3) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#f1, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min Speed Options 66 65 65 65 25 25 16 16 5 0 10 85 85 85 85 30 30 Unit ns ns ns ns ns ns ns ns ns ns
Notes:
1. Not 100% tested. 2. See Figure 11 and Table 18 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF.
Read-Only Operations – Am29PDL129H
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay (Note 3) Chip Enable to Output Delay (Note 4) Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 5, 6) Output Enable to Output High Z (Notes 1, 5) Output Hold Time From Addresses, CE#f1/CE#f2 or OE#, Whichever Occurs First (Notes 5, 6) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#f1, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min Speed Options 66 65 65 65 25 25 16 16 5 0 10 85 85 85 85 30 30 Unit ns ns ns ns ns ns ns ns ns ns
Notes:
1. Not 100% tested. 2. See Figure 11 and Table 18 for test specifications
3. Valid CE#f1/CE#f2 conditions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL). 4. Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= VIH) to (CE#f1= VIL, CE#f2=VIH) or (CE#f1= VIH, CE#f2=VIL).
5. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. 6. Valid CE#f1/CE#f2 transitions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL) to (CE#f1= CE#f2= VIH).
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ADVANCE
INFORMATION
FLASH AC CHARACTERISTICS
tRC Addresses CE#f1 or CE#f2 (PDL 129 only) OE# Addresses Stable tACC tRH tRH tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF
0V
Figure 14.
Read Operation Timings
Addresses
Same Page
A2-A0
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data CE# f1 or CE#f2 (PDL129 only) OE#
Figure 15.
Qa
Qb
Qc
Qd
Page Read Operation Timings
Notes: During CE#f1 transitions, CE#f2= VIH; During CE#f2 transitions, CE#f1= VIH
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Am49PDL127BH/Am49PDL129BH
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ADVANCE
INFORMATION
FLASH AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit µs ns ns ns µs ns
Note: Not 100% tested.
RY/BY#
CE#f1, CE#f2 (PDL129 only), OE# RESET# tRP tReady
tRH
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#f1, CE#f2 (PDL129 only), OE#
RESET# tRP
Figure 16.
Reset Timings
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ADVANCE
INFORMATION
FLASH AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tWHDL tGHWL tWS tCS tWH tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE#1f or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time (CE#f1 to WE#) CE#f1 Setup Time WE# Hold Time (CE#f1 to WE#) CE#f1 Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max 66 65 05 15 35 0 30 0 10 0 0 0 0 0 40 25 0 6 4 0.5 50 0 90 Speed 85 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs sec µs ns ns
Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information.
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ADVANCE
INFORMATION
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE#f1 or CE#f2 (PDL129 only) OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tGHWL
tCH
A0h
VCCf tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode. 3. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 17.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 18.
Accelerated Program Timing Diagram
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INFORMATION
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SADD
555h for chip erase
Read Status Data
VA tAH
VA
CE#f1 or CE#f2 (PDL129 only) OE#
tGHWL tCH tWP
WE# tCS tDS tDH Data 55h
tWPH
tWHWH2
30h
10 for Chip Erase
In Progress
Complete
tBUSY RY/BY# tVCS VCCf
tRB
Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. 2. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 19.
Chip/Sector Erase Operation Timings
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INFORMATION
FLASH AC CHARACTERISTICS
tWC Addresses
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC
CE#f1 or CE#f2 (PDL129 only)
tCPH
tCE tOE tCP
OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE#f Controlled Write Cycles
Figure 20.
Back-to-back Read/Write Cycle Timings
tRC Addresses VA tACC tCE CE#f1 or CE#f2 (PDL129 only) OE# tOEH WE# tOH DQ7
High Z
VA
VA
tCH
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6–DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 21.
Data# Polling Timings (During Embedded Algorithms)
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INFORMATION
FLASH AC CHARACTERISTICS
tAHT Addresses
tAS
tAHT tASO CE#f1 or CE#f2 (PDL129 only) tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 22.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f1 to toggle DQ2 and DQ6.
Figure 23.
DQ2 vs. DQ6
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INFORMATION
FLASH AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns µs µs
Note: Not 100% tested.
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE#f1 or CE#f2 (PDL129 only) tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 24.
Temporary Sector Unprotect Timing Diagram
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INFORMATION
FLASH AC CHARACTERISTICS
VID VIH
RESET#
SADD, A6, A1, A0
Valid* Sector/Sector Block Protect or Unprotect
Valid* Verify 40h
Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 µs CE#f1 or CE#f1(PDL129 only) WE#
OE#
1. 2. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram
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INFORMATION
FLASH AC CHARACTERISTICS Alternate CE#f1 Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE#f1 Pulse Width CE#f1 Pulse Width High Word Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 66 65 0 35 30 0 0 0 0 40 25 6 4 0.4 Speed 85 85 Unit ns ns ns ns ns ns ns ns ns ns µs µs sec
Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information.
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INFORMATION
FLASH AC CHARACTERISTICS
555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE#f1 or CE#f2 (PDL129 only) tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SADD = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 26.
Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings
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INFORMATION
pSRAM AC CHARACTERISTICS Read Cycle
Parameter Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPC tAA tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control High to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold from Address Change Page Mode Time Page Mode Cycle Time Page Mode Address Access Time Page Output Data Hold Time Description Min Max Max Max Max Min Min Min Max Max Max Min Min Min Max Min Speed 66 70 70 70 25 25 10 0 0 20 20 20 10 70 30 30 10 85 85 85 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRC
Addresses A0 to A20
tACC tCO tOH
CE#1
CE2
tOD tOE
Fixed High
OE#
tODO
WE#
LB#, UB#
tBE tOEE tCOE
tBA tBD
High-Z
Indeterminate Valid Data Out
DOUT I/O1 to 16
High-Z
Notes: 1. tOD, tODo, tBD, and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
Figure 27.
Pseudo SRAM Read Cycle
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INFORMATION
pSRAM AC CHARACTERISTICS Read Cycle
tPM
Addresses A0 to A2
tRC tPC tPC tPC
Addresses A3 to A20
CE#1
CE2
Fixed High
OE#
WE#
LB#, UB#
tOE tBA tOEE tBE tAOH tAOH tAOH tOD tBD tOH DOUT tAA tODO
DOUT I/O1 to 16
tCOE tCO tACC
DOUT tAA
DOUT tAA
DOUT
Maximum 8 words
Figure 28.
Page Read Timing
3. If CE#f1, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
Notes: 1. tOD, tODo, tBD, and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. If CE#f1, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance.
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INFORMATION
pSRAM AC CHARACTERISTICS Write Cycle
Parameter Symbol tWC tWP tCW tBW tAW tAS tWR tODW tOEW tDS tDH tCH tCEH tWEH Description Write Cycle Time Write Pulse Time Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Setup Time Write Recovery Time WE# Low to Write to Output High-Z WE# High to Write to Output Active Data Set-up Time Data Hold from Write Time CE2 Hold Time Chip Enable High Pulse Width Write Enable High Pulse Width Min Min Min Min Min Min Min Max Min Min Min Min Min Min Speed 66 70 50 60 60 60 0 0 20 0 30 0 300 10 6 ns µs ns ns 85 85 60 70 70 70 Unit ns ns ns ns ns ns ns ns ns
tWC
Addresses A20 to A0
tAS tWP tWR
WE#
tCW
CE#1
tCH
CE2
tBW
LB#, UB#
tODW
(Note 3)
DOUT DQ15 to DQ0
High-Z
tOEW
(Note 4)
tDS
tDH
DIN DQ15 to DQ0
(Note 1)
Valid Data In
Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance. 3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. 4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 29.
Pseudo SRAM Write Cycle—WE# Control
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INFORMATION
pSRAM AC CHARACTERISTICS
tWC
Addresses A20 to A0
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
LB#, UB#
tBE tODW
High-Z
DOUT DQ15 to DQ0
High-Z
tCOE tDS tDH
DIN DQ15 to DQ0
(Note 1)
Valid Data In
(Note 1)
Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 30.
Pseudo SRAM Write Cycle—CE1#s Control
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INFORMATION
pSRAM AC CHARACTERISTICS
tWC
Addresses A20 to A0
tAS
tWP
tWR
WE#
tCW
CE#1
tCH
CE2
tBW
UB#, LB#
tCOE tODW tBE
DOUT DQ15 to DQ0
High-Z
High-Z
tDS
tDH
DIN DQ15 to DQ0
Valid Data In
Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control
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INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Typ (Note 1) 0.4 108 7 4 50 210 120 200 Max (Note 2) 5 Unit sec sec µs µs sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 15 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 11 12 14 17 Max 14 16 16 20 Unit pF pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years
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INFORMATION
pSRAM DATA RETENTION
Parameter Symbol VDR IDR tCS tCH tDPD tCHC tCHP Parameter Description VCC for Data Retention Data Retention Current CE2 Setup Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE#1 CE2 Hold from Power On Test Setup CS1#ps ≥ VCC – 0.2 V (Note 1) VCC = 3.0 V, CE1#ps ≥ VCC – 0.2 V (Note 1) 0 300 10 0 30 Min 2.7 1.0 (Note 2) Typ Max 3.3 70 Unit V µA ns µs ms ns µs
Notes: 1. CE1#ps ≥ VCC – 0.2 V, CE2ps ≥ VCC – 0.2 V (CE1#s controlled) or CE2ps ≤ 0.2 V (CE2ps controlled). 2. Typical values are not 100% tested.
pSRAM POWER ON AND DEEP POWER DOWN
CE#1ps
tDPD
CE#2ps
tCH
Figure 32.
Deep Power-down Timing
Note: Data cannot be retained during deep power-down standby mode.
VDD
VDD min
CE#1ps
tCHP
tCHC
CE#2ps
tCH
Figure 33.
Power-on Timing
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pSRAM ADDRESS SKEW
over 10 µs
CE#1ps
WE#
Address
tRC min
Figure 34.
Read Address Skew
Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 µs, at least one valid address cycle over tRC min is required during that period.
over 10 µs
CE#1ps
tWP min
WE#
Address
tWC min
Figure 35.
Write Address Skew
Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 µs, at least one valid address cycle over tWC min, in addition to tWP min, is required during that period.
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INFORMATION
PHYSICAL DIMENSIONS TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE
7
E eE
6 5 4 3 2 1 M L K J H G F E D CB A
E1
PIN A1 CORNER
10 INDEX MARK
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
73X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC TLA 073 N/A 11.60 mm X 8.00 mm PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD/SE 0.33 MIN. --0.20 0.81 NOM. ------11.60 BSC 8.00 BSC 8.80 BSC 7.20 BSC 12 10 73 --0.80 BSC 0.80 BSC 0.40 BSC A2,A3,A4,A5,A6,A7,A8,A9 B2,B3,B4,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10 F5,F6,G5,G6,H1,H10,J1,J10 K1,K2,K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 0.43 MAX. 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7. 6. NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = E/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. NOT USED.
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
w053003-163814c
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ADVANCE
INFORMATION
REVISION SUMMARY Revision A (June 16, 2003)
Initial release.
Revision A+3 (December 16, 2003)
Lookahead Ballout Diagram Added section and figure. Figure 1, In-System Sector Protection/ Sector Unprotection Algorithms Corrected command sequence to indicate writing 68h (for protect) and 48h (for verify) with A7–A0 set to 00011010b. SecSi™ (Secured Silicon) Sector Flash Memory Region
Revision A+1 (July 14, 2003)
Sector Protection
Selecting a Sector Protection Mode: Slightly modified text to improve readability.
Pin Description Corrected typo in WP#/ACC pin name. Flash AC Characteristics
Read-only Operation tables (Am29PDL127H and Am29PDL129H): Changed tOE specification for the 66 speed option to 25 ns.
SRAM AC Characteristics
Customer-Lockable Area: Added sector protection figure, modified text and changed figure reference in first bullet from Figure 1 to Figure 3.
Table 16, Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit Status, PPMLB Status, and SPMLB Status from 4 to 5 cycles. For these command sequences, inserted a cycle before the final read cycle (RD0). ESD Immunity Added section.
Write Cycle table: Added tAW, tCEH, and tWEH specifications to table. Changed tBW minimum time for the 66 speed option to 65 ns. Figure 28, Pseudo SRAM Write Cycle—WE# Control: Added tAW and tWEH to figure. Figure 29, Pseudo SRAM Write Cycle–CE#1ps Control: Added tCEH to figure.
Revision A+2 (July 21, 2003)
DC Characteristics
Zero Power Flash: Deleted selection.
Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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