Am75PDL191CHHa/ Am75PDL193CHHa
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 30897 Revision A
Amendment +1 Issue Date January 14, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am75PDL191CHHa/Am75PDL193CHHa
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced Versatile I/O Control and Dual Chip Enable Input plus, for Additional Code or Data Storage, 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memory and 64 Mbit (4 M x 16-Bit) CMOS Pseudo Static RAM DISTINCTIVE CHARACTERISTICS
For Code Storage: Am29PDL127H/Am29PDL129H Features
ARCHITECTURAL ADVANTAGES
■ 128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random locations within the page
■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
■ High Performance
— Page access times as fast as 30 ns — Random access times as fast as 70 ns
■ Dual Chip Enable inputs (PDL129 only)
— Two CE inputs control selection of each half of the memory space
■ Single power supply operation
— Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications
■ Power consumption (typical values at 10 MHz)
— 45 mA active read current — 25 mA program/erase current — 1 µA typical standby mode current
■ Simultaneous Read/Write Operation
— Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations
SOFTWARE FEATURES
■ Software command-set compatible with JEDEC 42.4 standard
— Backward compatible with Am29F and Am29LV families
■ FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations per device
■ CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
PDL127:
— — — — — — — — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank B: 48 Mbit (32 Kw x 96) Bank C: 48 Mbit (32 Kw x 96) Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 1A: 48 Mbit (32 Kw x 96) Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2B: 48 Mbit (32 Kw x 96)
■ Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program operations in other sectors of same bank
PDL129:
■ Unlock Bypass Program command
— Reduces overall programming time when issuing multiple program command sequences
■ SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 30897 Rev: A Amendment +1 Issue Date: January 14, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
ADVANCE HARDWARE FEATURES
■ Ready/Busy# pin (RY/BY#)
INFORMATION
— Pinout and software compatible with single-power-supply flash standard
— Provides a hardware method of detecting program or erase cycle completion
PERFORMANCE CHARACTERISTICS
■ High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million erase cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
■ WP#/ACC (Write Protect/Acceleration) input
— At VIL, hardware level protection for the first and last two 4K word sectors. — At VIH, allows removal of sector protection — At VHH, provides accelerated programming in a factory setting
■ Persistent Sector Protection
— A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level
■ Password Sector Protection
— A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
SOFTWARE FEATURES
■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow reading from other sectors in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences
FOR CODE OR DATA STORAGE: AM29DL640H ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations ■ Flexible BankTM architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. ■ Boot Sectors — Top and bottom boot sectors in the same device — Any combination of sectors can be erased ■ Manufactured on 0.13 µm process technology ■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: One-time programmable only. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Compatible with JEDEC standards
HARDWARE FEATURES
■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system
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ADVANCE
PSRAM FEATURES
■ Organization: 4 M x 16-Bit ■ Power Supply voltage of 2.7 to 3.1 V ■ Three state outputs ■ Compatible with Low Power SRAM ■ Deep Power Down: Memory Cell data hold invalid
INFORMATION
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ADVANCE
INFORMATION
GENERAL DESCRIPTION (PDL129)
The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows:
Chip Enable Configuration CE#f1 Control Bank 1A 48 Mbit (32 Kw x 96) Bank 1B 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE#f2 Control Bank 2A 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2B 48 Mbit (32 Kw x 96)
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
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ADVANCE
INFORMATION
GENERAL DESCRIPTION (PDL127)
The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#f1), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows:
Bank A B C D Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31)
microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard
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ADVANCE
INFORMATION
GENERAL DESCRIPTION (DL640)
The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, or 120 ns and is offered in 48-pin TSOP, 63-ball Fine-Pitch BGA, and 64-ball Fortified BGA packages. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Factory locked parts provide several options. The SecSi Sector m ay store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d va n t a g e c o m p a r e d t o s ys te m s w h e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection m easures include a low V CC d etector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation b y dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640H can be organized as both a top and bottom boot sector configuration.
Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 8 Mb 24 Mb 24 Mb 8 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword
Am29DL640H Features
The S ecSi™ (Secured Silicon) Sector i s an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Customer Indicator Bit (DQ6) is permanently set to a 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part.
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ADVANCE
INFORMATION
Pseudo SRAM Memory
The pSRAM device is a 64 Mbit pseudo static random access memory (PSRAM) organized as 4,194,304 words by 16 bits. The device operates a single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by CE1#, OE#, and WE# on anynchronous. The device also supports deep power-down mode, realizing low-power standby.
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ADVANCE
INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 11 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 12 Connection Diagram–PDL127 . . . . . . . . . . . . . . . 13 Special Package Handling Instructions .................................. 13 Connection Diagram–PDL129 . . . . . . . . . . . . . . . 14 Special Package Handling Instructions .................................. 14 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 16 Am29PDL127H/AM29PDL129H Device Bus Operations ....... 17
Table 1. Device Bus Operations ..................................................... 18
SecSi Sector Protection Bits ................................................ 46 Hardware Data Protection ...................................................... 46 Low VCC Write Inhibit ......................................................... 46 Write Pulse “Glitch” Protection ............................................ 46 Logical Inhibit ....................................................................... 46 Power-Up Write Inhibit ......................................................... 46 Common Flash Memory Interface (CFI) . . . . . . . 46
Table 12. CFI Query Identification String ........................................ 47 System Interface String................................................................... 47 Table 14. Device Geometry Definition ............................................ 48 Table 15. Primary Vendor-Specific Extended Query ...................... 49
Requirements for Reading Array Data ................................... 19 Random Read (Non-Page Read) ........................................ 19 Page Mode Read ................................................................ 19
Table 2. Page Select .......................................................................19
Simultaneous Operation ......................................................... 19
Table 3. Bank Select (PDL129H) ....................................................19 Table 4. Bank Select (PDL127H) ....................................................19
Writing Commands/Command Sequences ............................ 20 Accelerated Program Operation .......................................... 20 Autoselect Functions ........................................................... 20 Standby Mode ........................................................................ 20 Automatic Sleep Mode ........................................................... 20 RESET#: Hardware Reset Pin ............................................... 21 Output Disable Mode .............................................................. 21
Table 5. SecSiTM Sector Addresses ................................................21 Table 6. Am29PDL127H Sector Architecture ..................................22 Table 7. Am29PDL129H Sector Architecture ..................................29 Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................37 Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f1 Control ..................................................................................38 Table 10. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f2 Control ..................................................................................38
Command Definitions . . . . . . . . . . . . . . . . . . . . . 50 Reading Array Data ................................................................ 50 Reset Command ..................................................................... 50 Autoselect Command Sequence ............................................ 50 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 51 Word Program Command Sequence ...................................... 51 Unlock Bypass Command Sequence .................................. 51
Figure 4. Program Operation ......................................................... 52
Chip Erase Command Sequence ........................................... 52 Sector Erase Command Sequence ........................................ 52
Figure 5. Erase Operation.............................................................. 53
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 39 Persistent Sector Protection ................................................... 39 Persistent Protection Bit (PPB) ............................................ 39 Persistent Protection Bit Lock (PPB Lock) .......................... 39 Dynamic Protection Bit (DYB) ............................................. 39
Table 11. Sector Protection Schemes .............................................40
Erase Suspend/Erase Resume Commands ........................... 53 Password Program Command ................................................ 53 Password Verify Command .................................................... 54 Password Protection Mode Locking Bit Program Command .. 54 Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 54 SecSi Sector Protection Bit Program Command .................... 54 PPB Lock Bit Set Command ................................................... 54 DYB Write Command ............................................................. 54 Password Unlock Command .................................................. 55 PPB Program Command ........................................................ 55 All PPB Erase Command ........................................................ 55 DYB Write Command ............................................................. 55 PPB Lock Bit Set Command ................................................... 55 PPB Status Command ............................................................ 55 PPB Lock Bit Status Command .............................................. 55 Sector Protection Status Command ....................................... 55 Command Definitions Tables .................................................. 56
Table 16. Memory Array Command Definitions ............................. 56 Table 17. Sector Protection Command Definitions ........................ 57
Persistent Sector Protection Mode Locking Bit ................... 40 Password Protection Mode ..................................................... 40 Password and Password Mode Locking Bit ........................ 41 64-bit Password ................................................................... 41 Write Protect (WP#) ................................................................ 41 Persistent Protection Bit Lock .............................................. 41 High Voltage Sector Protection .............................................. 42
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 43
Write Operation Status . . . . . . . . . . . . . . . . . . . . 58 DQ7: Data# Polling ................................................................. 58
Figure 6. Data# Polling Algorithm .................................................. 58
RY/BY#: Ready/Busy# ............................................................ 59 DQ6: Toggle Bit I .................................................................... 59
Figure 7. Toggle Bit Algorithm........................................................ 59
Temporary Sector Unprotect .................................................. 44
Figure 2. Temporary Sector Unprotect Operation........................... 44
SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 44 Factory-Locked Area (64 words) ......................................... 44 Customer-Lockable Area (64 words) ................................... 44
Figure 3. PDL127H SecSi Sector Protection Algorithm .................. 45
DQ2: Toggle Bit II ................................................................... 60 Reading Toggle Bits DQ6/DQ2 ............................................... 60 DQ5: Exceeded Timing Limits ................................................ 60 DQ3: Sector Erase Timer ....................................................... 60
Table 18. Write Operation Status ................................................... 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 62
Figure 8. Maximum Negative Overshoot Waveform ...................... 62 Figure 9. Maximum Positive Overshoot Waveform........................ 62
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ADVANCE
INFORMATION
Figure 3. SecSi Sector Protect Verify............................................. 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10. Test Setup..................................................................... 64 Figure 11. Input Waveforms and Measurement Levels .................. 64
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 65 CE#1ps Timing ....................................................................... 65
Figure 12. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................. 65
Hardware Data Protection ...................................................... 89 Low VCC Write Inhibit ......................................................... 89 Write Pulse “Glitch” Protection ............................................ 89 Logical Inhibit ....................................................................... 89 Power-Up Write Inhibit ......................................................... 89 Common Flash Memory Interface (CFI) . . . . . . . 89
Table 7. CFI Query Identification String .......................................... 90 System Interface String................................................................... 90 Table 9. Device Geometry Definition .............................................. 91 Table 10. Primary Vendor-Specific Extended Query ...................... 92
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66 Read-Only Operations – Am29PDL127H ............................... 66 Read-Only Operations – Am29PDL129H ............................... 66
Figure 13. Read Operation Timings ................................................ 67 Figure 14. Page Read Operation Timings....................................... 67
Hardware Reset (RESET#) .................................................... 68
Figure 15. Reset Timings ................................................................ 68
Erase and Program Operations .............................................. 69
Figure 16. Program Operation Timings........................................... 70 Figure 17. Accelerated Program Timing Diagram........................... 70 Figure 18. Chip/Sector Erase Operation Timings ........................... 71 Figure 19. Back-to-back Read/Write Cycle Timings ....................... 72 Figure 20. Data# Polling Timings (During Embedded Algorithms).. 72 Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 73 Figure 22. DQ2 vs. DQ6.................................................................. 73
Command Definitions . . . . . . . . . . . . . . . . . . . . . 93 Reading Array Data ................................................................ 93 Reset Command ..................................................................... 93 Autoselect Command Sequence ............................................ 93 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 93 Word Program Command Sequence ...................................... 94 Unlock Bypass Command Sequence .................................. 94
Figure 4. Program Operation ......................................................... 95
Chip Erase Command Sequence ........................................... 95 Sector Erase Command Sequence ........................................ 95
Figure 5. Erase Operation.............................................................. 96
Temporary Sector Unprotect .................................................. 74
Figure 23. Temporary Sector Unprotect Timing Diagram ............... 74 Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 75
Erase Suspend/Erase Resume Commands ........................... 96
Table 11. Am29DL640H Command Definitions .............................. 97
Alternate CE# Controlled Erase and Program Operations ..... 76
Figure 25. Flash Alternate CE# Controlled Write (Erase/Program) Operation Timings........................................................................... 77
Write Operation Status . . . . . . . . . . . . . . . . . . . . 98 DQ7: Data# Polling ................................................................. 98
Figure 6. Data# Polling Algorithm .................................................. 98
Erase And Programming Performance . . . . . . . . 78 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 78 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 78 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 78 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 79
Table 1. Am29DL640H Device Bus Operations ..............................79
RY/BY#: Ready/Busy# ............................................................ 99 DQ6: Toggle Bit I .................................................................... 99
Figure 7. Toggle Bit Algorithm........................................................ 99
DQ2: Toggle Bit II ................................................................. 100 Reading Toggle Bits DQ6/DQ2 ............................................. 100 DQ5: Exceeded Timing Limits .............................................. 100 DQ3: Sector Erase Timer ..................................................... 100
Table 12. Write Operation Status ................................................. 101
Word/Byte Configuration ........................................................ 79 Requirements for Reading Array Data ................................... 79 Writing Commands/Command Sequences ............................ 80 Accelerated Program Operation .......................................... 80 Autoselect Functions ........................................................... 80 Simultaneous Read/Write Operations with Zero Latency ....... 80 Standby Mode ........................................................................ 80 Automatic Sleep Mode ........................................................... 80 RESET#: Hardware Reset Pin ............................................... 81 Output Disable Mode .............................................................. 81
Table 2. Am29DL640H Sector Architecture ....................................81 Table 3. Bank Address ....................................................................84 SecSiTM Sector Addresses.............................................................. 84
Absolute Maximum Ratings . . . . . . . . . . . . . . . 102
Figure 8. Maximum Negative Overshoot Waveform .................... 102 Figure 9. Maximum Positive Overshoot Waveform...................... 102
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........................................................... 104 Figure 11. Typical ICC1 vs. Frequency .......................................... 104
pSRAM DC Characteristics . . . . . . . . . . . . . . . . 105 Recommended DC Operating Conditions (Note 1) .............. 105 Capacitance (f= 1MHz, TA = 25×C) ..................................... 105 DC and Operating Characteristics ........................................ 105 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 12. Test Setup.................................................................. 106 Figure 13. Input Waveforms and Measurement Levels ............... 106
Autoselect Mode ..................................................................... 84 Sector/Sector Block Protection and Unprotection .................. 85
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................85
PSRAM AC Characteristics . . . . . . . . . . . . . . . . 107 CE#s Timing ......................................................................... 107
Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash................................................. 107 Figure 15. Timing Waveform of Power-up ................................... 107
Write Protect (WP#) ................................................................ 85
Table 6. WP#/ACC Modes ..............................................................86
Temporary Sector Unprotect .................................................. 86
Figure 1. Temporary Sector Unprotect Operation........................... 86 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 87
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108 Read-Only Operations ......................................................... 108
Figure 16. Read Operation Timings ............................................. 108
SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 88
Hardware Reset (RESET#) .................................................. 109
Figure 17. Reset Timings ............................................................. 109
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
9
ADVANCE
INFORMATION pSRAM AC CHaracteristics . . . . . . . . . . . . . . . . 120 Functional Description .......................................................... 120 Absolute Maximum Ratings .................................................. 120
Figure 28. Standby Mode State Machines ................................... 121
Erase and Program Operations ............................................ 110
Figure 18. Program Operation Timings......................................... 111 Figure 19. Accelerated Program Timing Diagram......................... 111 Figure 20. Chip/Sector Erase Operation Timings ......................... 112 Figure 21. Back-to-back Read/Write Cycle Timings ..................... 113 Figure 22. Data# Polling Timings (During Embedded Algorithms) 113 Figure 23. Toggle Bit Timings (During Embedded Algorithms)..... 114 Figure 24. DQ2 vs. DQ6................................................................ 114
Standby Mode Characteristic ................................................ 121 AC Characteristics (VCC= 2.7-3.1 V, TA= -40 to 85×C) ....... 121 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 29. Timing Waveform of Read Cycle 1 ............................. Figure 30. Timing Waveform of Read Cycle 2 ............................. Figure 31. Timing Waveform of Write Cycle 1 ............................. Figure 32. Timing Waveform of Write Cycle 2 ............................. Figure 33. Timing Waveform of Write Cycle 3 ............................. 122 122 123 123 124
Temporary Sector Unprotect ................................................ 115
Figure 25. Temporary Sector Unprotect Timing Diagram ............. 115 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................ 116
Alternate CE# Controlled Erase and Program Operations ... 117
Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings......................................................................... 118
Erase And Programming Performance . . . . . . . 119 Latchup Characteristics . . . . . . . . . . . . . . . . . . 119
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . 125 FMB073—73-Ball Fine-Pitch Grid Array 9 x 13 mm ............. 125 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . 126
10
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) 30 VCC, VIO = 2.7–3.1 V Am29PDL129H 70 70
Part Number Speed Option Max Access Time (ns), tACC CE# Access (ns), tCE OE# Access (ns), tOE Standard Voltage Range: VCC = 2.7–3.1 V
Am29DL640H 70 70 70 30
Part Number Speed Option Standard Voltage Range: VCC = 2.7–3.1 V Max Access Time, ns (tACC) pSRAM Max CE# Access, ns (tCE) Max OE# Access, ns (tOE)
pSRAM 70 70 30
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
11
ADVANCE
INFORMATION
MCP BLOCK DIAGRAM
VCC A0 to A21 (A22 PDL127 Only)
VSS
A0 to A21 (A22)
CE#f1 CE#f2
Am29PDL127H or Am29PDL129H VIO = VCC
DQ0 to DQ15 DQ0 to DQ15
VCC
VSS
A0 to A21 WP#/ACC OE# CE#f3 WE# RESET# Am29DL640G DQ0 to DQ15
VSS VSSA A0 to A21 64 Mb pSRAM VCC = VCCQ
CE#1ps CE2ps UB# LB#
DQ0 to DQ15
VCC VSSQ
VCCps
12
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
CONNECTION DIAGRAM–PDL127
73-Ball FBGA Top View
A1
NC
A10
NC
DL640G Only Pseudo SRAM Only Flash Shared Only
B1
NC
B5
CE#f3
B6
NC
B10
NC
C1
NC
C3
A7
C4 D4
UB#
C5 D5 E5
RY/BY#
C6 D6 E6
A20
C7
A8
C8
A11
LB# WP#/ACC WE#
D2
A3
D3
A6
D7
A19
D8
A12
D9
A15
PDL127H Only
RESET# CE2ps
E2
A2
E3
A5
E4
A18
E7
A9
E8
A13
E9
A21
F1
NC
F2
A1
F3
A4
F4
A17
F7
A10
F8
A14
F9
A22
F10
NC
G1
NC
G2
A0
G3
VSS
G4
DQ1
G7
DQ6
G8
NC
G9
A16
G10
NC
H2
CE#f1
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
NC
J2
CE#1ps
J3
DQ0
J4
DQ10
J5
VCCf
J6
VCCps
J7
DQ12
J8
DQ7
J9
VSS
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8
DQ14
L1
NC
L5
NC
L6
NC
L10
NC
M1
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged periods of time.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
13
ADVANCE
INFORMATION
CONNECTION DIAGRAM–PDL129
73-Ball FBGA Top View
A1
NC
A10
NC
DL640G Only
B1
NC
B5
CE#f3
B6
NC
B10
NC
Pseudo SRAM Only Flash Shared Only
C1
NC
C3
A7
C4 D4
UB#
C5 D5 E5
RY/BY#
C6 D6 E6
A20
C7
A8
C8
A11
LB# WP#/ACC WE#
D2
A3
D3
A6
D7
A19
D8
A12
D9
A15
PDL129 Only
RESET# CE2ps
E2
A2
E3
A5
E4
A18
E7
A9
E8
A13
E9
A21
F1
NC
F2
A1
F3
A4
F4
A17
F7
A10
F8
A14
F9
CE#f2
F10
NC
G1
NC
G2
A0
G3
VSS
G4
DQ1
G7
DQ6
G8
NC
G9
A16
G10
NC
H2
CE#f1
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
NC
J2
CE#1ps
J3
DQ0
J4
DQ10
J5
VCCf
J6
VCCps
J7
DQ12
J8
DQ7
J9
VSS
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8
DQ14
L1
NC
L5
NC
L6
NC
L10
NC
M1
NC
M10
NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
14
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION WP/ACC#= 12V, program and erase operations are accelerated. VCCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = pSRAM Power Supply = Device Ground (Common) = Pin Not Connected Internally
PIN DESCRIPTION
A21–A0 A22 DQ15–DQ0 CE#f1 = 22 Address Inputs (Common) = Address Input (PDL127 only) (Flash) = 16 Data Inputs/Outputs (Common) = Chip Enable 1 (Flash) (PDL 127 only) VCCs VSS NC
CE#f1, CE#f2 = Chip Enable Inputs. CE#f1 controls the 64 Mb in Banks 1A and 1B. CE#f2 controls the 64 Mb in Banks 2A and 2B. CE#1ps CE2ps OE# WE# RY/BY# = Chip Enable 1 (pSRAM) (PDL129 only) = Chip Enable 2 (pSRAM) = Output Enable (Common) = Write Enable (Common) = Ready/Busy Output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. = Upper Byte Control (pSRAM) = Lower Byte Control (pSRAM) = Hardware Reset Pin, Active Low = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When
LOGIC SYMBOL
22 A21–A0
A22 (PDL127 Only) DQ15–DQ0 CE#f2 (PDL129 Only) CE#1ps CE2ps OE# WE# WP#/ACC RESET# UB#s LB#s RY/BY# CE#f1 16
UB#s LB#s RESET# WP#/ACC
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
15
ADVANCE
INFORMATION
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am75PDL19 1 C H HA 70 I
TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5. SECOND PSRAM SUPPLIER PROCESS TECHNOLOGY OF AM29DL640 H = 0.13 µm PROCESS TECHNOLOGY OF AM29PDL127/129 H = 0.13 µm PSEUDO SRAM DEVICE DENSITY C = 64 Mbits CONTROL PINS 1 = 1 CE Flash 3 = 2 CE Flash AMD DEVICE NUMBER/DESCRIPTION Am75PDL191CHHa/Am75PDL193CHHa Am29PDL127H/129H–128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory, One Chip Enable Input on Am29PDL127H, Dual Chip Enable Inputs on Am29PDL129H Am29DL640H–64 Megabit (4M x 16-Bit) CMOS Flash Memory 64 Mb pSRAM
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations for BGA Packages
Order Number Package Marking VIO Range
Am75PDL191CHHA70I Am75PDL193CHHA70I
M750000004 M750000005
2.7–3.1 V 2.7–3.1 V
16
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
Am29PDL127H/AM29PDL129H Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
17
ADVANCE Table 1.
Operation (Notes 1, 2)
Read from Active Flash Write to Active Flash Standby Deep Power-down Standby Output Disable (Note 9) Flash Hardware (Note 7) Reset (Note 8) (Note 7) Sector Protect (Notes 6, 10) (Note 9) (Note 7) (Note 8) (Note 7) (Note 8) X L (H) H (L) L (H) H (L) (Note 7) (Note 8) (Note 7) (Note 8)
INFORMATION
Device Bus Operations
Addr. LB#s UB#s WP#/ (Note (Note RESET# ACC 3) 3) (Note 4)
X X H L/H
CE#f2 CE#f1 (PDL129 CE#1ps CE2ps OE# WE# Active only)
L (H) H (L) H H H H H H L H H H H H H H H H L H L H L H H L H L H L H L X X H L H L L H
DQ7– DQ0
DOUT DIN High-Z High-Z High-Z
DQ15– DQ8
DOUT DIN High-Z High-Z High-Z
AIN AIN X X X X X SADD, A6 = L, A1 = H, A0 = L SADD, A6 = H, A1 = H, A0 = L X
L (H)
H (L)
H X X H H X
L X X H H X
X X X X X X
X X X X X X
H VCC ± 0.3 V VCC ± 0.3 V H
(Note 4)
H H L/H
VCC ± 0.3 V VCC ± 0.3 V L (H) H (L)
X
L
L/H
High-Z
High-Z
X
X
VID
L/H
DIN
X
Sector Unprotect (Notes 5, 9) Temporary Sector Unprotect
X
X
VID
(Note 6)
DIN
X
X L
X L L H L L H
VID
(Note 6)
DIN DOUT
High-Z DOUT DOUT High-Z DIN DIN High-Z
Read from pSRAM
H
H
L
H
L
H
AIN
H L L
H
X
High-Z DOUT DIN
Write to pSRAM
H
H
L
H
X
L
AIN
H L
H
X
High-Z DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f1 or 2 = VIL, CE#1ps = VIL and CE2ps = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM.
9. Both CE#f1 inputs may be held low for this operation.
18
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION page mode accesses are obtained by keeping A22–A3 (A21–A3 for PDL129) constant and changing A2 to A0 to select the specific word within that page.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE#f1/CE#f2 (PDL129 only) pins to VIL. CE#f1 and CE#f2 are the power control and for PDL129 select the lower (CE#f1) or upper (CE#f2) halves of the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Characteristics table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE#f1 to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits A22–A3 (A21–A3 for PDL129) select an 8-word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC o r tCE a nd subsequent page read accesses (as long as the locations specified by the microprocessor fall within that page) are t PACC. When CE#f1 and CE#f2 (PDL129 only) are deasserted (CE#f1=CE#f2=VIH), the reassertion of CE#f1 or CE#f2 (PDL129 only) for subsequent access has access time of t ACC o r t CE . Here again, CE#f1/CE#f2 (PDL129 only) selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast
Table 2.
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Page Select
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Simultaneous Operation
In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank addresses (A22–A20) (A21–A20 for PDL129) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 3.
Bank Bank 1A Bank 1B Bank 2A Bank 2B CE#f1 0 0 1 1
Bank Select (PDL129H)
CE#f2 1 1 0 0 A21–A20 00, 01, 10 11 00 01, 10, 11
Table 4.
Bank Bank A Bank B Bank C Bank D
Bank Select (PDL127H)
A22–A20 000 001, 010, 011 100, 101, 110 111
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
19
ADVANCE
INFORMATION Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Command Sequence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL 129 only) to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f1, CE#f2 (PDL129 only) and RESET# pins are all held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f1, CE#f2 (PDL129 only), and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 i n the DC Characteristics table represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#f1/CE#f2 (PDL129 only), WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.
20
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY ( not during Embedded Algorithms). The system can read data tRH a fter the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Table 5.
Am29PDL127H/ Am29PDL129H Factory-Locked Area Customer-Lockable Area
SecSiTM Sector Addresses
Sector Size 128 words 64 words 64 words Address Range 000000h–00007Fh 000000h-00003Fh 000040h-00007Fh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
21
ADVANCE Table 6.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank A SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
INFORMATION
Am29PDL127H Sector Architecture
Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh
Sector Address (A22-A12) 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
22
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 6.
Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
23
ADVANCE Table 6.
Bank Sector SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank B SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 01001000XXX 01001001XXX 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh
24
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 6.
Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 Bank B SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank C SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 01110000XXX 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh 400000h–407FFFh 408000h–40FFFFh 410000h–417FFFh 418000h–41FFFFh 420000h–427FFFh 428000h–42FFFFh 430000h–437FFFh 438000h–43FFFFh 440000h–447FFFh 448000h–44FFFFh 450000h–457FFFh 458000h–45FFFFh 460000h–467FFFh 468000h–46FFFFh 470000h–477FFFh 478000h–47FFFFh 480000h–487FFFh 488000h–48FFFFh 490000h–497FFFh 498000h–49FFFFh 4A0000h–4A7FFFh 4A8000h–4AFFFFh 4B0000h–4B7FFFh 4B8000h–4BFFFFh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
25
ADVANCE Table 6.
Bank Sector SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 Bank C SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX 10111111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 4C0000h–4C7FFFh 4C8000h–4CFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 4F0000h–4F7FFFh 4F8000h–4FFFFFh 500000h–507FFFh 508000h–50FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 530000h–537FFFh 538000h–53FFFFh 540000h–547FFFh 548000h–54FFFFh 550000h–557FFFh 558000h–15FFFFh 560000h–567FFFh 568000h–56FFFFh 570000h–577FFFh 578000h–57FFFFh 580000h–587FFFh 588000h–58FFFFh 590000h–597FFFh 598000h–59FFFFh 5A0000h–5A7FFFh 5A8000h–5AFFFFh 5B0000h–5B7FFFh 5B8000h–5BFFFFh 5C0000h–5C7FFFh 5C8000h–5CFFFFh 5D0000h–5D7FFFh 5D8000h–5DFFFFh 5E0000h–5E7FFFh 5E8000h–5EFFFFh 5F0000h–5F7FFFh 5F8000h–5FFFFFh
26
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 6.
Bank Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank C SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 600000h–607FFFh 608000h–60FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh 670000h–677FFFh 678000h–67FFFFh 680000h–687FFFh 688000h–68FFFFh 690000h–697FFFh 698000h–69FFFFh 6A0000h–6A7FFFh 6A8000h–6AFFFFh 6B0000h–6B7FFFh 6B8000h–6BFFFFh 6C0000h–6C7FFFh 6C8000h–6CFFFFh 6D0000h–6D7FFFh 6D8000h–6DFFFFh 6E0000h–6E7FFFh 6E8000h–6EFFFFh 6F0000h–6F7FFFh 6F8000h–6FFFFFh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
27
ADVANCE Table 6.
Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 Bank D SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
INFORMATION
Am29PDL127H Sector Architecture (Continued)
Sector Address (A22-A12) 11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range (x16) 700000h–707FFFh 708000h–70FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h–76FFFFh 770000h–777FFFh 778000h–77FFFFh 780000h–787FFFh 788000h–78FFFFh 790000h–797FFFh 798000h–79FFFFh 7A0000h–7A7FFFh 7A8000h–7AFFFFh 7B0000h–7B7FFFh 7B8000h–7BFFFFh 7C0000h–7C7FFFh 7C8000h–7CFFFFh 7D0000h–7D7FFFh 7D8000h–7DFFFFh 7E0000h–7E7FFFh 7E8000h–7EFFFFh 7F0000h–7F7FFFh 7F8000h–7F8FFFh 7F9000h–7F9FFFh 7FA000h–7FAFFFh 7FB000h–7FBFFFh 7FC000h–7FCFFFh 7FD000h–7FDFFFh 7FE000h–7FEFFFh 7FF000h–7FFFFFh
28
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 7.
Bank Sector SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 Bank 1A SA1-18 SA1-19 SA1-20 SA1-21 SA1-22 SA1-23 SA1-24 SA1-25 SA1-26 SA1-27 SA1-28 SA1-29 SA1-30 SA1-31 SA1-32 SA1-33 SA1-34 SA1-35 SA1-36 SA1-37 CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INFORMATION
Am29PDL129H Sector Architecture
CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21-A12) 0000000XXX 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
29
ADVANCE Table 7.
Bank Sector SA1-38 SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 Bank 1A SA1-57 SA1-58 SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 SA1-67 SA1-68 SA1-69 SA1-70 SA1-71 SA1-72 SA1-73 SA1-74 SA1-75 SA1-76 SA1-77
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21-A12) 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh
CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
30
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 7.
Bank Sector SA1-78 SA1-79 SA1-80 SA1-81 SA1-82 SA1-83 SA1-84 SA1-85 Bank 1A SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21-A12) 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh
CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
31
ADVANCE Table 7.
Bank Sector SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 SA1-103 SA1-104 SA1-105 SA1-106 SA1-107 SA1-108 SA1-109 SA1-110 SA1-111 SA1-112 SA1-113 Bank 1B SA1-114 SA1-115 SA1-116 SA1-117 SA1-118 SA1-119 SA1-120 SA1-121 SA1-122 SA1-123 SA1-124 SA1-125 SA1-126 SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21-A12) 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range (x16) 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh
CE#f1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 7.
Bank Sector SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 SA2-16 SA2-17 Bank 2A SA2-18 SA2-19 SA2-20 SA2-21 SA2-22 SA2-23 SA2-24 SA2-25 SA2-26 SA2-27 SA2-28 SA2-29 SA2-30 SA2-31 SA2-32 SA2-33 SA2-34 SA2-35 SA2-36 SA2-37 SA2-38
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21-A12) 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh
CE#f1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
33
ADVANCE Table 7.
Bank Sector SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 SA2-57 Bank 2B SA2-58 SA2-59 SA2-60 SA2-61 SA2-62 SA2-63 SA2-64 SA2-65 SA2-66 SA2-67 SA2-68 SA2-69 SA2-70 SA2-71 SA2-72 SA2-73 SA2-74 SA2-75 SA2-76 SA2-77 SA2-78
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21-A12) 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh
CE#f1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
34
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 7.
Bank Sector SA2-79 SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 Bank 2B SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 SA2-108 SA2-109 SA2-110 SA2-111 SA2-112 SA2-113 SA2-114 SA2-115 SA2-116 SA2-117 SA2-118
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21-A12) 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh
CE#f1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
35
ADVANCE Table 7.
Bank Sector SA2-119 SA2-120 SA2-121 SA2-122 SA2-123 SA2-124 SA2-125
Bank 2B
INFORMATION
Am29PDL129H Sector Architecture (Continued)
CE#f2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21-A12) 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh
CE#f1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134
36
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
Sector SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151-SA154 SA155-SA158 SA159-SA162 SA163-SA166 SA167-SA170 SA171-SA174 SA175-SA178 SA179-SA182 SA183-SA186 SA187-SA190 SA191-SA194 SA195-SA198 SA199-SA202 SA203-SA206 SA207-SA210 SA211-SA214 SA215-SA218 SA219-SA222 SA223-SA226 SA227-SA230 SA231-SA234 SA235-SA238 SA239-SA242 SA243-SA246 SA247-SA250 SA251-SA254 SA255-SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 A22-A12 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111 Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
37
ADVANCE
INFORMATION Table 10. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f2 Control
Sector Group
SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 - SA2-14 SA2-15 - SA2-18 SA2-19 - SA2-22 SA2-23 - SA2-26 SA2-27 - SA2-30 SA2-31 - SA2-34 SA2-35 - SA2-38 SA2-39 - SA2-42 SA2-43 - SA2-46 SA2-47 - SA2-50 SA2-51 - SA2-54 SA2-55 - SA2-58 SA2-59 - SA2-62 SA2-63 - SA2-66 SA2-67 - SA2-70 SA2-71 - SA2-74 SA2-75 - SA2-78 SA2-79 - SA2-82 SA2-83 - SA2-86 SA2-87 - SA2-90 SA2-91 - SA2-94 SA2-95 - SA2-98 SA2-99 - SA2-102 SA2-103 - SA2-106 SA2-107 - SA2-110 SA2-111 - SA2-114 SA2-115 - SA2-118 SA2-119 - SA2-122 SA2-123 - SA2-126 SA2-127 - SA2-130 SA2-131 - SA2-134
Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f1 Control Sector Group
SA1-0–SA1-3 SA1-4–SA1-7 SA1-8–SA1-11 SA1-12–SA1-15 SA1-16–SA1-19 SA1-20–SA1-23 SA1-24–SA1-27 SA1-28–SA1-31 SA1-32–SA1-35 SA1-36–SA1-39 SA1-40–SA1-43 SA1-44–SA1-47 SA1-48–SA1-51 SA1-52–SA1-55 SA1-56–SA1-59 SA1-60–SA1-63 SA1-64–SA1-67 SA1-68–SA1-71 SA1-72–SA1-75 SA1-76–SA1-79 SA1-80–SA1-83 SA1-84–SA1-87 SA1-88–SA1-91 SA1-92–SA1-95 SA1-96–SA1-99 SA1-100–SA1-103 SA1-104–SA1-107 SA1-108–SA1-111 SA1-112–SA1-115 SA1-116–SA1-119 SA1-120–SA1-123 SA1-124 SA1-125 SA1-126 SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134
A21-12
00000XXXXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector/Sector Block Size
128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
A21-12
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 11111XXXXX
Sector/Sector Block Size
4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
38
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
SECTOR PROTECTION
The Am50PDL191CH/Am50PDL193CH features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: ■ Dynamically Locked—The sector is protected and can be changed by a simple command. ■ Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the par ts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does 39
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted.
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. The WP# Hardware Protection feature is always available, regardless of which of the other two methods are chosen.
Selecting a Sector Protection Mode
The device defaults to the Persistent Sector Protection mode. However, to prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode, it is recommended that either of two one-time programmable non-volatile bits that permanently define which sector protection method be set before the device is first programmed. The Persistent Sector Protection Mode Locking Bit p ermanently sets the device to the Persistent Sector Protection mode. The Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Command Sequence for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection method in previous AMD flash devices. This new method provides three different sector protection states: ■ Persistently Locked—The sector is protected and cannot be changed.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
ADVANCE
INFORMATION Table 11. Sector Protection Schemes
PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable
n ot prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL.
DYB 0 0 0 1 1 0 1 1
PPB 0 0 1 0 1 1 0 1
Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable
Table 11 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a g i v e n s e c t o r c a n b e ve r i f i e d b y w r i t i n g a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differ-
40
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.
e nces between the Persistent Sector Protection and the Password Sector Protection Mode: ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
41
ADVANCE
INFORMATION
If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID ) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
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INFORMATION
START PLSCNT = 1 RESET# = VID Wait 4 µs Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 µs
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A7-A0 = 00000010 Set up next sector address
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes Remove VID from RESET#
Data = 00h? Yes
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Yes Remove VID from RESET#
No
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms
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ADVANCE
INFORMATION tection mode and Password Protection mode. It uses i nd i cato r bi ts ( D Q6 , D Q7 ) to in di ca te the factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory-Locked Area (64 words)
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
T h e fa c t o r y - l o cke d a r e a o f t h e S e c S i S e c t o r (000000h-00003Fh) is locked when the par t is shipped, whether or not the area was programmed at the factory. The SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. AMD offers the ExpressFlash service to program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only AMD can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact an AMD representative for details on using AMD’s ExpressFlash service. N ote that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Customer-Lockable Area (64 words) The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: ■ Follow the in-system sector protect algorithm as shown in Figure 3. This allows in-system protection of the Secsi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector.
Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 268, 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129.will remain protected). 2. All previously protected sectors are protected once again.
Figure 2.
Temporary Sector Unprotect Operation
SecSi™ (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Pro-
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INFORMATION
START
SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to address 555h
SecSi Sector Entry
SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to address 555h
PLSCNT = 1
Protect SecSi Sector: write 68h to sector address with A7–A0 = 00011010
Time out 256 µs
SecSi Sector Protection
Increment PLSCNT
Verify SecSi Sector: write 48h to sector address with A7–A0 = 00011010
Read from sector address with A7–A0 = 00011010 No No PLSCNT = 25? Data = 01h?
Yes Device Failed
Yes SecSi Sector Protection Completed
SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h
SecSi Sector Exit
Figure 3.
PDL127H SecSi Sector Protection Algorithm
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INFORMATION write cycle, CE#f1/CE#f2 and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f1 = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12–15. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12–15. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC i s greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#f1, CE#f2 or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = V IL, CE#f1 =CE#f2 = VIH o r WE# = VIH . To initiate a
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ADVANCE Table 12.
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
INFORMATION
CFI Query Identification String
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 13.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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ADVANCE Table 14.
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
INFORMATION
Device Geometry Definition
Description
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
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Am75PDL191CHHa/Am75PDL193CHHa
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ADVANCE Table 15.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 000Ch
INFORMATION
Primary Vendor-Specific Extended Query
Description
Query-unique ASCII string “PRI” Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
0002h 0001h 0001h 0007h 00E7h 0000h 0002h 0085h
Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag
4Eh
0095h
4Fh
0001h
00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4
50h
0001h
57h
0004h
58h
0027h
59h
0060h
5Ah
0060h
5Bh
0027h
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INFORMATION
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 16 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens later. All data is latched on the rising edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens first. Refer to the AC Characteristics section for timing diagrams. erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur ns th a t ba nk to the e ra s e- s us pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding ban k enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the MCP Device Bus Operations section for more information. The Read-Only Operations – Am29PDL127H and Read-Only Operations – Am29PDL127H tables provide the read parameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 16 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before
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ADVANCE
INFORMATION Programming is allowed in any sequence and across sector boundaries. A b it cannot be programmed from “0” back to a “1.” A ttempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 16 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH a ny operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figures 16 and 17 for timing diagrams.
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 16 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. N ote that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 16 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity.
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ADVANCE
INFORMATION
START
the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command.Table 16 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de-
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 16 for program command sequence.
Figure 4.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 16 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. N ote that
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ADVANCE
INFORMATION period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 5.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Four Password Program commands are required to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion
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INFORMATION
of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
SecSi Sector Protection Bit Program Command
The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. E xiting the VCC -level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode).
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits A22-A12 for PDL127 and (A21–A12) for PDL129H are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command.
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INFORMATION determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µ s execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written.
A fter programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The PPB Program command does not follow the Embedded Program algorithm.
PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to
Sector Protection Status Command
The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.
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INFORMATION
Command Definitions Tables
Table 16.
Command (Notes) Read (5) Reset (6) Manufacturer ID Device ID (10) Autoselect (Note 7) SecSi Sector Factory Protect (8) Sector Group Protect Verify (9) Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) CFI Query (13) Accelerated Program (15) Unlock Bypass Entry (15) Unlock Bypass Program (15) Unlock Bypass Erase (15) Unlock Bypass CFI (13, 15) Unlock Bypass Reset (15) Cycles
Memory Array Command Definitions
Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data
Addr Data Addr Data Addr Data RA XXX 555 555 555 555 555 555 555 BA BA 55 XX 555 XX XX XX XXX RD F0 AA AA AA AAA AA AA AA B0 30 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 90 90 90 90 A0 80 80
1 1 4 6 4 4 4 6 6 1 1 1 2 3 2 2 1 2
(BA)X00 (BA)X01 X03 (SA)X02 PA 555 555
01 7E (see note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X0E (Note 10) (BA)X0F 00
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A22:A20, (A21:A20 for PDL129) see Tables 4 and 5 for more detail. PA = Program Address (A22:A0) (A21:A0 for PDL129). Addresses latch on falling edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information.
RA = Read Address (A22:A0) (A21:A0 for PDL129). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A22:A12) (A21:A12 for PDL129) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care
8. The data is C0h for factory or customer locked and 80h for factory locked. 9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. 20 for Am29PDL127H and 21 for Am29PDL129H. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array.
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ADVANCE Table 17.
Command (Notes) Reset SecSi Sector Exit SecSi Protection Bit Program (5, 6) SecSi Protection Bit Status Cycles Addr Data Addr Data F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 88 90 60 60 38 C8 28 60 60 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL XX OW OW Addr
INFORMATION
Sector Protection Command Definitions
Bus Cycles (Notes 1-4) Data Addr Data Addr Data Addr Data Addr Data
1 XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 4 6 5
SecSi Sector Entry 3
00 68 48 PD[0-3] PWD[0-3] PWD[0] 68 48 60 PWA[1] (SA)WP (SA)WP (SA) PWD[1] 48 RD (0) 40 (SA)WP RD(0) PWA[2] (SA)WP PWD[2] RD(0) PWA[3] PWD[3] OW OW 48 RD(0) OW RD(0)
Password Program 4 (5, 7, 8) Password Verify (6, 4 8, 9) Password Unlock (7, 10, 11) 7
XX[0-3] PWA[0-3] PWA[0] (SA)WP (SA)WP WP
PPB Program (5, 6, 6 12, 17) PPB Status All PPB Erase (5, 6, 13, 14) PPB Lock Bit Set (17) PPB Lock Bit Status (15) DYB Write (7) DYB Erase (7) PPMLB Program (5, 6, 12) PPMLB Status (5) SPMLB Program (5, 6, 12) SPMLB Status (5) 5 6 3 4 4 4
RD(1) X1 X0 RD(0) 68 48 68 48 PL PL SL SL 48 RD(0) 48 RD(0) SL RD(0) PL RD(0)
DYB Status (6, 18) 4 6 5 6 5
Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits A21:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) (NoteTable.16 30897a1.fm) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For PDL128G and PDL640G, the WP address is 0111010. The EP address (PPB Erase Address) is 1111010. 17. Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary.
1.
See Table 1 for description of bus operations. 2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password. 9. Command sequence returns FFh if PPMLB is set.
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INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles. Table 18 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. Figure 6 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has comSTART
Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
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ADVANCE
INFORMATION DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 18 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 18 shows the outputs for RY/BY#.
START
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f1 to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.
Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7–DQ0) Address = VA
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7.
Toggle Bit Algorithm
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ADVANCE
INFORMATION The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f1 to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” O nly an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits.
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ADVANCE Table 18.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
INFORMATION Write Operation Status
Standard Mode Erase Suspend Mode
DQ7 (Note 2) DQ7# 0 1 Data DQ7#
DQ6 Toggle Toggle No toggle Data Toggle
DQ5 (Note 1) 0 0 0 Data 0
DQ3 N/A 1 N/A Data N/A
DQ2 (Note 2) No toggle Toggle Toggle Data N/A
RY/BY# 0 0 1 1 0
Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . –40°C to +85°C Voltage with Respect to Ground VCCf, VCCs (Note 1) . . . . . . . . . . . . –0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS t o –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins RESET#, and WP# /ACC is –0 .5 V. D ur ing volt age trans itions, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
+0.8 V –0.5 V –2.0 V 20 ns 20 ns 20 ns
Figure 8. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 9. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VCCf/VCCs Supply Voltages VCCf/VCCs for standard voltage range . . 2.7 V to 3.1 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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ADVANCE
INFORMATION
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VHH VID VOL VOH VLKO Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes Table.1 30897a1.fm, 2, 3) VCC Active Write Current (Notes Table.1 30897a1.fm, 3, 4) VCC Standby Current (Note 3) VCC Reset Current (Note 3) Automatic Sleep Mode (Notes 3, 5) VCC Active Read-While-Program Current (Notes 1, 2, 3) VCC Active Read-While-Erase Current (Notes 1, 2, 3) VCC Active Program-While-EraseSuspended Current (Notes 1, 3, 6) Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 6) Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE#f1, CE#f2 (PDL129 only), RESET#, WP/ACC# = VIO ± 0.3 V RESET# = VSS ± 0.3 V, CE# = VSS VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V, CE# = VSS OE# = VIH OE# = VIH OE# = VIH VIO = 2.7–3.6 V VIO = 2.7–3.6 V VCC = 3.0 V ± 10% VCC = 3.0 V ± 10% IOL = 2.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min 2.4 2.3 2.5 –0.5 2.0 8.5 11.5 Word Word 5 MHz 10 MHz 20 45 15 1 1 1 21 21 17 Min Typ Max ±1.0 35 35 ±1.0 30 55 25 5 5 5 45 45 25 0.8 VCC+0.3 9.5 12.5 0.4 Unit µA µA µA µA mA mA µA µA µA mA mA mA V V V V V V V
Notes: 1. Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2= VIL) 2. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 µA.
6. Not 100% tested.
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INFORMATION
TEST CONDITIONS
Table 19.
3.1 V 2.7 kΩ Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 kΩ Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
70 1 TTL gate 70 5 0.0–3.0 1.5 1.5 pF ns V V V Unit
Device Under Test
Note: Diodes are IN3064 or equivalent
Figure 10.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
KS000010-PAL
3.0 V 0.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
Figure 11.
Input Waveforms and Measurement Levels
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INFORMATION
pSRAM AC CHARACTERISTICS CE#1ps Timing
Parameter Test Setup JEDEC — Std tCCR Description CE#1ps Recover Time — Min 0 ns All Speeds Unit
CE#1ps
tCCR CE2ps
tCCR
Figure 12. Timing Diagram for Alternating Between Pseudo SRAM and Flash
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INFORMATION
AC CHARACTERISTICS Read-Only Operations – Am29PDL127H
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Note 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE#f1 or OE#, Whichever Occurs First (Notes 3) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#f1, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min All Speeds 70 70 70 70 30 30 16 16 5 0 10 Unit ns ns ns ns ns ns ns ns ns ns
Notes:
1. Not 100% tested. 2. See Figure 10 and Table 19 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF.
Read-Only Operations – Am29PDL129H
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay (Note 3) Chip Enable to Output Delay (Note 4) Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 5, 6) Output Enable to Output High Z (Notes 1, 5) Output Hold Time From Addresses, CE#f1/CE#f2 or OE#, Whichever Occurs First (Notes 5, 6) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#f1, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min All Speeds 70 70 70 70 30 30 16 16 5 0 10 Unit ns ns ns ns ns ns ns ns ns ns
Notes:
1. Not 100% tested. 2. See Figure 10 and Table 19 for test specifications
3. Valid CE#f1/CE#f2 conditions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL). 4. Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= VIH) to (CE#f1= VIL, CE#f2=VIH) or (CE#f1= VIH, CE#f2=VIL).
5. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. 6. Valid CE#f1/CE#f2 transitions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL) to (CE#f1= CE#f2= VIH).
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INFORMATION
AC CHARACTERISTICS
tRC Addresses CE#f1 or CE#f2 (PDL 129 only) OE# Addresses Stable tACC tRH tRH tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF
0V
Figure 13.
Read Operation Timings
Addresses
Same Page
A2-A0
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data CE# f1 or CE#f2 (PDL129 only) OE#
Figure 14.
Qa
Qb
Qc
Qd
Page Read Operation Timings
Notes: During CE#f1 transitions, CE#f2= VIH; During CE#f2 transitions, CE#f1= VIH
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INFORMATION
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit µs ns ns ns µs ns
Note: Not 100% tested.
RY/BY#
CE#f1, CE#f2 (PDL129 only), OE# RESET# tRP tReady
tRH
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY#1 tRB CE#f1, CE#f2 (PDL129 only), OE#
RESET# tRP
Figure 15.
Reset Timings
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INFORMATION
AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tWHDL tGHWL tWS tCS tWH tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE#1f or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time (CE#f1 to WE#) CE#f1 Setup Time WE# Hold Time (CE#f1 to WE#) CE#f1 Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max All Speeds 65 0 15 35 0 30 0 10 0 0 0 0 0 40 25 0 6 4 0.5 50 0 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs sec µs ns ns
Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information.
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INFORMATION
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE#f1 or CE#f2 (PDL129 only) OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tGHWL
tCH
A0h
VCCf tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode. 3. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 16.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 17.
Accelerated Program Timing Diagram
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INFORMATION
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SADD
555h for chip erase
Read Status Data
VA tAH
VA
CE#f1 (PDL129 only) OE#
tGHWL tCH tWP
WE# tCS tDS tDH Data 55h
tWPH
tWHWH2
30h
10 for Chip Erase
In Progress
Complete
tBUSY RY/BY# tVCS VCCf
tRB
Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. 2. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 18.
Chip/Sector Erase Operation Timings
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INFORMATION
AC CHARACTERISTICS
tWC Addresses
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC
CE#f1 or CE#f2 (PDL129 only)
tCPH
tCE tOE tCP
OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE#f Controlled Write Cycles
Figure 19.
Back-to-back Read/Write Cycle Timings
tRC Addresses VA tACC tCE CE#f1 or CE#f2 (PDL129 only) OE# tOEH WE# tOH DQ7
High Z
VA
VA
tCH
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6–DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.
Data# Polling Timings (During Embedded Algorithms)
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INFORMATION
AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE#f1 or CE#f2 (PDL129 only) tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 21.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f1 to toggle DQ2 and DQ6.
Figure 22.
DQ2 vs. DQ6
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INFORMATION
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns µs µs
Note: Not 100% tested.
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE#f1 or CE#f2 (PDL129 only) tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 23.
Temporary Sector Unprotect Timing Diagram
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INFORMATION
AC CHARACTERISTICS
VID VIH
RESET#
SADD, A6, A1, A0
Valid* Sector/Sector Block Protect or Unprotect
Valid* Verify 40h
Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 µs CE#f1 or CE#f1(PDL129 only) WE#
OE#
1. 2. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH.
Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram
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INFORMATION
AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE#f Pulse Width CE#f Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ All Speeds 70 0 35 30 0 0 0 0 40 25 6 4 0.4 Unit ns ns ns ns ns ns ns ns ns ns µs µs sec
Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information.
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INFORMATION
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE#f1 or CE#f2 (PDL129 only) tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SADD = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 25.
Flash Alternate CE# Controlled Write (Erase/Program) Operation Timings
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INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Typ (Note 1) 0.4 108 6 4 50 210 120 200 Max (Note 2) 5 Unit sec sec µs µs sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 11 12 14 17 Max 14 16 16 20 Unit pF pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years
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INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1.
Operation Read Write Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect CE# L L VCC ± 0.3 V L X L L X OE# L H X H X H H X
register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Am29DL640H Device Bus Operations
WE# H L X H X L L X RESET# H H VCC ± 0.3 V H L VID VID VID WP#/ACC L/H (Note 3) L/H L/H L/H L/H (Note 3) (Note 3) Addresses (Note 2) AIN AIN X X X SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L AIN DQ15–DQ8 DOUT DIN High-Z High-Z High-Z X X DIN DQ7– DQ0 DOUT DIN High-Z High-Z High-Z DIN DIN DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in word mode. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 3. If WP#/ACC = VIL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH . The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
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INFORMATION
R efer to the AC AC Characteristics table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 85 for related information.
Autoselect Functions
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Requirements for Reading Array Data” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon-
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 i n the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when ad-
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INFORMATION The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY ( not during Embedded Algorithms). The system can read data tRH a fter the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.
d resses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2.
Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
Am29DL640H Sector Architecture
Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x16) Address Range 00000h–00FFFh 01000h–01FFFh 02000h–02FFFh 03000h–03FFFh 04000h–04FFFh 05000h–05FFFh 06000h–06FFFh 07000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h–47FFFh 48000h–4FFFFh 50000h–57FFFh 58000h–5FFFFh 60000h–67FFFh 68000h–6FFFFh 70000h–77FFFh 78000h–7FFFFh
Sector Address A21–A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001101xxx 0001111xxx
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
81
ADVANCE Table 2.
Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Bank 2 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
INFORMATION
Am29DL640H Sector Architecture (Continued)
Sector Address A21–A12 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011000xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0100100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x16) Address Range 80000h–87FFFh 88000h–8FFFFh 90000h–97FFFh 98000h–9FFFFh A0000h–A7FFFh A8000h–AFFFFh B0000h–B7FFFh B8000h–BFFFFh C0000h–C7FFFh C8000h–CFFFFh D0000h–D7FFFh D8000h–DFFFFh E0000h–E7FFFh E8000h–EFFFFh F0000h–F7FFFh F8000h–FFFFFh F9000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh
82
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 2.
Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 Bank 3 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
INFORMATION
Am29DL640H Sector Architecture (Continued)
Sector Address A21–A12 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x16) Address Range 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–28FFFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2FFFFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
83
ADVANCE Table 2.
Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank 4 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
INFORMATION
Am29DL640H Sector Architecture (Continued)
Sector Address A21–A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x16) Address Range 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh
Table 3.
Bank 1 2 3 4
Bank Address
A21–A19 000 001, 010, 011 100, 101, 110 111
Table 4.
Device Am29DL640H
SecSiTM Sector Addresses
Sector Size 256 bytes (x16) Address Range 00000h–0007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its c orresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID o n address pin A9. Address pins must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 5 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then 84
read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the Am29DL640 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 11. Note that if a Bank Address (BA) on address bits A21, A20, and A19 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 11. This method does not require V ID. Refer to the Autoselect Command Sequence section for more information.
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
Sector/ Sector Block Size 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 10). The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8–SA10 SA11–SA14 SA15–SA18 SA19–SA22 SA23–SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55–SA58 SA59–SA62 SA63–SA66 SA67–SA70 SA71–SA74 SA75–SA78 SA79–SA82 SA83–SA86 SA87–SA90 SA91–SA94 SA95–SA98 A21–A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX, 0000010XXX, 0000011XXX, 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX Sector/ Sector Block Size 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes
Sector SA99–SA102 SA103–SA106 SA107–SA110 SA111–SA114 SA115–SA118 SA119–SA122 SA123–SA126 SA127–SA130 SA131–SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21–A12 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX, 1111101XXX, 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111101 1111111111
Sector protection/sector unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 24 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector Unprotect”. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
85
ADVANCE
INFORMATION
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Table 6.
WP# Input Voltage
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 10). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. If the WP#/ACC pin is at VIL , sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode.
WP#/ACC Modes
Device Mode
VIL VIH VHH
Disables programming and erasing in SA0, SA1, SA140, and SA141 Enables programming and erasing in SA0, SA1, SA140, and SA141 Enables accelerated programming (ACC). See “Accelerated Program Operation” on page 20.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again.
Figure 1.
Temporary Sector Unprotect Operation
86
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
START PLSCNT = 1 RESET# = VID Wait 4 µs Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 µs
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address
No
Temporary Sector Unprotect Mode
Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Reset PLSCNT = 1 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
Increment PLSCNT
No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A7-A0 = 00000010 Set up next sector address
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes Remove VID from RESET#
Data = 00h? Yes
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Yes Remove VID from RESET#
No
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure 2.
In-System Sector Protect/Unprotect Algorithms
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
87
ADVANCE
INFORMATION programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter Secsi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, example that RESET# may be at either VIH or VID. This allows in-system protection of the Secsi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secsi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 1. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.
SecSi™ (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either fac t or y l ocke d or c u s t om e r l o ckabl e. T he fac tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number is at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN is
88
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE
INFORMATION
Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
START RESET# = VIH or VID Wait 1 µs Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected.
Remove VIH or VID from RESET#
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12–15. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12–15. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.
Write reset command SecSi Sector Protect Verify complete
Figure 3.
SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC i s greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
89
ADVANCE Table 7.
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
INFORMATION
CFI Query Identification String
Description Query Unique ASCII string “QRY”
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 8.
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
System Interface String
Description VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
90
Am75PDL191CHHa/Am75PDL193CHHa
January 14, 2004
ADVANCE Table 9.
Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
INFORMATION
Device Geometry Definition
Description Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
N
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
January 14, 2004
Am75PDL191CHHa/Am75PDL193CHHa
91
ADVANCE Table 10.
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah
INFORMATION
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string “PRI” Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported, but not tested Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4
Data 0050h 0052h 0049h 0031h 0033h 0004h
46h 47h 48h
8Ch 8Eh 90h
0002h 0001h 0001h
49h
92h
0004h
4Ah 4Bh 4Ch 4Dh 4Eh
94h 96h 98h 9Ah 9Ch
0077h 0000h 0000h 0085h 0095h
4Fh
9Eh
0004h
50h 57h 58h 59h 5Ah 5Bh
A0h AEh B0h B2h B4h B6h
0001h 0004h 0017h 0030h 0030h 0017h
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INFORMATION
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 11 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device to an unknown state. A reset command is required to return the device to read array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the pSRAM AC Characteristics section for timing diagrams. before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur ns th a t ba nk to the e ra s e- s us pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding ban k enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The AC Characteristics table provides the read parameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence January 14, 2004
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is-
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INFORMATION ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 11 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. See Table 12. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH a ny operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.
s ues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. SecSi sector, autoselect, and CFI are not allowed. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A b it cannot be programmed from “0” back to a “1.” A ttempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success-
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INFORMATION Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. N o SecSi sector, autoselect, or CFI is available. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de-
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 11 for program command sequence.
Figure 4.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 11 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.
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INFORMATION for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 11 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 5.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected
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Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Autoselect (Note 7) Manufacturer ID Device ID (Note 9) SecSi Sector Factory Protect (Note 10) Sector/Sector Block Protect Verify (Note 11) Word Byte Word Byte Word Byte Word Byte Cycles First Addr Data RA RD XXX F0 555 AA AAA 555 AA AAA 555 AA AAA 555 AA AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA BA BA 55 AA AA AA AA AA A0 90 AA AA B0 30 98
INFORMATION
Am29DL640H Command Definitions
Second Addr Data Bus Cycles (Notes 2–5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
1 1 4 6 4 4 3 4 4 3 2 2 6 6 1 1 1
2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555
55 55 55 55 55 55 55 55 PD 00 55 55
(BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA 555 AAA 555 AAA 555 AAA 555 AAA
90 90 90 90 88 90 A0 20
(BA)X00
01 02 (BA)X0F (BA)X1E 01
(BA)X01 (BA)X0E 7E (BA)X02 (BA)X1C (BA)X03 80/00 (BA)X06 (SA)X02 00/01 (SA)X04
Word Byte Word Exit SecSi Sector Region Byte Word Program Byte Word Unlock Bypass Byte Unlock Bypass Program (Note 15) Unlock Bypass Reset (Note 15) Word Chip Erase Byte Word Sector Erase Byte Erase Suspend (Note 11) Erase Resume (Note 12) Word CFI Query (Note 13) Byte Enter SecSi Sector Region
XXX PA
00 PD
555 AAA 555 AAA
80 80
555 AAA 555 AAA
AA AA
2AA 555 2AA 555
55 55
555 AAA SA
10 30
Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. Refer to Table 2 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A21–A19 uniquely select a bank.
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA is required. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the same until a reset command is given. See the Autoselect Command Sequence section for more information.
9. The device ID must be read across the fourth, fifth, and sixth cycles. 10. The data is 80h for factory locked, 40h for customer locked, and 00h for not factory/customer locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode.
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INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. vice has completed the program or erase operation a n d D Q 7 h a s va l i d d a ta , th e d a t a o u t p u ts o n D Q1 5–D Q0 may be s ti ll i nva lid . Val id d ata o n DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read cycles. Table 18 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. Figure 20 in the pSRAM AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode.
No START
Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-only device) while Output Enable (OE#) is asserted low. That is, the device may change from providing status infor mation to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the de-
DQ5 = 1?
Yes Read DQ7–DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
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INFORMATION DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 18 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 18 shows the outputs for RY/BY#.
START
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.
Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7–DQ0) Address = VA
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7.
Toggle Bit Algorithm
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INFORMATION not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” O nly an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
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ADVANCE Table 12.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
INFORMATION Write Operation Status
Standard Mode Erase Suspend Mode
DQ7 (Note 2) DQ7# 0 1 Data DQ7#
DQ6 Toggle Toggle No toggle Data Toggle
DQ5 (Note 1) 0 0 0 Data 0
DQ3 N/A 1 N/A Data N/A
DQ2 (Note 2) No toggle Toggle Toggle Data N/A
RY/BY# 0 0 1 1 0
Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS t o –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS t o –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
+0.8 V –0.5 V –2.0 V 20 ns 20 ns 20 ns
Figure 8. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 9. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . –55°C to +125°C VCC Supply Voltages VCC for standard voltage range . . . . . . . 2.7 V to 3.1 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
S pansion Flash MultiChip memory products are not tested or guaranteed for any level of ESD immunity on components not designed and manufactured by FASL LLC. Please refer to individual MCP product qualification reports for information on how to obtain ESD immunity infor mation from manufacturers of such components.
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INFORMATION
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO ILR Parameter Description Input Load Current A9 Input Load Current Output Leakage Current Reset Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max VCC = VCC max; RESET= 12.5 V CE# = VIL, OE# = VIH, Byte Mode CE# = VIL, OE# = VIH, Word Mode 5 MHz 1 MHz 5 MHz 1 MHz 10 2 10 2 15 0.2 0.2 0.2 Word Word 21 21 Min Typ Max ±1.0 35 ±1.0 35 16 4 mA 16 4 30 5 5 5 45 45 mA µA µA µA mA mA Unit µA µA µA µA
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2 ICC3 ICC4 ICC5 ICC6 ICC7
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% CE#, RESET# = VCC ± 0.3 V RESET# = VSS ± 0.3 V VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH
ICC8 VIL VIH VHH
CE# = VIL, OE# = VIH –0.5 0.7 x VCC 8.5
17
35 0.8 VCC + 0.3 9.5
mA V V V
VID VOL VOH1 VOH2 VLKO
Voltage for Autoselect and Temporary VCC = 3.0 V ± 10% Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 5) IOL = 2.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min
11.5
12.5 0.45
V V V
0.85 VCC VCC–0.4 2.0 2.5
V
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested.
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ADVANCE
INFORMATION
DC CHARACTERISTICS Zero-Power Flash
25 Supply Current in mA
20
15
10
5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000
Note: Addresses are switching at 1 MHz
Figure 10.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12 3.6 V 10 2.7 V 8 Supply Current in mA
6
4
2
0 1
Note: T = 25 °C
2
3 Frequency in MHz Figure 11. Typical ICC1 vs. Frequency
4
5
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ADVANCE
INFORMATION
PSRAM DC CHARACTERISTICS Recommended DC Operating Conditions (Note 1)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.3 (Note 3) Typ 2.9 0 Max 3.1 0 VCC + 0.3 (Note 2) 0.6 Unit V V V V
Notes:
1. TA = -40 to 85°C, otherwise specified. 2. Overshoot: VCC + 1.0 V in case of pulse width ≤ 20 ns.
3. Undershoot: -1.0 V in case of pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (f= 1MHz, TA = 25°C)
Item Input Capacitance Input/Output Capacitance Symbol CIN CIO Test Condition VIN= 0 V VIO= 0 V Min Max 8 10 Unit pF pF
Note: Capacitance is sampled, not 100% tested.
DC and Operating Characteristics
Item Input Leakage Current Output Leakage Current Symbol Test Conditions ILI VIN= VSS to VCC ILO CS#1s= VIH, CS2s= VIH or WE#= VIL, VIO= VSS to VCC Cycle time = 1ms, 100% duty, IIO= 0 mA, CS#1s ≤ 0.2 V, CS2s ≥ VCC ≤ 0.2 V or ICC1 VIN ≥ VCC-0.2 V Cycle Time = Min, IIO = 0 mA, 100% duty, IIO = 0 mA, ICC2 CS#1s = VIL, CS2s = VIH, VIN=VIL or VIH VOL IOL= 2.1 mA VOH IOH= -1.0 mA CS#1s ≥ VCC-0.2 V, CS2s ≥ VCC-0.2 V, ISB1 Other inputs= VSS to VCC ISBD CS2s ≤ 0.2V, Other inputs= VSS to VCC Min -1 -1 2.4 Typ 30 Max 1 1 7 35 0.4 80 20 Unit µs µs mA mA V V µs µs
Average Operating Current
Output Low Voltage Output High Voltage Standby Current (CMOS) Deep Power Down
Note: Typical values are tested at VCC= 2.9 V, TA= 25°C and not guaranteed.
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INFORMATION
TEST CONDITIONS
Table 13.
3.1 V 2.7 kΩ Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 kΩ Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
All Speed Options 1 TTL gate 70 5 0.0–3.0 1.5 1.5 pF ns V V V Unit
Device Under Test
Note: Diodes are IN3064 or equivalent
Figure 12.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
Figure 13.
Input Waveforms and Measurement Levels
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ADVANCE
INFORMATION
PSRAM AC CHARACTERISTICS CE#s Timing
Parameter Test Setup JEDEC — Std tCCR Description CE#s Recover Time — Min 0 ns All Speeds Unit
CE#1ps
tCCR CE2ps
tCCR
Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash
VCC (Min) Min. 0 ns CS2s Min. 200 µs CS#1s Power Up Mode Normal Operation
VCC
Note: After VCC reaches VCC (MIn), wait 200 µs with CS#1s and CS2s high. The device will enter into normal operation.
Figure 15.
Timing Waveform of Power-up
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INFORMATION
AC CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tRC tACC tCE tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min All Speed Options 70 70 70 30 16 16 0 0 10 Unit ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See Figure 10 and Table 19 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF
.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 16.
Read Operation Timings
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ADVANCE
INFORMATION
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit µs ns ns ns µs ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 17.
Reset Timings
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INFORMATION
AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max All Speed Options 70 0 15 40 0 40 0 20 0 0 0 30 30 0 7 4 0.4 50 0 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs sec µs ns ns
Notes: 1. Not 100% tested. 2. See the “Physical Dimensions” section for more information.
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INFORMATION
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 18.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 19.
Accelerated Program Timing Diagram
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INFORMATION
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. 2. These waveforms are for the word mode.
Figure 20.
Chip/Sector Erase Operation Timings
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INFORMATION
AC CHARACTERISTICS
tWC Addresses
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC CE# tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tCPH
tCP
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE# or CE2# Controlled Write Cycles
Figure 21.
Back-to-back Read/Write Cycle Timings
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0–DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 22.
Data# Polling Timings (During Embedded Algorithms)
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INFORMATION
AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 23.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 24.
DQ2 vs. DQ6
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ADVANCE
INFORMATION
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns µs µs
Note: Not 100% tested.
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 25.
Temporary Sector Unprotect Timing Diagram
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INFORMATION
AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect/Unprotect
Valid* Verify 40h
Valid*
Data 1 µs CE#
60h
60h
Status
Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram
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ADVANCE
INFORMATION
AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ All Speed Options 70 0 40 40 0 0 0 0 40 30 7 4 0.4 Unit ns ns ns ns ns ns ns ns ns ns µs µs sec
Notes: 1. Not 100% tested. 2. See the “Erase and Programming” section for more information.
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INFORMATION
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 27.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
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ADVANCE
INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Chip Program Time (Note 3) Word Mode Typ (Note 1) 0.4 56 5 4 7 28 150 120 210 84 Max (Note 2) 5 Unit sec sec µs µs µs sec Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)
Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years
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INFORMATION
PSRAM AC CHARACTERISTICS Functional Description
CS#1s H X L L L L L L L L CS2s H L H H H H H H H H OE# X X X H H L L L X X WE# X X X H H H H H L L LB# X X H L X L H L L L UB# X X H X L H L L H L I/O1-8 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN DIN I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Word Write Power Standby Deep Power Down Standby Active Active Active Active Active Active Active
Note: “X” means don’t care. (Must be low or high state).
Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC + 0.3V -0.2 to 3.6 V 1.0 -65 to 150 -40 to 85 Unit V V W °C °C
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
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INFORMATION
PSRAM AC CHARACTERISTICS
CS#1s=V IH and CS2s =V IH Power On Initial State (Wait 200µ s)
CS #1=V IL, UB or/and LB=VIL CS2s =VIH Active CS#1s =V IH CS2s =VIH
Standby Mode
CS2s =V IL
CS2s =V IL CS#1s =V IH, CS2s =V IH
Deep Power Down Mode
Figure 28.
Standby Mode State Machines
Standby Mode Characteristic
Power Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current (µA) 80 20 Wait Time (µs) 0 200
AC Characteristics (VCC= 2.7-3.1 V, TA= -40 to 85°C)
Parameter List Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Speed Bins 70 ns Min Max 70 70 70 35 70 10 10 5 0 25 0 25 0 25 5 70 60 0 60 60 55 (Note 1) 0 0 25 30 0 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Read
Write
tWP (min)= 70 ns for continuous write operation over 50 times.
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TIMING DIAGRAMS
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
Figure 29.
Timing Waveform of Read Cycle 1
tRC Address tAA CS#1s tCO t HZ tBA UB#, LB# t BHZ OE# t LZ tOLZ t BLZ Data Valid tOE t OHZ tOH
Data out
High-Z
Figure 30.
Timing Waveform of Read Cycle 2
3. tOE (Max) is met only when OE# becomes enabled after tAA (Max). 4. If invalid address signals shorter than min. tRC are continuously repeated for over 4 us, the device needs a normal read timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4 us.
Notes: 1. tHZ and tOZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Min) both for a given device and from device interconnection.
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TIMING DIAGRAMS
tWC Address tCW(2) CS#1s tAW tBW UB#, LB# tWP(1) WE# tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z tWR(4)
Figure 31.
Timing Waveform of Write Cycle 1
tWC
Address tCW(2) CS#1s tAW tBW UB#, LB# tAS(3) tWP(1) WE# tDW Data in Data Valid tDH tWR(4)
Data out
High-Z
High-Z
Figure 32.
Timing Waveform of Write Cycle 2
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TIMING DIAGRAMS
tWC Address tCW(2) CS#1s tAW UB#, LB# tAS(3) tWP(1) WE# tDW Data in Data Valid tDH tBW tWR(4)
Data out
High-Z
High-Z
Notes: Write Cycle 1. A write occurs during the overlap (tWP) of low CS#1s and low WE#. A write begins when CS#1s goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS#1s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS#1s going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS#1s or WE# going high.
200µs
≈
CS2s Normal Operation MODE
0.5µs Suspend
Wake up
Normal Operation
Deep Power Down Mode
≈
CS#1s
Notes: Deep Power Down Mode 1. When you toggle CS2s pin low, the device gets into the Deep Power Down mode after 0.5 ms suspend period. 2. To return to normal operation, the device needs Wake-up period. 3. Wake Up sequence is just the same as Power Up sequence.
Figure 33.
Timing Waveform of Write Cycle 3
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PHYSICAL DIMENSIONS FMB073—73-Ball Fine-Pitch Grid Array 9 x 13 mm
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE 7 E1
E eE
6 5 4 3 2 1
INDEX MARK PIN A1 CORNER 10
M
L
K
J
H
G
F
E
D
CB
A
B
TOP VIEW
7
0.15 C (2X)
PIN A1 CORNER
SD
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW
73X
b
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC FMB 073 N/A 13.00 mm X 9.00 mm PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD/SE 0.29 MIN. --0.20 1.02 NOM. ------13.00 BSC 9.00 BSC 8.80 BSC 7.20 BSC 12 10 73 --0.80 BSC 0.80 BSC 0.40 BSC A2,A3,A4,A5,A6,A7,A8,A9 B2,B3,B4,B5,B6,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10 F5,F6,G5,G6,H1,H10,J1,J10 K1,K2,K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 0.39 MAX. 1.40 --1.17 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7. 6. NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = E/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. NOT USED.
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
w053003f-163814c
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REVISION SUMMARY Revision A (November 6, 2003)
Initial release.
Revision A+1 (November 24, 2003)
DC Characteristics - CMOS Compatible Corrected DC test condition of VOL [IOL of Vol (Output Low Voltage)]. See DC Characteristics - CMOS Compatible table. SecSi™ (Secured Silicon) Sector Flash Memory Region
Customer-Lockable Area: Added sector protection figure and changed figure reference in this section from Figure 1 to Figure 3.
Figure 17, Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit Status, PPMLB Status, and SPMLB Status from 4 to 5 cycles. For these command sequences, inserted a cycle before the final read cycle (RD0).
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Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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