BS320GTD3V

Am29BDS320G Data Sheet October 1, 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 27243 Revision B Amendment 1 Issue Date October 1, 2003 THIS PAGE LEFT INTENTIONALLY BLANK. Am29BDS320G 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet PRELIMINARY Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.17 µm process technology Enhanced VersatileIO™ (VIO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.8V and 3V compatible I/O signals Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 8Mb/8Mb/8Mb/8Mb Programmable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst Sector Architecture — Eight 8 Kword sectors and sixty-two 32 Kword sectors — Banks A and D each contain four 8 Kword sectors and fifteen 32 Kword sectors; Banks B and C each contain sixteen 32 Kword sectors — Eight 8 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range Minimum 1 million erase cycle guarantee per sector 20-year data retention at 125°C — Reliable operation for the life of the system 64-ball FBGA package Hardware Features Sector Protection — Software command sector locking Reduced Wait-State Handshaking feature available — Provides host system with minimum possible latency by monitoring RDY Hardware reset input (RESET#) — Hardware method to reset the device for reading array data WP# input — Write protect (WP#) function protects sectors 0 and 1 (bottom boot), or sectors 68 and 69 (top boot), regardless of sector protect status ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL CMOS compatible inputs, CMOS compatible outputs Low VCC write inhibit Software Features Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences Performance Charcteristics Read access times at 54/40 MHz (at 30 pF) — Burst access times of 13.5/20 ns — Asynchronous random access times of 70 ns — Initial Synchronous access times as fast as 87.5/95 ns Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA Publication Number 27243 Revision B Amendment 1 Issue Date October 1, 2003 Preliminary General Description The Am29BDS320G is a 32 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. The device supports Enhanced VIO to offer up to 3V compatible inputs and outputs. A 12.0-volt VID may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30 pF with a latency of 95 ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in the 64-ball FBGA package. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Bank A B C D Quantity 4 15 16 16 15 4 Size 8 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 8 Kwords The Enhanced VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. This allows the device to operate in 1.8 V and 3 V system environments as required. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. 2 Am29BDS320G 27243B1 October 1, 2003 Preliminary Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. The sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector. When at VIL, WP# locks sectors 0 and 1 (bottom boot device) or sectors 68 and 69 (top boot device). The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Spansion flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunnelling. The data is programmed using hot electron injection. October 1, 2003 27243B1 Am29BDS320G 3 Preliminary Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9 Special Handling Instructions for FBGA Package .......................... 9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 12 Table 1. Device Bus Operations ..........................................12 Configuration Register ........................................................................ 29 Table 12. Burst Mode Configuration Register ........................ 29 Sector Lock/Unlock Command Sequence .................................... 29 Reset Command ................................................................................... 30 Autoselect Command Sequence ..................................................... 30 Table 13. Device IDs ......................................................... 31 Program Command Sequence ............................................................31 Unlock Bypass Command Sequence ................................................31 Figure 2. Erase Operation.................................................. 32 Enhanced VersatileIO™ (VIO) Control ............................................ 12 Requirements for Asynchronous Read Operation (Non-Burst) ........................................................................ 12 Requirements for Synchronous (Burst) Read Operation ......... 13 8-, 16-, and 32-Word Linear Burst with Wrap Around ............. 14 Table 2. Burst Address Groups ............................................14 Chip Erase Command Sequence ......................................................32 Sector Erase Command Sequence ...................................................33 Erase Suspend/Erase Resume Commands .....................................34 Figure 3. Program Operation.............................................. 35 Command Definitions .......................................................................... 36 Table 14. Command Definitions ......................................... 36 Write Operation Status . . . . . . . . . . . . . . . . . . . . 37 DQ7: Data# Polling ..............................................................................37 Figure 4. Data# Polling Algorithm....................................... 38 Burst Mode Configuration Register ................................................. 14 Reduced Wait-State Handshaking Option ..................................... 14 Simultaneous Read/Write Operations with Zero Latency ....... 15 Writing Commands/Command Sequences ................................... 15 Accelerated Program Operation ...................................................... 15 Autoselect Functions ............................................................................ 16 Standby Mode ......................................................................................... 16 Automatic Sleep Mode ......................................................................... 16 RESET#: Hardware Reset Input ........................................................ 16 Output Disable Mode ........................................................................... 17 Hardware Data Protection ................................................................. 17 Write Protect (WP#) ........................................................................... 17 Low VCC Write Inhibit ........................................................................ 17 Write Pulse “Glitch” Protection .......................................................18 Logical Inhibit ..........................................................................................18 Power-Up Write Inhibit ......................................................................18 VCC and VIO Power-up And Power-down Sequencing .............18 Common Flash Memory Interface (CFI) . . . . . . . 18 Table 3. CFI Query Identification String ...............................19 System Interface String..................................................... 19 RDY: Ready .............................................................................................38 DQ6: Toggle Bit I ..................................................................................39 Figure 5. Toggle Bit Algorithm............................................ 40 DQ2: Toggle Bit II ................................................................................ 40 Table 15. DQ6 and DQ2 Indications .................................... 41 Reading Toggle Bits DQ6/DQ2 ........................................................ 41 DQ5: Exceeded Timing Limits ........................................................... 41 DQ3: Sector Erase Timer .................................................................. 42 Table 16. Write Operation Status ........................................ 42 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 43 Figure 6. Maximum Negative Overshoot Waveform ............... 43 Figure 7. Maximum Positive Overshoot Waveform................. 43 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 CMOS Compatible .............................................................................. 44 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8. Test Setup ......................................................... 45 Table 17. Test Specifications .............................................. 45 Key to Switching Waveforms . . . . . . . . . . . . . . . . 45 Figure 9. Input Waveforms and Measurement Levels............. 45 Table 5. Device Geometry Definition......................................... 20 Table 6. Primary Vendor-Specific Extended Query................. 21 Table 7. Sector Address Table...................................................... 22 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25 Reading Array Data ............................................................................. 25 Set Burst Mode Configuration Register Command Sequence 25 Figure 1. Synchronous/Asynchronous State Diagram ............. 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47 Synchronous/Burst Read .....................................................................47 Figure 11. CLK Synchronous Burst Mode Read (rising active CLK)............................................................ Figure 12. CLK Synchronous Burst Mode Read (Falling Active Clock) ........................................................ Figure 13. Synchronous Burst Mode Read ............................ Figure 14. 8-word Linear Burst with Wrap Around................. Figure 15. Burst with RDY Set One Cycle Before Data............ Figure 16. Reduced Wait-State Handshaking Burst Mode Read Starting at an Even Address .............................................. Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address................................................ 48 49 50 50 51 52 53 Figure 10. VCC and VIO Power-up Diagram ........................... 46 Read Mode Setting ............................................................................... 26 Programmable Wait State Configuration ...................................... 26 Table 8. Programmable Wait State Settings ..........................27 Reduced Wait-State Handshaking Option .................................... 27 Table 9. Initial Access Cycles vs. Frequency ..........................27 Standard Handshaking Operation ...................................................28 Table 10. Wait States for Standard Handshaking ...................28 Burst Read Mode Configuration ......................................................28 Table 11. Burst Read Mode Settings ....................................28 Asynchronous Read ..............................................................................54 Figure 18. Asynchronous Mode Read with Latched Addresses . 54 Figure 19. Asynchronous Mode Read................................... 55 Figure 20. Reset Timings................................................... 56 Burst Active Clock Edge Configuration .........................................28 RDY Configuration .............................................................................. 29 4 Am29BDS320G 27243B1 October 1, 2003 Preliminary Erase/Program Operations ................................................................ 57 Figure 21. Asynchronous Program Operation Timings............. 58 Figure 22. Alternate Asynchronous Program Operation Timings 59 Figure 23. Synchronous Program Operation Timings .............. 60 Figure 24. Alternate Synchronous Program Operation Timings 61 Figure 25. Chip/Sector Erase Command Sequence................. 62 Figure 26. Accelerated Unlock Bypass Programming Timing .... 63 Figure 27. Data# Polling Timings (During Embedded Algorithm) 64 Figure 28. Toggle Bit Timings (During Embedded Algorithm)... 64 Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings . 65 Figure 30. Latency with Boundary Crossing .......................... 66 Figure 31. Latency with Boundary Crossing into Program/Erase Bank ................................................... 67 Figure 32. Example of Wait States Insertion (Standard Handshaking Device) ........................................................ 68 Figure 33. Back-to-Back Read/Write Cycle Timings ............... 69 Erase and Programming Performance . . . . . . . . 70 FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 70 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 71 VBD064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm Package ..................................................................................71 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 72 October 1, 2003 27243B1 Am29BDS320G 5 Preliminary Product Selector Guide Part Number Burst Frequency Speed Option VCC = 1.65 – 1.95 V, VIO = 2.7 – 3.15 V VCC, VIO = 1.65 – 1.95 V Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state Handshaking: Even Address Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state Handshaking: Odd Address; or Standard Handshaking Max Burst Access Time, ns (tBACC) Max Asynchronous Access Time, ns (tACC) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) 87.5 106 13.5 70 13.5 Am29BDS320G 54 MHz D3, D4 D8, D9 40 MHz C3, C4 C8, C9 95 120 20 90 20 Notes: 1. Speed Options ending in “3” and “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. 2. Speed Options ending in “4” and “9” indicate the “standard handshaking” option. 3. See the AC Characteristics section of this data sheet for full specifications. 6 Am29BDS320G 27243B1 October 1, 2003 Preliminary Block Diagram VCC VSS VIO RDY Buffer DQ15–DQ0 RDY Erase Voltage Generator Input/Output Buffers WE# RESET# WP# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder VCC Detector Y-Gating Address Latch Timer X-Decoder Cell Matrix AVD# CLK Burst State Control Burst Address Counter A20–A0 October 1, 2003 27243B1 Am29BDS320G 7 Preliminary Block Diagram of Simultaneous Operation Circuit VCC VSS VIO Y-Decoder Bank A Address Latches and Control Logic DQ15–DQ0 Bank A A20–A0 X-Decoder OE# Bank B Address Latches and Control Logic Y-Decoder DQ15–DQ0 Bank B WP# ACC RESET# WE# CE# AVD# RDY DQ15–DQ0 A20–A0 X-Decoder DQ15–DQ0 Status STATE CONTROL & COMMAND REGISTER A20–A0 Control X-Decoder Latches and Control Logic Y-Decoder Bank C Address Bank C DQ15–DQ0 A20–A0 A20–A0 X-Decoder Bank D Address Latches and Control Logic Y-Decoder Bank D DQ15–DQ0 8 Am29BDS320G 27243B1 October 1, 2003 Preliminary Connection Diagram 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A8 NC A7 A13 A6 A9 A5 WE# A4 RDY A3 A7 A2 A3 A1 NC B8 NC B7 A12 B6 A8 B5 RESET# B4 ACC B3 A17 B2 A4 B1 VCC C8 NC C7 A14 C6 A10 C5 NC C4 A18 C3 A6 C2 A2 C1 CLK D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 WP# E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 AVD# F8 NC F7 NC F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO G8 NC G7 DQ15 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 VSS H8 NC H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 NC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. October 1, 2003 27243B1 Am29BDS320G 9 Preliminary Input/Output Descriptions A20-A0 DQ15-DQ0 CE# OE# WE# VCC VIO VSS NC RDY = = = = = = = = = = Address inputs Data input/output Chip Enable input. Asynchronous relative to CLK for the Burst mode. Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Device Power Supply (1.65 – 1.95 V). Input & Output Buffer Power Supply (either 1.65 – 1.95 V or 2.7 – 3.15 V). Ground No Connect; not connected internally Ready output; indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Address Valid input. Indicates to device that the valid address is present on the address inputs (A20–A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the two outermost sectors. Should be at VIH for all other conditions. At VID, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions. CLK = AVD# = RESET# WP# = = ACC = Logic Symbol 21 A20–A0 CLK WP# ACC CE# OE# WE# RESET# AVD# RDY DQ15–DQ0 16 10 Am29BDS320G 27243B1 October 1, 2003 Preliminary Ordering Information The order number (Valid Combination) is formed by the following: Am29BDS320G T D 8 VM I TEMPERATURE RANGE I VM = Industrial (–40°C to +85°C) = 64-Ball Fine-Pitch Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (VBD064) = = = = 1.8 V VIO, reduced wait-state handshaking 1.8 V VIO, standard handshaking 3 V VIO, reduced wait-state handshaking 3 V VIO, standard handshaking PACKAGE TYPE VIO AND HANDSHAKING FEATURES 8 9 3 4 CLOCK RATE/ASYNCHRONOUS SPEED D C T B = 54 MHz/70 ns = 40 MHz/90 ns = Top boot sector = Bottom boot sector BOOT CODE SECTOR ARCHITECTURE DEVICE NUMBER/DESCRIPTION Am29BDS320G 32 Megabit (2 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase Valid Combinations Order Number Am29BDS320GTD8 Am29BDS320GBD8 Am29BDS320GTD9 Am29BDS320GBD9 Am29BDS320GTC8 Am29BDS320GBC8 Am29BDS320GTC9 Am29BDS320GBC9 Am29BDS320GTD3 Am29BDS320GBD3 Am29BDS320GTD4 Am29BDS320GBD4 Am29BDS320GTC3 Am29BDS320GBC3 Am29BDS320GTC4 Am29BDS320GBC4 Package Marking BS320GTD8V BS320GBD8V BS320GTD9V BS320GBD9V BS320GTC8V BS320GBC8V BS320GTC9V BS320GBC9V BS320GTD3V BS320GBD3V BS320GTD4V BS320GBD4V BS320GTC3V BS320GBC3V BS320GTC4V BS320GBC4V Burst Frequency (MHz) VIO Range 54 1.65–1.95V 40 VMI 54 2.7–3.15V 40 VMI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local sales office or representative to confirm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29BDS320G, the last digit of the speed grade specifies the VIO range of the device. Speed options ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt VIO range. Speed grades ending in “3” and “4” (e.g., D3, D4) indicate a 3.0 Volt VIO range. October 1, 2003 27243B1 Am29BDS320G 11 Preliminary Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations CLK (See RESET# Note) H H H H H L X X X X X X L L L Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle CE# L L L L H X OE# L L H H X X WE# H H L L X X A20–0 Addr In Addr In Addr In Addr In HIGH Z HIGH Z DQ15–0 I/O I/O I/O I/O HIGH Z HIGH Z AVD# L L H X L X L X X X H H H H H Addr In HIGH Z HIGH Z HIGH Z HIGH Z X Burst Data Out HIGH Z HIGH Z I/O H H H L H X H X X Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. Enhanced VersatileIO™ (VIO) Control The Enhanced VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data and address inputs to the same voltage level that is asserted on the VIO pin. The device is available with either 1.65–1.95 or 2.7–3.15 VIO. This allows the device to operate in 1.8 V or 3 V system environments as required. For example, a VIO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving and receiving signals to and from other 3 V devices on the same bus. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must first assert a valid address on A20–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. 12 Am29BDS320G 27243B1 October 1, 2003 Preliminary Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the burst mode configuration register command sequence. See “Set Burst Mode Configuration Register Command Sequence” and “Command Definitions” for further details. Once the system has written the “Set Burst Mode Configuration Register” command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). The RDY output indicates this condition to the system by pulsing low. For standard handshaking devices, there is no two cycle latency between 3Fh and 40h (or addresses offset from 3F and 40h by a multiple of 64). See Table 10. For reduced wait-state handshaking devices, if the address latched is 3Dh (or offset from 3Dh by a multiple of 64), an additional cycle latency occurs prior to the initial access. If the address latched is 3Eh (or offset from 3Eh by a multiple of 64) two additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3Fh and 40h (or offset from 3Fh by a multiple of 64) will not occur. For 3Fh latched addresses (or offset from 3Fh by a multiple of 64) three additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3Fh and 40h (or offset from these addresses by a multiple of 64) will not occur. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, “Device Bus Operations,” on page 12. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as described above in the subsequent bank. If the host system crosses the bank October 1, 2003 27243B1 Am29BDS320G 13 Preliminary boundary while the device is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will occur. RDY indicates the length of the latency by pulsing low. 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 2.) Table 2. Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Burst Address Groups Group Address Ranges 0-7h, 8-Fh, 10-17h, ... 0-Fh, 10-1Fh, 20-2Fh, ... 00-1Fh, 20-3Fh, 40-5Fh, ... As an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Burst Mode Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-State Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. 14 Am29BDS320G 27243B1 October 1, 2003 Preliminary For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Burst Mode Configuration Register Command Sequence” section on page 25 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 33, “Back-to-Back Read/Write Cycle Timings,” on page 69 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write operation, the system must drive CE#, WE#, and CLK to VIL and OE# to VIH when providing an address, command, and data. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 8, “Programmable Wait State Settings,” on page 27 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 8 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VID on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two- October 1, 2003 27243B1 Am29BDS320G 15 Preliminary cycle program command sequence as required by the Unlock Bypass mode. Removing VID from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VID. Note that the ACC pin must not be at VID for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 30 section for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK edge occurs after tACC or the CLK runs slower than 5MHz. Note that a new burst operation is required to provide new data. ICC4 in the “DC Characteristics” section on page 44 represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. 16 Am29BDS320G 27243B1 October 1, 2003 Preliminary Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of tREADY (during Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 20, “Reset Timings,” on page 56 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14, “Command Definitions,” on page 36 for command definitions). The device offers two types of data protection at the sector level: The sector lock/unlock command sequence disables or re-enables both program and erase operations in any sector. When WP# is at VIL, sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot) are locked. When ACC is at VIL, all sectors are locked. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Write Protect (WP#) The Write Protect (WP#) input provides a hardware method of protecting data without using VID. If the system asserts VIL on the WP# pin, the device disables program and erase functions in sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot). If the system asserts VIH on the WP# pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The sys- October 1, 2003 27243B1 Am29BDS320G 17 Preliminary tem must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. VCC and VIO Power-up And Power-down Sequencing The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach their operating voltages. Once VCC and VIO attain their respective operating voltages, de-assertion of RESET# to VIH is permitted. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 3-6. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 3-6. The system must write the reset command to return the device to the reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the web at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact a sales office or representative for copies of these documents. 18 Am29BDS320G 27243B1 October 1, 2003 Preliminary Table 3. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h CFI Query Identification String Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 4. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0004h 0000h 0009h 0000h 0004h 0000h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) October 1, 2003 27243B1 Am29BDS320G 19 Preliminary Table 5. Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0016h 0001h 0000h 0000h 0000h 0003h 0003h 0000h 0040h 0000h 003Dh 0000h 0000h 0001h 0003h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information 20 Am29BDS320G 27243B1 October 1, 2003 Preliminary Table 6. Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 0004h Primary Vendor-Specific Extended Query Description Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0001 = 0.17 µm Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation Number of Sectors in all banks except boot block Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization: X = Number of banks Bank A Region Information. X = Number of sectors in bank Bank B Region Information. X = Number of sectors in bank Bank C Region Information. X = Number of sectors in bank Bank D Region Information. X = Number of sectors in bank 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh 0002h 0001h 0000h 0005h 0033h 0001h 0000h 00B5h 00C5h 00xxh 0000h 0004h 0013h 0010h 0010h 0013h October 1, 2003 27243B1 Am29BDS320G 21 Preliminary Table 7. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 Bank D SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Sector Address Table Sector Size 8 Kwords 8 Kwords 8 Kwords 8 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 22 Am29BDS320G 27243B1 October 1, 2003 Preliminary Sector SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank C SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 Bank B SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords (x16) Address Range 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh October 1, 2003 27243B1 Am29BDS320G 23 Preliminary Sector SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 Bank A SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 8K words 8K words 8K words 8K words (x16) Address Range 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1FDFFFh 1FE000h-1FFFFFh 24 Am29BDS320G 27243B1 October 1, 2003 Preliminary Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 14, “Command Definitions,” on page 36 defines the valid register command sequences. Note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the “Erase Suspend/Erase Resume Commands” section on page 34 section for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the “Reset Command” section on page 30 section for more information. See also “Requirements for Asynchronous Read Operation (Non-Burst)” and “Requirements for Synchronous (Burst) Read Operation” sections for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figures 11, 13, and 18 show the timings. Set Burst Mode Configuration Register Command Sequence The device uses a burst mode configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. The burst mode configuration register must be set before the device will enter burst mode. The burst mode configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11–A0 should be 555h, and address bits A19–A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The burst mode configuration register can not be changed during device operations (program, erase, or sector lock). October 1, 2003 27243B1 Am29BDS320G 25 Preliminary Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (A19 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (A19 = 1) Synchronous Read Mode Only Figure 1. Synchronous/Asynchronous State Diagram Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: “1’ for asynchronous mode, “0” for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14– A12 determine the setting (see Table 8). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. 26 Am29BDS320G 27243B1 October 1, 2003 Preliminary Table 8. A14 0 0 0 0 1 1 Programmable Wait State Settings A12 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 A13 0 0 1 1 0 0 Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. 3. Assumes even address. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Reduced Wait-State Handshaking Option If the device is equipped with the reduced wait-state handshaking option, the host system should set address bits A14–A12 to 010 for a clock frequency of 40 MHz or to 011 for a clock frequency of 54 MHz for the system/device to execute at maximum speed. Table 9 describes the typical number of clock cycles (wait states) for various conditions. Table 9. Initial Access Cycles vs. Frequency Even Initial Addr. with Boundary 3 4 5 6 6 7 Odd Initial Addr. with Boundary 4 5 6 7 7 8 54 MHz 40 MHz System Frequency Range 6–11 MHz 12–23 MHz 24–33 MHz 34–40 MHz 40–47 MHz 48–54 MHz Even Initial Addr. 2 2 3 4 4 5 Odd Initial Addr. 2 3 4 5 5 6 Device Speed Rating Note: In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64). The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. October 1, 2003 27243B1 Am29BDS320G 27 Preliminary Standard Handshaking Operation For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Table 10 describes the typical number of clock cycles (wait states) for various conditions with A14–A12 set to 101. Table 10. Wait States for Standard Handshaking Typical No. of Clock Cycles after AVD# Low Conditions at Address Initial address is even Initial address is odd Initial address is even, and is at boundary crossing* Initial address is odd, and is at boundary crossing* 40/54 MHz 7 7 7 7 * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64). Burst Read Mode Configuration The device supports four different burst read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then proceeds until the next 8 word boundary. The address pointer then returns to the first word of the burst sequence, wrapping back to the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 11 shows the address bits and settings for the four burst read modes. Table 11. Burst Read Mode Settings Address Bits Burst Modes Continuous 8-word linear wrap around 16-word linear wrap around 32-word linear wrap around A16 0 0 1 1 A15 0 1 0 1 Note: Upon power-up or hardware reset the default setting is continuous. Burst Active Clock Edge Configuration By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock 28 Am29BDS320G 27243B1 October 1, 2003 Preliminary edge is active for all synchronous accesses. Address bit A17 determines this setting; “1” for rising active, “0” for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock cycle before valid data. Configuration Register Table 12 shows the address bits that determine the configuration register settings for various device functions. Table 12. Address Bit A19 A18 A17 A16 A15 A14 A13 A12 Programmable Wait State Burst Read Mode Function Set Device Read Mode RDY Clock Burst Mode Configuration Register Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) 00 01 10 11 = = = = Continuous (default) 8-word linear with wrap around 16-word linear with wrap around 32-word linear with wrap around 000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) Note: Device will be in the default state upon power-up or hardware reset. Sector Lock/Unlock Command Sequence The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/ unlock command sequence. In the first and second cycles, the address must point to the bank that contains the sector(s) to be locked or unlocked. The first and second cycle data is 60h. In the third cycle, the address must point to the target sector, and A6 is used to specify a lock (A6 = VIL) or unlock (A6 = VIH) operation. The third cycle data is 60h. After the third cycle, the system can continue to lock or unlock additional sectors in the same bank or exit the sector lock/unlock sequence by writing the reset command (F0h). It is not possible to read from the bank selected for sector lock/unlock operations. To enable such read operations, write the reset command. Note that the last two outermost boot sectors can be locked by taking the WP# signal to VIL. October 1, 2003 27243B1 Am29BDS320G 29 Preliminary Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). The reset command is used to exit the sector lock/unlock sequence. This command is required before reading from the bank selected for sector lock/unlock operations. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14, “Command Definitions,” on page 36 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and SA represents the sector address. The device ID is read in three cycles. 30 Am29BDS320G 27243B1 October 1, 2003 Preliminary Table 13. Description Manufacturer ID Device ID, Word 1 Device IDs Read Data 0001h 227Eh 2222h (1.8 V VIO, top boot), 2223h (1.8 V VIO, bottom boot), 2214h (3.0 V VIO, top boot), 2234h (3.0 V VIO, bottom boot) 2200h 0001 (locked), 0000 (unlocked) 43h (reduced wait-state), 42h (standard) Address (BA) + 00h (BA) + 01h Device ID, Word 2 (BA) + 0Eh Device ID, Word 3 Sector Block Lock/Unlock Handshaking (BA) + 0Fh (SA) + 02h (BA) + 03h The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend). Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 37 section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to primarily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in October 1, 2003 27243B1 Am29BDS320G 31 Preliminary the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 14, “Command Definitions,” on page 36 shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VID on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 2 illustrates the algorithm for the program operation. Refer to the Erase/ Program Operations table in the AC Characteristics section for parameters, and Figure 21, “Asynchronous Program Operation Timings,” on page 58 for timing diagrams. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Figure 2. Erase Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require 32 Am29BDS320G 27243B1 October 1, 2003 Preliminary the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 14, “Command Definitions,” on page 36 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles in length instead of six cycles. See Table 14 for details on the unlock bypass command sequences. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 14 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 35 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 42.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading October 1, 2003 27243B1 Am29BDS320G 33 Preliminary DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” section on page 37 section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the “Write Operation Status” section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Autoselect Functions” section on page 16 and “Autoselect Command Sequence” section on page 30 sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 34 Am29BDS320G 27243B1 October 1, 2003 Preliminary START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 14 for program command sequence. Figure 3. Program Operation October 1, 2003 27243B1 Am29BDS320G 35 Preliminary Command Definitions Table 14. Command Sequence (Notes) Asynchronous Read (6) Reset (7) Autoselect (8) Manufacturer ID Device ID (9) Sector Lock Verify (10) Handshaking Option (11) Cycles First RA XXX 555 555 555 555 555 555 XXX XXX XXX BA 555 555 BA BA BA 555 55 RD F0 AA AA AA AA AA AA A0 80 80 90 AA AA B0 30 60 AA 98 BA 2AA 60 55 SLA (CR)555 60 C0 2AA 2AA 2AA 2AA 2AA 2AA PA SA XXX XXX 2AA 2AA 55 55 55 55 55 55 PD 30 10 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)555 (BA)555 (SA)555 (BA)555 555 555 90 90 90 90 A0 20 (BA)X00 (BA)X01 (SA)X02 (BA)X03 PA 0001 227E 0000/0001 0042/0043 PD (BA)X 0E (Note 9) (BA) X0F 2200 Command Definitions Bus Cycles (Notes 1–5) Third Addr Data Addr Fourth Data Fifth Addr Data Sixth Addr Data Second Addr Data Addr Data 1 1 4 6 4 4 4 3 2 2 2 2 6 6 1 1 3 3 1 Program Unlock Bypass Unlock Bypass Program (12) Unlock Bypass Sector Erase (12) Unlock Bypass Chip Erase (12) Unlock Bypass Reset (13) Chip Erase Sector Erase Erase Suspend (7, 14) Erase Resume (15) Sector Lock/Unlock (7) Set Burst Mode Configuration Register (16) CFI Query (17) Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# pulse. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A13 uniquely select any sector. BA = Address of the bank (A20, A19) that is being switched to Autoselect mode, is in bypass mode, is being erased, or is being selected for sector lock/unlock. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. Notes: 1. 2. 3. 4. 5. 6. 7. See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A20–A12 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. The data in the fifth cycle is 2222 for 1.8 V VIO, and 2214 for 3.0 V VIO (top boot); 2223 for 1.8 V VIO, and 2234 for 3.0 V VIO (bottom boot). 10. The data is 0000h for an unlocked sector and 0001h for a locked sector 11. The data is 0043h for reduced wait-state handshaking and 0042h for standard handshaking. 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. 8. 9. 36 Am29BDS320G 27243B1 October 1, 2003 Preliminary Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16, “Write Operation Status,” on page 42 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive read cycles. Table 16 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Po l l i n g algorithm. Figure 27, “Data# Po l l i n g Timings (During Embedded Algorithm),” on page 64 in the AC Characteristics section shows the Data# Polling timing diagram. October 1, 2003 27243B1 Am29BDS320G 37 Preliminary START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 4. Data# Polling Algorithm RDY: Ready The RDY is a dedicated output that, by default, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. RDY functions only while reading data in burst mode. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. 38 Am29BDS320G 27243B1 October 1, 2003 Preliminary DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 4 (toggle bit flowchart), DQ6: To g g l e B i t I ( d e s c r i p t i o n ) , F i g u r e 2 8 , “ To g g l e B i t T i m i n g s (During Embedded Algorithm),” on page 64 (toggle bit timing diagram), and Table 15, “DQ6 and DQ2 Indications,” on page 41. October 1, 2003 27243B1 Am29BDS320G 39 Preliminary START Read DQ7–DQ0 Read DQ7–DQ0 Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 5. Toggle Bit Algorithm DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which 40 Am29BDS320G 27243B1 October 1, 2003 Preliminary sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 5, “Toggle Bit Algorithm,” on page 40, See “DQ6: Toggle Bit I” on page 39., Figure 28, “Toggle Bit Timings (During Embedded Algorithm),” on page 64, and Table 15, “DQ6 and DQ2 Indications,” on page 41. Table 15. If device is programming, and the system reads at any address, DQ6 and DQ2 Indications then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable. actively erasing, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at any address, erase suspended, programming in erase suspend Reading Toggle Bits DQ6/DQ2 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. October 1, 2003 27243B1 Am29BDS320G 41 Preliminary The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 16 shows the status of DQ3 relative to the other status bits. Table 16. Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead (Note 4) Erase Suspended Sector Write Operation Status DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A Erase Suspend Mode Non-Erase Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in non-erase-suspended mode. 42 Am29BDS320G 27243B1 October 1, 2003 Preliminary Absolute Maximum Ratings Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . –0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +3.5 V ACC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V Output Short Circuit Current (Note 3)100 mA Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns during voltage transitions inputs might overshoot to VCC +0.5 V for periods up to 20 ns. See Figure 6. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 7. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V –0.5 V –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns Figure 6. Maximum Negative Overshoot Waveform Figure 7. Maximum Positive Overshoot Waveform Operating Ranges Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Supply Voltages VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.65 V to +1.95 V VIO Supply Voltages: VIO ≤ VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65 V to +1.95 V VIO > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 to +3.15 V Operating ranges define those limits between which the functionality of the device is guaranteed. October 1, 2003 27243B1 Am29BDS320G 43 Preliminary DC Characteristics CMOS Compatible Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions (Note 1,2) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, ICCB VCC Active Burst Read Current 54 MHz CE# = VIL, OE# = VIH, WE# = VIH, 40 MHz IIO VIO Non-active Output VCC Active Asynchronous Read Current (Note 3) VIO = 1.8 V, OE# = VIH VIO = 3.0 V, OE# = VIH CE# = VIL, OE# = VIH, WE# = VIH 5 MHz 1 MHz 10 8 0.2 0.2 12 3.5 15 0.2 0.2 25 –0.5 –0.5 VIO – 0.2 VIO – 0.4 min, min, Min Typ. Max ±1 ±1 20 16 10 10 16 5 40 10 10 60 0.2 0.4 VIO + 0.2 VIO + 0.4 0.1 Unit µA µA mA mA µA µA mA mA mA µA µA mA V V V V V V ICC1 ICC2 ICC3 ICC4 ICC5 VIL VCC Active Write Current (Note 4) CE# = VIL, OE# = VIH, VPP = VIH VCC Standby Current (Note 5) VCC Reset Current VCC Active Current (Read While Write) Input Low Voltage CE# = RESET# = VCC ± 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH VIO = 1.8 V VIO = 3.0 V VIO = 1.8 V VIO = 3.0 V IOL = 100 µA, VCC = VCC VIO = VIO min VIH VOL VOH VID VLKO Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage IOH = –100 µA, VCC = VCC VIO = VIO min VIO – 0.1 11.5 1.0 12.5 1.4 V V Notes: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. All ICC specifications are tested with VIO = VCC. 3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 44 Am29BDS320G 27243B1 October 1, 2003 Preliminary Test Conditions Table 17. Test Condition Device Under Test CL Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Specifications All Speed Options Unit 30 5 0.0–VIO VIO/2 VIO/2 pF ns V V V Note: Diodes are IN3064 or equivalent Figure 8. Test Setup Key to Switching Waveforms WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS Switching Waveforms All Inputs and Outputs VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output Figure 9. Input Waveforms and Measurement Levels October 1, 2003 27243B1 Am29BDS320G 45 Preliminary AC Characteristics VCC and VIO Power-up Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Test Setup Min Min Min Speed 50 50 50 Unit µs µs µs tVCS VCC tVIOS VIO tRSTH RESET# Figure 10. VCC and VIO Power-up Diagram 46 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Synchronous/Burst Read Parameter JEDEC Standard Description tIACC Parameter JEDEC Standard Description tIACC tBACC tACS tACH tBDH tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD tACC Latency—(Standard Handshaking or Odd Address in Handshake mode) Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note Note:) Address Hold Time from CLK (Note Note:) Data Hold Time from Next Clock Cycle Output Enable to Output Valid Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note Note:) Address Hold Time to AVD# (Note Note:) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Access Time Max Max Min Min Min Max Max Max Min Min Max Min Min Min Min Min Max 5 13.5 4.5 14 5 7 0 5 12 70 10 10 13.5 10.5 10.5 5 5 20 4.5 20 10 10 Latency (Even Address in Reduced Wait-State Handshaking Mode) Max D8 D3 C8 C3 (54 MHz) (54 MHz) (40 MHz) (40 MHz) 87.5 95 Unit ns D8, D9 D3, D4 C8, C9 C3, C4 (54 MHz) (54 MHz) (40 MHz) (40 MHz) 106 13.5 5 7 3 20 10.5 10.5 120 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. October 1, 2003 27243B1 Am29BDS320G 47 Preliminary AC Characteristics 7 cycles for initial access shown. tCES CE# 1 CLK tAVC AVD# tACS A20-A0 Aa tCEZ 2 3 4 5 6 7 tAVD tBDH tACH tBACC Hi-Z DQ15-DQ0 tIACC tACC OE# Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tOE RDY tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. Figure 11. CLK Synchronous Burst Mode Read (rising active CLK) 48 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics 4 cycles for initial access shown. tCES CE# 1 CLK tAVC AVD# tACS A20-A0 Aa tCEZ 2 3 4 5 tAVD tBDH tACH tBACC Hi-Z DQ15-DQ0 tIACC tACC OE# Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tOE RDY tRDYS Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. In the Burst Mode Configuration Register, A17 = 0. Figure 12. CLK Synchronous Burst Mode Read (Falling Active Clock) October 1, 2003 27243B1 Am29BDS320G 49 Preliminary AC Characteristics 7 cycles for initial access shown. tCAS CE# 1 CLK tAVC AVD# tAAS A20-A0 Aa tCEZ 2 3 4 5 6 7 tAVD tBDH tAAH tBACC Hi-Z DQ15-DQ0 tIACC tACC OE# Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tOE RDY tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. In the Burst Mode Configuration Register, A17 = 1. Figure 13. Synchronous Burst Mode Read 7 cycles for initial access shown. 18.5 ns typ. (54 MHz) tCES CE# 1 CLK tAVDS AVD# tACS A20-A0 Aa 2 3 4 5 6 7 tAVD tBDH tACH tBACC tIACC tACC D6 DQ15-DQ0 D7 D0 D1 D5 D6 OE# tOE RDY Hi-Z tRACC tRDYS Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the 7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data. Figure 14. 8-word Linear Burst with Wrap Around 50 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics 6 wait cycles for initial access shown. 25 ns typ. (40 MHz) tCES CE# 1 CLK tAVDS AVD# tACS A20-A0 Aa tCEZ 6 2 3 4 5 tAVD tBDH tACH tBACC Hi-Z DQ15-DQ0 tIACC tACC OE# tOE RDY Hi-Z D0 D1 D2 D3 Da + n tRACC tOEZ Hi-Z tRDYS Note: Figure assumes 6 wait states for initial access, 40 MHz clock, and synchronous read. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 15. Burst with RDY Set One Cycle Before Data October 1, 2003 27243B1 Am29BDS320G 51 Preliminary AC Characteristics 7 cycles for initial access shown. tCAS CE# 1 CLK tAVC AVD# tAAS A20-A0 Aa tCEZ 2 3 4 5 6 7 tAVD tBDH tAAH tBACC Hi-Z DQ15-DQ0 tIACC tACC OE# tOE RDY Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tRDYS Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst Mode Read Starting at an Even Address 52 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics 7 cycles for initial access shown. tCAS CE# 1 CLK tAVC AVD# tAAS A20-A0 Aa tCEZ 2 3 4 5 6 7 8 tAVD tBDH tBACC Hi-Z tAAH DQ15-DQ0 tIACC tACC OE# tOE RDY Hi-Z Da Da + 1 Da + n tOEZ tRACC Hi-Z tRDYS Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode. October 1, 2003 27243B1 Am29BDS320G 53 Preliminary AC Characteristics Asynchronous Read Parameter JEDEC Standard Description tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Access Time from CE# Low Asynchronous Access Time (Note 1) AVD# Low Time Address Setup Time to Rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Output Enable Hold Time Read Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min 10 0 13.5 0 10 10.5 D3, D4 D8, D9 (54 MHz) 70 70 12 5 7 20 C3, C4 C8, C9 (40 MHz) 90 90 Unit ns ns ns ns ns ns ns ns ns ns Output Enable to High Z (Note 2) CE# Setup Time to AVD# Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. CE# tOE tOEH WE# DQ15-DQ0 tACC A20-A0 tCAS AVD# tAVDP tAAVDS Note: RA = Read Address, RD = Read Data. OE# tCE Valid RD tOEZ RA tAAVDH Figure 18. Asynchronous Mode Read with Latched Addresses 54 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics CE# tOE tOEH WE# DQ15-DQ0 tACC A20-A0 RA tCE Valid RD tOEZ OE# AVD# Note: RA = Read Address, RD = Read Data. Figure 19. Asynchronous Mode Read October 1, 2003 27243B1 Am29BDS320G 55 Preliminary AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std tReadyw tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min All Speed Options 35 500 500 200 20 Unit µs ns ns ns µs Note: Not 100% tested. CE#, OE# tRH RESET# tRP tReadyw Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE#, OE# tReady RESET# tRP Figure 20. Reset Timings 56 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX Standard tWC tAS tAH tACS tACH tDVWH tWHDX tGHWL tWHEH tWLWH tWHWL tWHWH1 tWHWH1 tWHWH2 tDS tDH tGHWL tCAS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tVID tVIDS tVCS tCSW1 tCSW2 tCHW tELWL tCS tAVSW tAVHW tAVHC tAVDP Notes: 1. Not 100% tested. 2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 3. See the “Erase and Programming Performance” section for more information. 4. Does not include the preprogramming time. Description Write Cycle Time (Note 1) Address Setup Time (Note 2) Address Hold Time (Note 2) Synchronous Asynchronous Synchronous Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min Min Min Max Min Min Min Min Min All Speed Options 80 5 0 7 45 5 7 45 0 0 0 0 50 30 0 8 2.5 0.4 28 500 1 50 5 1 1 0 5 5 5 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs sec ns µs µs ns ns ns ns ns ns ns ns Address Setup Time to CLK (Note 2) Address Hold Time to CLK (Note 2) Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 3) Accelerated Programming Operation (Note 3) Sector Erase Operation (Notes 3, 4) Chip Erase Operation (Notes 3, 4) VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time Clock Setup Time to WE# (Asynchronous) Clock Setup Time to WE# (Synchronous) Clock Hold Time from WE# CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Hold Time to CLK AVD# Low Time October 1, 2003 27243B1 Am29BDS320G 57 Preliminary AC Characteristics Program Command Sequence (last two cycles) tCSW1 VIH Read Status Data CLK VIL tAVSW tAVHW AVD tAS tAH Addresses 555h PA VA In Progress tAVDP VA Data A0h tDS tDH PD Complete CE# OE# tWP WE# tCH tWHWH1 tCS tWC tVCS VCC tWPH Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A20–A12 are don’t care during command sequence unlock cycles. 4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 21. Asynchronous Program Operation Timings 58 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Program Command Sequence (last two cycles) tCHW Read Status Data VIH CLK VIL tAVSW tAVHW AVD tAS tAH Addresses 555h PA VA In Progress tAVDP VA Data A0h tDS tDH PD Complete CE# OE# tWP WE# tCH tWHWH1 tCS tWC tVCS VCC tWPH Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A20–A12 are don’t care during command sequence unlock cycles. 4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 22. Alternate Asynchronous Program Operation Timings October 1, 2003 27243B1 Am29BDS320G 59 Preliminary AC Characteristics Program Command Sequence (last two cycles) Read Status Data CLK tACS tAS AVD tAH tAVDP Addresses 555h PA VA In Progress VA Data tCAS CE# A0h PD tDS tDH Complete OE# tAVSW tWP tCH WE# tWHWH1 tCSW2 tWC tWPH tVCS VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A20–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CS# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 7. CLK must not have an active edge while WE# is at VIL. 8. AVD# must toggle during command sequence unlock cycles. Figure 23. Synchronous Program Operation Timings 60 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Program Command Sequence (last two cycles) tAVHC CLK tACS tAS AVD tAH Addresses 555h Read Status Data (Note 8) tAVDP PA VA In Progress VA Data tCAS CE# A0h PD tDS tDH Complete OE# tCSW2 tWP tCH WE# tWHWH1 tWC tWPH tVCS VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A20–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CS# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 7. AVD# must toggle during command sequence unlock cycles. 8. tAH = 45 ns. 9. CLK must not have an active edge while WE# is at VIL. Figure 24. Alternate Synchronous Program Operation Timings October 1, 2003 27243B1 Am29BDS320G 61 Preliminary AC Characteristics VIH Erase Command Sequence (last two cycles) Read Status Data CLK VIL tAVDP AVD# tAS Addresses 2AAh tAH SA 555h for chip erase 10h for chip erase VA In Progress VA Data 55h 30h tDS tDH Complete CE# OE# tWP WE# tCS tCH tWHWH2 tWPH tWC tVCS VCC Figure 25. Chip/Sector Erase Command Sequence Notes: 1. SA is the sector address for Sector Erase. 2. Address bits A20 –A12 are don’t cares during unlock cycles in the command sequence. 62 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics CE# AVD# WE# Addresses Data Don't Care A0h PA Don't Care PD Don't Care OE# ACC VID 1 ms tVIDS tVID VIL or VIH Note: Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing October 1, 2003 27243B1 Am29BDS320G 63 Preliminary AC Characteristics AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ Data Status Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. AVD# must toggle between data reads. Figure 27. Data# Polling Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA tOE tOEZ tCEZ Data Status Data Status Data Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. AVD# must toggle between data reads. Figure 28. Toggle Bit Timings (During Embedded Algorithm) 64 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics CE# CLK AVD# Addresses VA VA OE# tIACC tIACC Status Data Status Data Data RDY Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RDY is active one clock cycle before data. 4. AVD# must toggle between data reads. Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings October 1, 2003 27243B1 Am29BDS320G 65 Preliminary AC Characteristics Address boundary occurs every 64 words, beginning at address 00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing. C60 CLK Address (hex) AVD# 3C (stays high) C61 3D C62 3E C63 3F C63 3F C63 3F C64 40 C65 41 C66 42 C67 43 tRACC RDY (Note 1) tRACC RDY (Note 2) latency latency tRACC tRACC Data D60 D61 D62 D63 D64 D65 D66 D67 OE#, CE# (stays low) Notes: 1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register). 2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. Figure 30. Latency with Boundary Crossing 66 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Address boundary occurs every 64 words, beginning at address 00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing C60 CLK Address (hex) AVD# 3C (stays high) C61 3D C62 3E C63 3F C63 3F C63 3F C64 40 tRACC RDY (Note 1) tRACC RDY (Note 2) latency latency tRACC tRACC Data D60 D61 D62 D63 Invalid Read Status OE#, CE# (stays low) Notes: 1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register). 2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. Figure 31. Latency with Boundary Crossing into Program/Erase Bank October 1, 2003 27243B1 Am29BDS320G 67 Preliminary AC Characteristics Data D0 D1 AVD# Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD# falling edge OE# 1 CLK 0 1 2 3 4 5 6 7 2 3 4 5 number of clock cycles programmed Note: A14, A14, A14, A14, A14, A14, A13, A13, A13, A13, A13, A13, A12 A12 A12 A12 A12 A12 = = = = = = “101” “100” “011” “010” “001” “000” ⇒ 5 programmed, 7 total ⇒ 4 programmed, 6 total ⇒ 3 programmed, 5 total ⇒ 2 programmed, 4 total ⇒ 1 programmed, 3 total ⇒ 0 programmed, 2 total Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 32. Example of Wait States Insertion (Standard Handshaking Device) 68 Am29BDS320G 27243B1 October 1, 2003 Preliminary AC Characteristics Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tWC tRC tRC tWC CE# OE# tOE tOEH WE# tWPH tWP tDS Data PD/30h tGHWL tACC tDH RD tOEZ tOEH RD AAh tSR/W Addresses PA/SA RA RA 555h tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 33. Back-to-Back Read/Write Cycle Timings October 1, 2003 27243B1 Am29BDS320G 69 Preliminary Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Word Programming Time Accelerated Word Programming Time Chip Programming Time (Note 3) Accelerated Chip Programming Time Typ (Note 1) 0.4 28 11.5 4 25 9 210 120 75 27 Max (Note 2) 5 Unit s s µs µs s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles. FBGA Ball Capacitance Parameter Symbol CIN COUT CIN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4.2 5.4 3.9 Max 5.0 6.5 4.7 Unit pF pF pF Data Retention Parameter Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years 70 Am29BDS320G 27243B1 October 1, 2003 Preliminary Physical Dimensions VBD064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm Package D 0.05 C (2X) A D1 8 7 e E 6 5 4 3 2 1 HGFEDCBA 7 SE E1 INDEX MARK PIN A1 CORNER 10 B 6 NXφb φ 0.08 M C φ 0.15 M C A B SD A1 CORNER TOP VIEW 0.05 C (2X) BOTTOM VIEW A A1 SEATING PLANE A2 0.10 C C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC VBD 064 N/A 8.95 mm x 7.95 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.30 MIN --0.20 0.62 NOM ------8.95 BSC. 7.95 BSC. 5.60 BSC. 5.60 BSC. 8 8 64 0.35 0.80 BSC. 0.40 BSC. NONE 0.40 MAX 1.00 0.30 0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Note: BSC is an ANSI standard for Basic Space Centering. October 1, 2003 27243B1 Am29BDS320G 71 Preliminary Revision Summary Revision A (November 22, 2002) Initial release. Revision A + 1 (March 7, 2003) Autoselect Command Sequence Updated Table 3. Command Definitions Updated Table 14, Device ID Sixth Cycle. Revision B (August 12, 2003) Global Updated formatting to new Spansion template. Sector Lock/Unlock Command Sequence Modified description of write cycles. Reset Command Modified last paragraph of section. Table 14, Command Definitions Added note references to Erase Suspend and Sector Lock/Unlock rows in table. Replaced addresses “XXX” with “BA” in first and second cycles of Sector Lock/Unlock table row. Modified description of BA in legend. Revision B + 1 (October 1, 2003) DC Characteristics - CMOS Compatible Added note #2. Modified column heading from Test Conditions (Note 1) to Test Conditions (Note 1,2). Trademarks and Notice This document contains FASL confidential information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from FASL. The information in this document is subject to change without notice. Product and Company names are trademarks or registered trademarks of their respective owners Copyright 2003 FASL LLC. All rights reserved. 72 Am29BDS320G 27243B1 October 1, 2003