MB84VP23481FK-70

FUJITSU SEMICONDUCTOR DATA SHEET DS05-50224-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM CMOS 64M (×16) Page FLASH MEMORY & 32M (×16) Mobile FCRAMTM MB84VP23481FK-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 25 ns maximum page read access time, 65 ns maximum random access time (Flash) 20 ns maximum page read access time, 70 ns maximum random access time (FCRAM) • Operating Temperature –30 °C to +85 °C • Package 65-ball FBGA (Continued) s PRODUCT LINEUP Flash Supply Voltage (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 3.0 V 65 25 65 25 +0.1V –0.3 V FCRAM VCCr* = 3.0 V –0.3 V 70 20 70 40 +0.1V *: Both VCCf and VCCr must be the same level when either part is being accessed. s PACKAGE 65-ball plastic FBGA (BGA-65P-M01) MB84VP23481FK-70 (Continued) — FLASH MEMORY • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM *1 Bank A: 8 Mbit (8 KB ×8 and 64 KB ×15) Bank B: 24 Mbit (64 KB ×48) Bank C: 24 Mbit (64 KB ×48) Bank D: 8 Mbit (8 KB ×8 and 64 KB ×15) • 8 words Page • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Minimum 100,000 Program/Erase Cycles • Sector Erase Architecture Eight 8 Kbytes, a hundred twenty-six 64 Kbytes, eight 8 Kbytes sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase • Dual Boot Block Sixteen to 8Kbytes boot block sectors, eight at the top of the address range and eight at the bottom of the address range • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • New Sector Protection Persistent Sector Protection Password Sector Protection • Please refer to “MBM29QM64DF” Datasheet in Detailed Function (Continued) 2 MB84VP23481FK-70 (Continued) — FCRAMTM *3 • Power Dissipation Operating : 30 mA Max Standby : 100 µA Max • Power Down Mode Sleep : 10 µA Max 4M Partial : 45 µA Max 8M Partial : 55 µA Max 16M Partial: 70 µA Max • Power Down Control by CE2r • Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) • 8 words Page Access Capability *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan. 3 MB84VP23481FK-70 s PIN ASSIGNMENT (Top View) Marking Side A10 N.C. A9 N.C. B8 A11 B7 A8 B6 WE B5 WP/ACC B4 LB B3 A7 A2 N.C. A1 N.C. B1 N.C. C9 A15 C8 A12 C7 A19 C6 CE2r C5 RESET C4 UB C3 A6 C2 A3 D9 A21 D8 A13 D7 A9 D6 A20 D5 RY/BY D4 A18 D3 A5 D2 A2 E4 A17 E3 A4 E2 A1 F4 DQ1 F3 VSS F2 A0 E9 N.C. E8 A14 E7 A10 F9 A16 F8 N.C F7 DQ6 G9 N.C G8 DQ15 G7 DQ13 G6 DQ4 G5 DQ3 G4 DQ9 G3 OE G2 CEf H9 Vss H8 DQ7 H7 DQ12 H6 Vccr H5 Vccf H4 DQ10 H3 DQ0 H2 CE1r J8 DQ14 J7 DQ5 J6 N.C J5 DQ11 J4 DQ2 J3 DQ8 K10 N.C. K9 N.C. K2 N.C. K1 N.C. (BGA-65P-M01) 4 MB84VP23481FK-70 s PIN DESCRIPTION Pin name A20 to A0 A21 DQ15 to DQ0 CEf CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCr Input/ Output I I I/O I I I I I O I I I I — Power Power Power Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Description 5 MB84VP23481FK-70 s BLOCK DIAGRAM VCCf A21 to A0 A21 to A0 WP/ACC RESET CEf VSS RY/BY 64 M bit Page Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 LB UB WE OE CE1r CE2r 32 M bit FCRAM VSS 6 MB84VP23481FK-70 s DEVICE BUS OPERATIONS Operation*1, *2 Full Standby Output Disable*3 Read from Flash*4 Write to Flash CEf H H L L L CE1r CE2r OE WE H L H H H H H H H X H L H X H H L LB X X X X L Read from FCRAM H L H L H H L FCRAM No Read H L H L H H L Write to FCRAM H L H H*7 L H L FCRAM No Write Flash Temporary Sector Group Unprotection*5 Flash Hardware Reset Flash Boot Block Sector Write Protection FCRAM Power Down*6 H X X X X L X H X X H X H X L H*7 X X X X L X X X X H X X X X UB X X X X L L H H L L H H X X X X Valid X X X X Valid Valid Valid A21 to A0 X X*8 Valid Valid DQ7 to DQ0 High-Z High-Z DOUT DIN DIN High-Z DIN High-Z DIN High-Z DIN High-Z X High-Z X X DQ15 to RESET WP/ACC*9 DQ8 High-Z High-Z DOUT DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X H VID L X X X X X L X H X H X H X H H H H X X X X Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See sDC CHARACTERISTICS for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : Do not apply for two or more states of the following conditions at the same time; • CEf = VIL • CE1r = VIL and CE2r = VIH *3 : Should not be kept FCRAM Output Disable condition longer than 1µs. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : It is also used for the extended sector group protections. *6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Please refer to “Power Down Program” in FCRAM Characteristics part. *7 : OE can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous operation cycle is satisfied. 2) OE stays VIL during Write cycle. *8 : Can be either VIL or VIH but must be valid before Read or Write. *9 : Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors. 7 MB84VP23481FK-70 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCr Supply *1 RESET *2 WP/ACC *3 Symbol Tstg TA VIN, VOUT VCCf, VCCr VIN VIN Rating Min –55 –30 –0.3 –0.3 –0.5 –0.5 Max +125 +85 VCCf + 0.3 VCCr + 0.3 +3.3 + 13.0 +10.5 Unit °C °C V V V V V *1 Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCr Supply Voltages Symbol TA VCCf, VCCr Value Min –30 +2.7 Max +85 +3.1 Unit °C V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 8 MB84VP23481FK-70 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current (Flash) WP/ACC Acceleration Program Current (Flash) Flash VCC Active Current *1,*6 (Initial/Random Read) Flash VCC Active Current *2 Flash VCC Current (Page Mode) *9,*6 Flash VCC Active Current*5,*6 (Read-While-Program) Flash VCC Active Current*5,*6 (Read-While-Erase) Flash VCC Active Current*5,*6 (Erase-Suspend-Program) Flash VCC Current (Standby) *6 Flash VCC Current (Standby, Reset) *6 Flash VCC Current (Automatic Sleep Mode)*3 Symbol ILI ILO ILIT ILIA Conditions VIN = VSS to VCCf, VCCr Value Min –1.0 Typ Max — — — — — — — — — — — 1 1 1 — — — +1.0 +1.0 35 20 45 20 25 10 45 45 25 5 5 5 30 mA — — 3 10 mA Unit µA µA µA mA mA mA mA mA mA mA mA µA µA µA VOUT = VSS to VCCf, VCCr, Output Disable –1.0 VCCf = VCCf Max, RESET = 12.5 V VCCf = VCCf Max, WP/ACC = VACC Max CEf = VIL, OE = VIH, f = 10 MHz CEf = VIL, OE = VIH, f = 5 MHz CEf = VIL, OE = VIH CEf = VIL, OE = VIH, f = 40 MHz CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCf = VCCf Max,CEf = VCCf ±0.3 V RESET= VCCf ±0.3 V, WP/ACC =VCCf ±0.3 V VCCf = VCCf Max, RESET= VSS ±0.3 V VCCf = VCCf Max, CEf= VSS ±0.3 V, RESET= VCCf ±0.3 V, VIN = VCCf ±0.3 V or VSSf±0.3 V VCCr = VCCr Max, CE1r = VIL, CE2r = VIH, VIN = VIH or VIL, IOUT = 0 mA*7 tRC / tWC =Min tRC / tWC =1µs — — — — — — — — — — — — — ICC1f ICC2f ICC3f ICC4f ICC5f ICC6f ISB1f ISB2f ISB3f ICC1r FCRAM VCC Active Current *6, *8 ICC2r FCRAM VCC Page Read Current *6, *8 ICC3r VCCr = VCCr Max, VIN = VIH or VIL, CE1r = VIL, CE2r = VIH, IOUT = 0 mA *7, tPRC=Min VCCr = VCCr Max, VIN < 0.2V or > VCCr – 0.2V CE1r > VCCr – 0.2V, CE2r > VCCr– 0.2V Sleep 4M Partial 8M Partial 16M Partial FCRAM VCC Standby Current *6, *8 ISB1r IDDPSr — — — — — — — — — — 100 10 45 55 70 µA µA µA µA µA FCRAM VCC Power Down Current *6, *8 IDDP4r VCCr = VCCr Max, CE2r < 0.2V, IDDP8r VIN = VIH or VIL IDDP16r (Continued) 9 MB84VP23481FK-70 (Continued) Parameter Input Low Level Input High Level Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 Output Low Voltage Level Output High Voltage Level Flash Low VCCf Lock-Out Voltage Symbol VIL VIH Conditions — — Value Min –0.3 VCC × 0.8 *6 11.5 Typ — — Max VCC × 0.2 *6 VCC + 0.2 *6 12.5 Unit V V VID — 12 V VACC VOLf VOLr VOHf VOHr VLKO — VCCf = VCCf Min, IOL=4.0 mA Flash 8.5 — — 2.4 2.4 2.3 9.0 — — — — 2.4 9.5 0.4 0.4 — — 2.5 V V V V V V VCCr = VCCr Min, IOL =1.0mA FCRAM VCCf = VCCf Min, IOH=–2.0 mA VCCr = VCCr Min, IOH=–0.5 mA Flash FCRAM — *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCCf applying. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6: VCC indicates lower of VCCf or VCCr. *7: FCRAM Characteristics are measured after following POWER-UP timing. *8: IOUT depends on the output load conditions. *9: Address except A2, A1 and A0 are fixed. 10 MB84VP23481FK-70 s AC CHARACTERISTICS • CE Timing Parameter CE Recover Time CE Hold Time CE1r High to WE Invalid time for Standby Entry Symbol JEDEC — — — Standard tCCR tCHOLD tCHWX Condition — — — Value Min 0 3 10 Max — — — Unit ns ns ns • Timing Diagram for alternating RAM to Flash CEf tCCR tCCR CE1r WE tCHWX tCHOLD tCCR tCCR CE2r • Flash Characteristics Please refer to “s64 M PAEG FLASH MEMORY CHARACTERISTICS for MCP”. • FCRAM Characteristics Please refer to “s32 M FCRAM CHARACTERISTICS for MCP”. 11 MB84VP23481FK-70 s 64 M PAEG FLASH MEMORY CHARACTERISTICS for MCP 1. Flexible Sector-erase Architecture on FLASH MEMORY • Sixteen 4K words, and one hundred twenty-six 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. SA0 : 8KB (4KW) SA1 : 8KB (4KW) SA2 : 8KB (4KW) SA3 : 8KB (4KW) SA4 : 8KB (4KW) SA5 : 8KB (4KW) SA6 : 8KB (4KW) SA7 : 8KB (4KW) SA8 : 64KB (32KW) SA9 : 64KB (32KW) SA10 : 64KB (32KW) SA11 : 64KB (32KW) SA12 : 64KB (32KW) SA13 : 64KB (32KW) SA14 : 64KB (32KW) SA15 : 64KB (32KW) SA16 : 64KB (32KW) SA17 : 64KB (32KW) SA18 : 64KB (32KW) SA19 : 64KB (32KW) SA20 : 64KB (32KW) SA21 : 64KB (32KW) SA22 : 64KB (32KW) SA23 : 64KB (32KW) SA24 : 64KB (32KW) SA25 : 64KB (32KW) SA26 : 64KB (32KW) SA27 : 64KB (32KW) SA28 : 64KB (32KW) SA29 : 64KB (32KW) SA30 : 64KB (32KW) SA31 : 64KB (32KW) SA32 : 64KB (32KW) SA33 : 64KB (32KW) SA34 : 64KB (32KW) SA35 : 64KB (32KW) SA36 : 64KB (32KW) SA37 : 64KB (32KW) SA38 : 64KB (32KW) SA39 : 64KB (32KW) SA40 : 64KB (32KW) SA41 : 64KB (32KW) SA42 : 64KB (32KW) SA43 : 64KB (32KW) SA44 : 64KB (32KW) SA45 : 64KB (32KW) SA46 : 64KB (32KW) SA47 : 64KB (32KW) SA48 : 64KB (32KW) SA49 : 64KB (32KW) SA50 : 64KB (32KW) SA51 : 64KB (32KW) SA52 : 64KB (32KW) SA53 : 64KB (32KW) SA54 : 64KB (32KW) SA55 : 64KB (32KW) SA56 : 64KB (32KW) SA57 : 64KB (32KW) SA58 : 64KB (32KW) SA59 : 64KB (32KW) SA60 : 64KB (32KW) SA61 : 64KB (32KW) SA62 : 64KB (32KW) SA63 : 64KB (32KW) SA64 : 64KB (32KW) SA65 : 64KB (32KW) SA66 : 64KB (32KW) SA67 : 64KB (32KW) SA68 : 64KB (32KW) SA69 : 64KB (32KW) SA70 : 64KB (32KW) Word Mode 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh SA71 : 64KB (32KW) SA72 : 64KB (32KW) SA73 : 64KB (32KW) SA74 : 64KB (32KW) SA75 : 64KB (32KW) SA76 : 64KB (32KW) SA77 : 64KB (32KW) SA78 : 64KB (32KW) SA79 : 64KB (32KW) SA80 : 64KB (32KW) SA81 : 64KB (32KW) SA82 : 64KB (32KW) SA83 : 64KB (32KW) SA84 : 64KB (32KW) SA85 : 64KB (32KW) SA86 : 64KB (32KW) SA87 : 64KB (32KW) SA88 : 64KB (32KW) SA89 : 64KB (32KW) SA90 : 64KB (32KW) SA91 : 64KB (32KW) SA92 : 64KB (32KW) SA93 : 64KB (32KW) SA94 : 64KB (32KW) SA95 : 64KB (32KW) SA96 : 64KB (32KW) SA97 : 64KB (32KW) SA98 : 64KB (32KW) SA99 : 64KB (32KW) SA100 : 64KB (32KW) SA101 : 64KB (32KW) SA102 : 64KB (32KW) SA103 : 64KB (32KW) SA104 : 64KB (32KW) SA105 : 64KB (32KW) SA106 : 64KB (32KW) SA107 : 64KB (32KW) SA108 : 64KB (32KW) SA109 : 64KB (32KW) SA110 : 64KB (32KW) SA111 : 64KB (32KW) SA112 : 64KB (32KW) SA113 : 64KB (32KW) SA114 : 64KB (32KW) SA115 : 64KB (32KW) SA116 : 64KB (32KW) SA117 : 64KB (32KW) SA118 : 64KB (32KW) SA119 : 64KB (32KW) SA120 : 64KB (32KW) SA121 : 64KB (32KW) SA122 : 64KB (32KW) SA123 : 64KB (32KW) SA124 : 64KB (32KW) SA125 : 64KB (32KW) SA126 : 64KB (32KW) SA127 : 64KB (32KW) SA128 : 64KB (32KW) SA129 : 64KB (32KW) SA130 : 64KB (32KW) SA131 : 64KB (32KW) SA132 : 64KB (32KW) SA133 : 64KB (32KW) SA134 : 8KB (4KW) SA135 : 8KB (4KW) SA136 : 8KB (4KW) SA137 : 8KB (4KW) SA138 : 8KB (4KW) SA139 : 8KB (4KW) SA140 : 8KB (4KW) SA141 : 8KB (4KW) Word Mode 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h 3FFFFFh Bank A Bank C Bank B Bank D Sector Architecture 12 MB84VP23481FK-70 • FlexBankTM Architecture Bank Splits 1 2 3 4 Bank 1 Volume 8 Mbit 24 Mbit 24 Mbit 8 Mbit Combination Bank A Bank B Bank C Bank D Volume 56 Mbit 40 Mbit 40 Mbit 56 Mbit Bank 2 Combination Remainder (Bank B, C, D) Remainder (Bank A, C, D) Remainder (Bank A, B, D) Remainder (Bank A, B, C) • Example of Virtual Banks Combination Bank 1 Bank Splits Volume Combination Sector Size Volume 1 8 Mbit Bank A 8 × 8 Kbyte/4 Kword + 56 Mbit 15 × 64 Kbyte/32 Kword 16 × 8 Kbyte/4 Kword + 48 Mbit 30 × 64 Kbyte/32 Kword 48 × 64 Kbyte/32 Kword 40 Mbit 2 16 Mbit Bank A + Bank D 3 24 Mbit Bank B 4 32 Mbit Bank A + Bank B 8 × 8 Kbyte/4 Kword + 32 Mbit 63 × 64 Kbyte/32 Kword Bank 2 Combination Sector Size Bank B + 8 × 8 Kbyte/4 Kword Bank C + + 111 × 64 Kbyte/32 Kword Bank D Bank B + 96 × 64 Kbyte/32 Kword Bank C Bank A + 16 × 8 Kbyte/4 Kword Bank C + + 78 × 64 Kbyte/32 Kword Bank D Bank C 8 × 8 Kbyte/4 Kword + + Bank D 63 × 64 Kbyte/32 Kword Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. 13 MB84VP23481FK-70 • Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode * Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C and Bank D. Bank Address (BA) meant to specify each of the Banks. 14 MB84VP23481FK-70 • Sector Address Tables Sector Address Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Address Range A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bank Address A21 A20 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X Word Mode 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh Bank A (Continued) 15 MB84VP23481FK-70 Sector Address Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Address Range A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Bank Address A21 A20 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Word Mode 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh Bank B (Continued) 16 MB84VP23481FK-70 Sector Address Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 Address Range A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Bank Address A21 A20 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Word Mode 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh Bank C (Continued) 17 MB84VP23481FK-70 (Continued) Sector Address Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Address Range A14 X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 Bank Address A21 A20 A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A13 X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Word Mode 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh Bank D 18 MB84VP23481FK-70 • Sector Group Addresses Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 19 MB84VP23481FK-70 • Flash Memory Autoselect Codes Type Manufacture’s Code Device Code Extended Device Code*2 A21 to A12 BA BA BA BA Sector Group Addresses A6 VIL VIL VIL VIL VIL A5 x x x x VIH A4 x x x x VIH A3 VIL VIL VIH VIH VIH A2 VIL VIL VIH VIH VIL A1 VIL VIL VIH VIH VIH A0 VIL VIH VIL VIH VIL Code (HEX) 04h 227Eh 2215h 2201h 01h*1 Sector Group Protection*1 *1:Sector Group can be protected by “Sector Group Protection”, “Extended Sector Group Protection” and “New Sector Protection (PPB Protection)”. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh 20 MB84VP23481FK-70 • Flash Memory Command Definitions Command Sequence Second Seventh Bus First Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Bus Bus Write Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 2 4 3 4 6 6 1 XXXh F0h 555h 555h 555h 555h 555h BA RA RD 55h 55h 55h 55h 55h — — 555h (BA) 555h 555h 555h 555h — — F0h 90h A0h 80h 80h — — RA — PA 555h 555h — — RD — PD — — — — — — — — 55h 55h — — — — — 555h SA — — — — — 10h 30h — — — — — — — — — — — — — — — Read/Reset *1 Read/Reset *1 Autoselect Program Chip Erase Sector Erase Program/Erase Suspend Program/Erase Resume Set to Fast Mode Fast Program *2 Reset from Fast Mode *2 Extended Sector Group Protection*3 Query *4 HiddenROM Entry HiddenROM Program *5 HiddenROM Exit *5 HiddenROM Protect *5 AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh B0h — AAh 2AAh AAh 2AAh — — 1 3 2 2 BA 555h 30h — — 55h PD — 555h — — — 20h — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — AAh 2AAh PA XXXh A0h BA 90h XXXh F0h*6 4 XXXh 60h (BA) 55h 555h 555h SGA 60h SGA 40h SGA SD — — — — — — 1 3 4 98h — — 55h 55h — 555h 555h (HRBA) — 88h — — — — PD — — — — — — — — — — — — — — — — — — AAh 2AAh AAh 2AAh A0h (HRA) PA 4 555h AAh 2AAh 55h 555h 555h 90h XXXh 00h — — — — — — 6 555h AAh 2AAh 55h 60h OPBP 68h OPBP 48h XXXh RD(0) XX0h PD0 — — — — — — — — — — — — — — — — — — — — — — — — — — Password Program *7 XX1h PD1 4 555h AAh 2AAh 55h 555h 38h XX2h PD2 XX3h PD3 Password Unlock Password Verify 7 4 555h 555h AAh 2AAh AAh 2AAh 55h 55h 555h 555h 28h C8h XX0h PD0 XX1h PD1 XX2h PD2 XX3h PD3 PWA PWD — — — — — — (Continued) 21 MB84VP23481FK-70 (Continued) Command Sequence Second Seventh Bus First Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Bus Bus Write Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Password Mode Locking Bit Program Persistent Protection Mode Locking Bit Program PPB Program PPB Verify All PPB Erase *8 PPB Lock Bit Set PPB Lock Bit Verify DPB Write DPB Erase DPB Verify 6 555h AAh 2AAh 55h 555h 60h PL 68h PL 48h XXh RD(0) — — 6 555h AAh 2AAh 55h 555h 60h SPML 68h SPML 48h XXh RD(0) — — 6 4 6 3 4 4 4 4 555h 555h 555h 555h 555h 555h 555h 555h AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh 55h 55h 55h 55h 55h 55h 55h 55h 555h 555h 555h 555h 555h 555h 555h 555h 60h SA+WP 68h SA+WP 48h 90h SA+x02 RD(0) — — XXh — XXh — — — — — RD(0) — RD(0) — — — — — — — — — — — — — — — — — — — — — 60h SA+WP 60h SA+WP 40h 78h 58h 48h 48h 58h — SA SA SA SA — RD(1) X1h X0h RD(0) — — — — — — — — — — Legend: RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector BA = Bank Address RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SGA = Sector group address to be protected. Set sector group address and (A6, A5, A4, A3, A2, A1, A0) = (0, 1, 1, 1, 0, 1, 0) SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area (000000h to 00007Fh) HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL) RD(0) = DQ0 data, RD(1) = DQ1 data. PPB Lock bit is read on DQ1 and PPB or DPB are read on DQ0. If set, DQ0/DQ1=1. If cleared, DQ0/DQ1=0. OPBP = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 1, 0, 1, 0) SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked PWA/PWD = Password Address/Password Data PL = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 0, 1, 0, 1, 0) SPML = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 0, 0, 1, 0) WP = (A6, A5, A4, A3, A2, A1, A0) is (X, 1, 1, 1, 0, 1, 0) 22 MB84VP23481FK-70 *1: Both of these reset commands are equivalent. *2: This command is valid during Fast Mode. *3: This command is valid while RESET = VID. *4: The valid addresses are A6 to A0. *5: This command is valid during HiddenROM mode. *6: The data “00h” is also acceptable. *7: Data before fourth cycle also need to be programmed repearting from first cycle to third cycle. *8: RD(0) of the sixth cycle shows PPB erase status. When RD(0) is "1", programming must be repeated from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase. Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except for PA, SA, BA, SGA, OPBP SLA, PWA, PL, SPML, WP , . • Bus operations are defined in "s DEVICE BUS OPERATIONS". • The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • Command combinations not described in Command Definitions table are illegal. 23 MB84VP23481FK-70 2. AC Characteristics • Read Only Operations Characteristics Symbol Parameter JEDEC Read Cycle Time Address to Output Delay Page Read Cycle Time Page Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode tAVAV tAVQV — — tELQV tGLQV tEHQZ tGHQZ tAXQX — Standard tRC tACC tPRC tPACC tCE tOE tDF tDF tOH tREADY — CEf = VIL OE = VIL — CEf = VIL OE = VIL OE = VIL — — — — — Condition Min 65 — 25 — — — — — 4 — Max — 65 — 25 65 25 25 25 — 20 ns ns ns ns ns ns ns ns ns ns Value* Unit * : Test Conditions: Output Load:VCCf =2.7 V to 3.1 V:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCf Timing measurement reference level Input: 0.5 × VCCf Output: 0.5 × VCCf 24 MB84VP23481FK-70 • Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC tAVAV tAVWL — tWLAX — tDVWH tWHDX — — — tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 — — Standard tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVACCR Min 65 0 12 45 0 35 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 — — 50 500 Value Typ — — — — — — — — — — — — — — — — — — — — — 6 0.5 — — Max — — — — — — — — — — — — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs s µs ns CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Word Programming Operation Sector Erase Operation*1 VCC Setup Time Rise Time to VACC*2 (Continued) 25 MB84VP23481FK-70 (Continued) Parameter Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time Symbol JEDEC — — — — — — — Standard tRB tRP tRH tBUSY tEOE tTOW tSPD Min 0 500 200 — — 50 — Value Typ — — — — — — — Max — — — 90 65 — 20 Unit ns ns ns ns ns ns ns *1 : This does not include the preprogramming time. *2 : This timing is for Accelerated Program operation. 26 MB84VP23481FK-70 • Read Operation Timing Diagram tRC Address Address Stable tACC CEf tOE tDF OE tOEH WE tCE tOH Outputs High-Z Output Valid High-Z 27 MB84VP23481FK-70 • Page Read Operation Timing Diagram A21 to A3 Same page Addresses A2 to A0 Aa t t RC Ab t PRC Ac t PRC Ad t PRC Ae t PRC Af t PRC Ag t PRC Ah t PRC ACC CEf t OEH t CE OE WE t OE t t t PACC OH DF t t PACC OH t t PACC OH t t PACC OH t t PACC OH t t PACC OH t t PACC OH t Dh OH Output High-Z Da Db Dc Dd De Df Dg 28 MB84VP23481FK-70 • Hardware Reset/Read Operation Timing Diagram tRC Address tACC Address Stable CEf tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid 29 MB84VP23481FK-70 • Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Address 555h tWC tAS PA tAH Data Polling PA tRC CEf tCS tCH tCE OE tGHWL tWP tWPH tWHWH1 tOE WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. 30 MB84VP23481FK-70 • Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CEf tDS tDH PD DQ7 DOUT Data A0h Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. 31 MB84VP23481FK-70 • Chip/Sector Erase Operation Timing Diagram Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CEf tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 30h for Sector Erase 10h/ 30h Data tVCS VCCf * : SA is the sector address for Sector Erase. 32 MB84VP23481FK-70 • Data Polling during Embedded Algorithm Operation Timing Diagram CEf t CH t OE t DF OE t OEH WE t CE * DQ7 Data DQ7 DQ7 = Valid Data High-Z t WHWH1 or 2 DQ6 to DQ0 Data DQ6 to DQ0 = Output Flag t EOE DQ6 to DQ0 Valid Data High-Z * : DQ7 = Valid Data (The device has completed the Embedded operation). 33 MB84VP23481FK-70 • AC Waveforms for Toggle Bit I during Embedded Algorithm Operations Address tAHT tASO tAHT tAS CEf tCEPH WE tOEH tOEPH tOEH OE tDH tOE tCE DQ 6/DQ2 Data tBUSY Toggle Data Toggle Data Toggle Data * Stop Toggling Output Valid RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation). 34 MB84VP23481FK-70 • Bank-to-Bank Read/Write Timing Diagram Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC Address BA1 tAS BA2 (555h) tAH BA1 tACC tCE BA2 (PA) BA1 tAS tAHT BA2 (PA) CEf tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS tDH tDF DQ Valid Output Valid Intput (A0h) Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 35 MB84VP23481FK-70 • DQ2 vs. DQ6 Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note : DQ2 is read from the erase-suspended sector. • RY/BY Timing Diagram during Program/Erase Operation Timing Diagram CEf Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY 36 MB84VP23481FK-70 • RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY 37 MB84VP23481FK-70 • Temporary Sector Group Unprotection Timing Diagram VCCf tVCS tVIDR tVLHT VID VIH RESET CEf WE tVLHT Program Command Sequence tVLHT RY/BY Unprotection period 38 MB84VP23481FK-70 • Extended Sector Group Protection Timing Diagram VCCf tVCS RESET tVIDR tVLHT tWC tWC SGAX SGAX SGAY Address A6, A2, A0 A5, A4, A3, A1 CEf OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 39 MB84VP23481FK-70 • Accelerated Program Timing Diagram VCCf tVCS VACC VIH ACC tVACCR tVLHT CEf WE tVLHT Program Command Sequence Acceleration period tVLHT 40 MB84VP23481FK-70 3. Erase and Programming Performance Limits Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Note — — — 100,000 Typ 0.5 6 25.2 — Max 2.0 100 95 — s µs s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead — Unit Comments Typical Erase conditions TA = + 25°C, VCCf = 2.9 V Typical Program conditions TA = + 25°C, VCCf = 2.9 V, Data = Checker 41 MB84VP23481FK-70 s 32 M FCRAM CHARACTERISTICS for MCP 1. Power Down (32M Page Mode FCRAM) • Power Down (32M Page mode FCRAM) The Power Down is to enter low power idle state when CE2r stays Low. The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial. These can be programmed by series of read/write operation. Each mode has following features. Mode Sleep (default) 4M Partial 8M Partial 16M Partial Data Retention No 4M bit 8M bit 16M bit Retention Address N/A 00000h to 3FFFFh 00000h to 7FFFFh 00000h to FFFFFh The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. • Power Down Program Sequence (32M Page mode FCRAM) The program requires total 6 read/write operation with unique address and data. Between each read/write operation requires that device be in standby mode. Following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh Address Key Data Read Data (RDa) RDa RDa 0000h Data Key Read Data (RDb) The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0’s and data of fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also cancelled. The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle and address key must be the same mode for proper programming. Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used. 42 MB84VP23481FK-70 • Address Key (32M Page mode FCRAM) The address key has following format. Address A20 1 0 1 0 A19 1 1 0 0 A18 to A0 1 1 1 1 Binary 1FFFFFh 0FFFFFh 17FFFFh 07FFFFh Mode Sleep (default) 4M Partial 8M Partial 16M Partial • Data Key (32M Page mode FCRAM) The data key has following format. Mode Sleep (default) 4M Partial 8M Partial 16M Partial Data DQ15 to DQ8 0 0 0 0 DQ7 to DQ2 0 0 0 0 DQ1 1 1 0 0 DQ0 1 0 1 0 The upper byte of data code may be ignored and it is just for recommendation to write 0’s to upper byte for future compatibility. 43 MB84VP23481FK-70 2. AC Characteristics • READ OPERATION (32M Page mode FCRAM) Value Parameter Read Cycle Time CE1r Access Time OE Access Time Address Access Time LB / UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1r Low to Output Low-Z OE Low to Output Low-Z LB / UB Low to Output Low-Z CE1r High to Output High-Z OE High to Output High-Z LB / UB High to Output High-Z Address Setup Time to CE1r Low Address Setup Time to OE Low Address Invalid Time Page Address Invalid Time Address Hold Time from CE1r High Address Hold Time from OE High CE1r High Pulse Width Symbol Min tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tAXP tCHAH tOHAH tCP 70 — — — — — 25 5 3 0 0 — — — –5 10 — — –5 –5 15 Max 1000 70 40 70 30 18 1000 — — — — 20 20 20 — — 10 10 — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5, *8 *6, *8 *9 *1, *2 *3 *3 *3, *5 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *4 *4 *4 Unit Remarks *1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A20 to A3. If needed by system operation, please contact local FUJITSU representative for the relaxation of 1µs limitation. *2 : Address should not be changed within minimum tRC. *3 : The output load 30 pF. *4 : The output load 5 pF without any other load. *5 : Applicable to A20 to A3 when CE1r is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1r is kept at Low for the page address access. *7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. *8 : Applicable when at least two of address inputs among applicable are switched from previous state. *9 : tRC(Min) and tPRC(Min) must be satisfied. 44 MB84VP23481FK-70 • WRITE OPERATION (32M Page mode FCRAM) Value Parameter Write Cycle Time Address Setup Time CE1r Write Pulse Width WE Write Pulse Width LB / UB Write Pulse Width CE1r Write Recovery Time WE Write Recovery Time LB / UB Write Recovery Time Data Setup Time Data Hold Time Address Invalid Time after Write OE High to CE1r Low Setup Time for Write OE High to Address Setup Time for Write LB and UB Write Pulse Overlap CE1r High Pulse Width Symbol Min tWC tAS tCW tWP tBW tWRC tWR tBR tDS tDH tAXW tOHCL tOES tBWO tCP 70 0 45 45 45 15 15 15 20 0 — –5 0 20 15 Max 1000 — — — — — 1000 1000 — — 10 — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5 *6 *7 *1, *2 *2 *3 *3 *3 *4 *4 *4 Unit Notes *1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation. *2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or tBR). *3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last. *4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first. *5 : Applicable to any address change when CE1r stays Low. *6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. 45 MB84VP23481FK-70 • POWER DOWN PARAMETERS (32M Page mode FCRAM) Parameter CE2r Low Setup Time for Power Down Entry CE2r Low Hold Time after Power Down Entry CE1r High Hold Time following CE2r High after Power Down Exit [SLEEP mode only] CE1r High Hold Time following CE2r High after Power Down Exit [not in SLEEP mode] CE1r High Setup Time following CE2r High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when 4M, 8M, and 16M Partial mode is programmed. • OTHER TIMING PARAMETERS (32M Page mode FCRAM) Parameter CE1r High to OE Invalid Time for Standby Entry CE1r High to WE Invalid Time for Standby Entry CE1r High Hold Time following CE2r High after Power-up Input Transition Time Symbol tCHOX tCHWX tCHH tT Value Min 10 10 300 1 Max — — — 25 Unit ns ns µs ns *2 *1 Remarks Symbol tCSP tC2LP tCHH tCHHP tCHS Value Min 10 70 300 1 0 Max — — — — — Unit ns ns µs µs ns *1 *2 Remarks *1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. • AC TEST CONDITIONS (32M Page mode FCRAM) Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Test Setup — — — Between VIL and VIH Value VCCr VSS VCCr × 0.5 5 Unit V V V ns Remarks 46 MB84VP23481FK-70 • READ Timing #1 (Basic Timing) (32M Page FCRAM) tRC Address tASC tCE Address Valid tCHAH tASC CE1r tOE tCP tCHZ OE tOHZ tBA LB / UB tBLZ tOLZ tOH tBHZ DQ (Output) tCLZ Valid Data Output Note : CE2r and WE must be High for entire read cycle. 47 MB84VP23481FK-70 • READ Timing #2 (OE & Address Access) (32M Page FCRAM) tAx tRC tRC Address Address Valid tAA Address Valid tAA tOHAH CE1r Low tASO tOE OE LB / UB tOHZ tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2r and WE must be High for entire read cycle. 48 MB84VP23481FK-70 • READ Timing #3 (LB / UB Byte Access) (32M Page FCRAM) tAX Address tAA CE1r, OE tRC Address Valid tAx Low tBA tBA LB tBA UB tBHZ tBLZ DQ7 to DQ0 (Output) Valid Data Output DQ15 to DQ8 (Output) tOH tBHZ tBLZ tOH Valid Data Output tBLZ tBHZ tOH Valid Data Output Note : CE2r and WE must be High for entire read cycle. 49 MB84VP23481FK-70 • READ Timing #4 (Page Address Access after CE1r Control Access) (32M Page FCRAM) tRC Address (A20 to A3) tRC Address (A2 to A0) tASC CE1r tCE tCHZ Address Valid Address Valid tPRC Address Valid tPRC Address Valid tPRC Address Valid tPAA tPAA tPAA tCHAH OE LB / UB tCLZ DQ (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) tOH tOH tOH tOH Note : CE2r, and WE must be High for entire read cycle. 50 MB84VP23481FK-70 • READ Timing #5 (Random and Page Address Access) (32M Page FCRAM) tRC Address (A20 to A3) tRC Address (A2 to A0) Address Valid tAX tRC Address Valid tAx Address Valid tPRC Address Valid tRC Address Valid tPRC Address Valid tAA CE1r tPAA tAA tPAA Low tASO tOE OE tBA LB / UB tOLZ tBLZ tOH tOH tOH tOH DQ (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) Note : CE2r, and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low. 51 MB84VP23481FK-70 • WRITE Timing #1 (Basic Timing) (32M Page FCRAM) tWC Address tAS CE1r tAS WE tAS LB, UB tOHCL OE tDS DQ (Input) Valid Data Input tDH tBR tAS tWR tAS Address Valid tWRC tAS tCW tWP tBW Note : CE2r must be High for write cycle. 52 MB84VP23481FK-70 • WRITE Timing #2 (WE Control) (32M Page FCRAM) tWC Address Address Valid tWC Address Valid tOHAH CE1r Low tAS WE tWP tWR tAS tWP tWR LB, UB tOES OE tOHZ DQ (Input) Valid Data Input Valid Data Input tDS tDH tDS tDH Note : CE2r must be High for write cycle. 53 MB84VP23481FK-70 • WRITE Timing #3-1 (WE / LB / UB Byte Write Control) (32M Page FCRAM) tWC Address Address Valid tWC Address Valid CE1r Low tAS tWP tAS tWP WE tBR LB tBR UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH Note : CE2r must be High for write cycle. 54 MB84VP23481FK-70 • WRITE Timing #3-2 (WE / LB / UB Byte Write Control) (32M Page FCRAM) tWC Address Address Valid tWC Address Valid CE1r Low tWR tWR WE tAS LB tAS UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH tBW tBW Note : CE2r must be High for write cycle. 55 MB84VP23481FK-70 • WRITE Timing #3-3 (WE / LB / UB Byte Write Control) (32M Page FCRAM) tWC Address Address Valid tWC Address Valid CE1r Low WE tAS LB tAS UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH tBW tBR tBW tBR Note : CE2r must be High for write cycle. 56 MB84VP23481FK-70 • WRITE Timing #3-4 (WE / LB / UB Byte Write Control) (32M Page FCRAM) tWC Address Address Valid tWC Address Valid CE1r Low WE tAS LB tBWO tDS DQ7 to DQ0 (Input) tAS UB tDS DQ15 to DQ8 (Input) Valid Data Input Valid Data Input tBW tBR tAS tBW tBR tDH tDS Valid Data Input tDH tBW tBR tAS tBWO tBW tBR tDH tDS Valid Data Input tDH Note : CE2r must be High for write cycle. 57 MB84VP23481FK-70 • READ / WRITE Timing #1-1 (CE1r Control) (32M Page FCRAM) tWC Address tCHAH CE1r tCP tCP tAS WRITE Address tWRC tCW tASC tRC READ Address tCHAH tCE WE UB, LB tOHCL OE tCHZ tOH DQ READ Data Output WRITE Data Input tDS tDH tCLZ tOH Note : Write address is valid from either CE1r or WE of last falling edge. 58 MB84VP23481FK-70 • READ / WRITE Timing #1-2 (CE1r / WE / OE Control) (32M Page FCRAM) tWC Address tCHAH CE1r tCP tWP WE tCP tAS WRITE Address tWR tASC tRC READ Address tCHAH tCE UB, LB tOHCL OE tCHZ tOH DQ READ Data Output WRITE Data Input READ Data Output tDS tDH tOLZ tOH tOE Note : OE can be Low fixed in write operation under CE1r control RD-WR-RD operation. 59 MB84VP23481FK-70 • READ / WRITE Timing #2 (OE, WE Control) (32M Page FCRAM) tWC Address WRITE Address tRC READ Address tAA tOHAH CE1r Low tAS WE tOES tWP tWR tOHAH UB, LB tASO OE tOHZ tOH DQ READ Data Output WRITE Data Input tDS tDH tOLZ tOE tOHZ tOH READ Data Output Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE. 60 MB84VP23481FK-70 • READ / WRITE Timing #3 (OE, WE, LB, UB Control) (32M Page FCRAM) tWC Address WRITE Address tRC READ Address tAA tOHAH CE1r Low tOHAH WE tOES UB, LB tBHZ OE tBHZ tOH DQ READ Data Output WRITE Data Input READ Data Output tDS tDH tBLZ tOH tASO tAS tBW tBR tBA Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE. 61 MB84VP23481FK-70 • POWER-UP Timing (32M Page FCRAM) CE1r tCHH CE2r VCCr 0V VCCr Min Note : The tCHH specifies after VCCr reaches specified minimum level and applicable both CE1r and CE2r. • POWER DOWN Entry and Exit Timing CE1r tCHS CE2r tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP) Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset. • Standby Entry Timing after Read or Write (32M Page FCRAM) CE1r tCHOX OE tCHWX WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition. 62 MB84VP23481FK-70 • POWER DOWN PROGRAM Timing (32M Page FCRAM) tRC Address MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Key*2 tCP CE1r tCP tCP tCP tCP tCP*4 OE WE LB, UB DQ*3 RDa Cycle #1 RDa Cycle #2 RDa Cycle #3 00 Cycle #4 Key*3 Cycle #5 RDb Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. The address key must confirm the format specified in “s 32 M FCRAM CHARACTERISTICS for MCP 1. Power Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed. *2 : The data key must confirm the format specified in “s 32 M FCRAM CHARACTERISTICS for MCP 1. Power Down Program Timing (32 M Page FCRAM) ”. If not, the operation and data are not guaranteed. *3 : After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation. 63 MB84VP23481FK-70 s PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Condition VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Value Min     Typ 11.0 12.0 14.0 21.5 Max 14.0 16.0 16.0 26.0 Unit pF pF pF pF Note: Test conditions TA = + 25°C, f = 1.0 MHz s HANDLING OF PACKAGE Please handle this package carefully since the sides of package create acute angles. s CAUTION • The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. • Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group Protection” command. 64 MB84VP23481FK-70 s ORDERING INFORMATION MB84VP23481 FK -70 PBS Package Type PBS = 65-ball FBGA Speed Option Device Revision Device Number/Description 64Mega-bit (2M × 16-bit + 2M × 16-bit) Dual Operation Page Flash Memory 3.0V-only Read, Program, and Erase 32Mega-bit(2M × 16-bit) Mobile FCRAM 65 MB84VP23481FK-70 s PACKAGE DIMENSION 65-ball plastic FBGA (BGA-65P-M01) 9.00±0.10(.354±.004) 0.20(.008) S B (Seated height) +.006 .047 –.004 0.39±0.10 (Stand off) (.015±.004) 1.19 –0.10 +0.15 B 0.40(.016) REF 0.80(.031) REF 10 0.80(.031) REF A 9.00±0.10 (.354±.004) 0.40(.016) REF 0.10(.004) S KJHGFEDCBA INDEX BALL S 65-Ø0.45 –0.05 65-Ø.018 –.002 +0.10 +.004 9 8 7 6 5 4 3 2 1 INDEX-MARK AREA 0.20(.008) S A 0.08(.003) M SAB 0.10(.004) S C 2001 FUJITSU LIMITED B65001S-c-1-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 66 MB84VP23481FK-70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0311 © FUJITSU LIMITED Printed in Japan