MBM29F004BC-70PFTR

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20876-3E FLASH MEMORY CMOS 4 M (512 K × 8) BIT MBM29F004TC/004BC-70/-90 s DESCRIPTION The MBM29F004TC/BC is a 4 M-bit, 5.0 V-Only Flash memory organized as 512 K bytes of 8 bits each. The MBM29F004TC/BC is offered in a 32-pin TSOP (1) and 32-pin QFJ (PLCC) packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F004TC/BC offers access times between 70 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29F004TC/BC is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. (Continued) s PRODUCT LINE UP Part No. Ambient Temperature ( °C) Max Address Access Time (ns) VCC Supply Voltage Operation Erase/Program Voltage Consumption (mW) (Max) TTL Standby mode CMOS Standby mode Max CE Access (ns) Max OE Access (ns) 70 30 MBM29F004TC/BC -70 −20 to + 70 70 5.0 V ± 10% 193 275 5.5 0.0275 90 35 -90 −40 to + 85 90 MBM29F004TC/004BC-70/90 (Continued) The MBM29F004TC/BC is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. Any individual sector is typically erased and verified within 1.0 second (if already completely preprogrammed) . This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29F004TC/BC is erased when shipped from the factory. The MBM29F004TC/BC device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a non-busy sector. True background erase can thus be achieved. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ7, or by the Toggle Bit I feature on DQ6 output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29F004TC/BC memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. s PACKAGE 32-pin plastic TSOP (1) Marking Side 32-pin plastic TSOP (1) 32-pin plastic QFJ (PLCC) Marking Side (FPT-32P-M24) (FPT-32P-M25) (LCC-32P-M02) 2 MBM29F004TC/004BC-70/90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection • 32-pin TSOP (1) (Package Suffix : PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix : PD) • Minimum 100,000 write/erase cycles • High performance 70 ns maximum access time • Flexible sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and seven 64 K bytes sectors Any combination of sectors can be erased. Also supports full chip erase. • Embedded Erase™* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded Program™* Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Low VCC write inhibit ≤ 3.2 V • Erase Suspend/Resume Supports reading or programming data to a sector not being erased • Sector Protection Hardware sector protect that disables any combination of sectors from write or erase operations • Temporary Sector Unprotection Temporary sector unprotection via the command sequence • Boot Code Sector Architecture • Fast Programming • Extended Sector Protection *: Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc. 3 MBM29F004TC/004BC-70/90 s PIN ASSIGNMENTS TSOP (1) A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Marking Side) Normal Bend 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 (FPT-32P-M24) A4 A5 A6 A7 A12 A15 A16 A18 VCC WE A17 A14 A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 CE A10 OE (FPT-32P-M25) (Continued) 4 MBM29F004TC/004BC-70/90 (Continued) PLCC (TOP VIEW) VCC WE 31 A12 A15 A16 A18 A17 30 29 28 27 26 25 24 23 22 21 14 DQ1 15 DQ2 16 VSS 17 DQ3 18 DQ4 19 DQ5 20 DQ6 A14 A13 A8 A9 A11 OE A10 CE DQ7 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 3 2 1 32 (LCC-32P-M02) s PIN DESCRIPTION Table 1 Pin A18 to A0 DQ7 to DQ0 CE OE WE VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable/Sector Protection Unlock Device Ground Device Power Supply (5.0 V±10%) MBM29F004TC/BC Pin Configuration Function 5 MBM29F004TC/004BC-70/90 s BLOCK DIAGRAM VCC VSS Erase Voltage Generator DQ7 to DQ0 Input/Output Buffers State Control WE Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch STB Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase Address X-Decoder Latch 4,194,304 Cell Matrix A18 to A0 s LOGIC SYMBOL 19 A18 to A0 DQ7 to DQ0 CE OE WE 8 6 MBM29F004TC/004BC-70/90 s DEVICE BUS OPERATION Table 2 MBM29F004TC/BC User Bus Operations Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*2 Standby Output Disable Write (Program/Erase) Enable Sector Protection*3 3-Byte Sector Unlock Sequence 2-Byte Sector Relock Sequence Command Mode Sector Protect*2 Verify Sector Protect*2, *5 Hardware Sector Protect* 2 CE L L L H L L L L L L L H L L OE L L L X H H VID VID VID VID L VID L VID WE H H H X H L A0 L H A0 X X A0 X A0 A0 A0 A1 L L A1 X X A1 X A1 A1 A1 A1 X H A1 A6 L L A6 X X A6 X A6 A6 A6 A6 L L A6 A9 VID VID A9 X X A9 VID A9 A9 A9 A9 VID VID A9 I/O Code Code DOUT High-Z High-Z DIN X DIN DIN DIN Code X Code DIN H L H A0 X L A0 Verify Sector Protection* * 2, 6 Temporary Sector Unprotection*3 Legend : L = VIL, H = VIH, X = “H” or “L”, = Pulse Input. See DC Characteristics for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 6. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Refer to the section on Sector Protection. *4 : To activate the command, OE has to be taken to VID. *5 : In case of Command Mode Sector Protect. *6 : In case of Hardware Sector Protect. 7 MBM29F004TC/004BC-70/90 Table 3 Command Sequence *1, *2, *3 Read/Reset *1 Read/Reset Byte *1 Auto-Select Manufacture Code Auto-Select Device Code Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Set to Fast Mode Temporary Sector Unprotection Mode *2 Reset from fast Mode *8 Sector Unlock *9 Fast Programming *3 Sector Relock *2 Sector Protection Set Function by Extended Sector Protection Command *2 Extended sector Protection 3 3 2 3 2 2 MBM29F004TC/BC Command Definitions Second Fourth Bus Bus First Bus Third Bus Fifth Bus Sixth Bus Bus Read/Write Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 3 4 6 6 XXXh F0h 555h 555h 555h 555h 555h 555h   55h 55h 55h 55h 55h 55h  555h 555h 555h  F0h F0h 90h  RA 00h 01h PA  RD 04h ID PD                555h SA      10h 30h AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh 555h A0h 555h 555h 80h 80h 555h AAh 2AAh 55h 555h AAh 2AAh 55h Erase can be suspended during sector erase with Addr (“H” or “L”) , Data (B0h) Erase can be resumed after suspend with Addr (“H” or “L”) , Data (30h) 555h 555h AAh 2AAh AAh 2AAh 55h 55h 555h 555h  555h   20h 20h  24h                                       XXXh 90h XXXh 00h 555h AAh 2AAh PA 55h PD F0h or 00h XXXh A0h XXXh 90h XXXh 3 555h AAh 2AAh 55h 555h 24h       3 XXXh 60h SPA 60h SPA 40h SPA SD     *1: Either of the two reset commands will reset the device to read mode. *2: To activate the command, OE has to be taken to VID. *3: Valid only during Temporary Sector Unprotection mode. *4: Valid only during Extended Sector Protection Set-up Mode. (Continued) 8 MBM29F004TC/004BC-70/90 (Continued) Notes : • Address bits X = “H” or “L” for all address commands except for Program Address (PA) and Sector Address (SA) . • Bus operations are defined in Table 2. • RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, and A13 will uniquely select any sector. • RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse. ID = Device Code. (See Table 4 Autoselect Codes. ) • SPA = Sector Protection Address. Sector Address (SA) and (A6, A1, A0) = (0, 1, 0) to be set. SD = Data to verify the Sector Protection. The output at protected Sector = 01h and the output at unprotected Sector = 00h. • Command combinations not described in “MBM29F004TC/BC Command Definitions Table” are illegal. Table 4.1 MBM29F004TC/BC Sector Protection Verify Autoselect Codes Type Manufacture’s Code Device Code MBM29F004TC MBM29F004BC A18 to A13 X X X Sector Addresses A6 VIL VIL VIL VIL A1 VIL VIL VIL VIH A0 VIL VIH VIH VIL Code (HEX) 04h 77h 7Bh 01h* Sector Protection * : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. Table 4.2 Type Manufacturer’s Code Device MBM29F004TC Code MBM29F004BC Sector Protection Code 04h 77h 7Bh 01h DQ7 0 0 0 0 Expanded Autoselect Code Table DQ6 0 1 1 0 DQ5 0 1 1 0 DQ4 0 1 1 0 DQ3 0 0 1 0 DQ2 1 1 0 0 DQ1 0 1 1 0 DQ0 0 1 1 1 9 MBM29F004TC/004BC-70/90 s FLEXIBLE SECTOR-ERASE ARCHITECTURE • One 16 K byte, two 8 K bytes, one 32 K byte, and seven 64 K bytes sectors. • Individual-sector, multiple-sector, or bulk-erase capability. • Individual or multiple-sector protection is user definable. Table 5 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A18 0 0 0 0 1 1 1 1 1 1 1 A17 0 0 1 1 0 0 1 1 1 1 1 Sector Address Tables (MBM29F004TC) A16 0 1 0 1 0 1 0 1 1 1 1 A15 X X X X X X X 0 1 1 1 A14 X X X X X X X X 0 0 1 A13 X X X X X X X X 0 1 X Address Range 00000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 77FFFh 78000h to 79FFFh 7A000h to 7BFFFh 7C000h to 7FFFFh Table 6 Sector Address Tables (MBM29F004BC) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A18 0 0 0 0 0 0 0 1 1 1 1 A17 0 0 0 0 0 1 1 0 0 1 1 A16 0 0 0 0 1 0 1 0 1 0 1 A15 0 0 0 1 X X X X X X X A14 0 1 1 X X X X X X X X A13 X 0 1 X X X X X 0 1 X Address Range 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 10 MBM29F004TC/004BC-70/90 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Sector Size 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 32 K bytes 8 K bytes 8 K bytes 16 K bytes (×8) Address Range 00000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 77FFFh 78000h to 79FFFh 7A000h to 7BFFFh 7C000h to 7FFFFh MBM29F004TC Top Boot Sector Architecture Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Sector Size 16 K bytes 8 K bytes 8 K bytes 32 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes 64 K bytes (×8) Address Range 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh MBM29F004BC Bottom Boot Sector Architecture 11 MBM29F004TC/004BC-70/90 s FUNCTIONAL DESCRIPTION Read Mode The MBM29F004TC/BC has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time) . Standby Mode When using CE pin, a CMOS standby mode is achieved with CE input held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE pin held at VIH. Under this condition the current is reduced to approximately 1 mA. During Embedded Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard access time (tCE) from either of these standby modes. In this mode, all outputs pins are placed in the high impedance state. Output Disable With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6. (See Table 4.1 and 4.2.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29F004TC/BC is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3. (Refer to Autoselect Command section.) Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and byte 1 (A0 = VIH) represents the device identifier code for MBM29F004TC = 77h, MBM29F004BC = 7Bh. These two bytes are given in the tables 4.1 and 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See Tables 4.1 and 4.2.) The Autoselect mode also facilitates the determination of sector group protection in the system. By performing a read operation at the address location XX02h with the higher order address bit A13, A14, A15, A16, A17 and A18 set to the desired sector address, the device will return 01h for a protected sector group and 00h for a nonprotected sector. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. 12 MBM29F004TC/004BC-70/90 Sector Group Protection The MBM29F004TC/BC features hardware sector group protection. These features will disable both program and erase operations in any combination of sectors (0 through 10) . The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector group unprotected. To activate command mode sector group protection, the programming groups equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12 V) , CE = VIL, A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, and A13) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the eleven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 12 and 20 for sector protection waveforms and algorithm. To verify programming of the command mode sector protection circuitry, the programming equipment must force VID on address A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, and A13) while (A6, A5, A1, A0) = (0, 1, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A5, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. The alternate hardware sector protect mode intended only for the programming equipment required force VID on address pin A9 and control pin OE, (suggest VID = 12 V) , CE = VIL. The sector addresses (A18, A17, A16, A15, A14, and A13) should be set to the sector to be protected. Tables 4 and 5 define the sector address for each of the eleven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 15 and 23 for sector protection waveforms and algorithm. To verify programming of the hardware sector protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, and A13) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, and A13) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See Tables 3.1 and 3.2 for Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotect of previously protected sector of the MBM29F004TC/BC device in order to change data. The Temporary Sector Unprotection mode is activated by setting the OE pin to high voltage (12 V) . While OE is at VID, the sector unlock sequence is written to the device. After the sector unlock sequence is written, the OE pin is taken back to VIH. The device is now in the Temporary Sector Unprotection mode. While in this mode, formerly protected sectors can be programmed or erased by selecting the appropriate sector addresses during programming or erase operations. Either sector erase or chip erase operations can be performed in this mode. Exiting the Temporary Sector unprotection mode is accomplished by either removing VCC from the device or by taking OE back to VID and writing the sector relock sequence. After writing the sector relock sequence, the OE pin is taken back to VIH and all previously protected sectors will be protected again. The Temporary Sector Unprotection Status can be used to check whether this mode is in operation or not. The Temporary Sector Unprotection Status can be executed by setting AO = AI = VIH (A6 = VIL) during Autoselect mode. 13 MBM29F004TC/004BC-70/90 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/ Reset Commands are functionally equivalent, resetting the device to the read mode. Read/Reset Command The read or reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory at the Read/Reset operation. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect Command sequence into the command register. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h returns the device code (MBM29F004TC = 77h, MBM29F004BC = 7Bh) . (See Tables 4.1 and 4.2) All manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Sector state (protect or unprotect) will be informed by address XX02h. Scanning the sector addresses (A18, A17, A16, A15, A14, and A13) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence. Byte Programming The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 6, Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. 14 MBM29F004TC/004BC-70/90 Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Reset/Read mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. Figure 16 illustrates the Embedded ProgrammingTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section) at which time the device returns to read the mode. Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE (whichever happens first) , while the command (Data = 30h) is latched on the rising edge of CE or WE (whichever happens first) . After time-out of 50 µs from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command (30h) to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last CE or WE will initiate the execution of the Sector Erase command (s) . If another falling edge of the CE or WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, Write Operation Status section for DQ3, Sector Erase Timer operation.) Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 6) . Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 µs time out from the rising edge of the CE or WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable only during a Sector Erase operation which includes the time-out period for sector erase and will be ignored during Chip Erase or Programming 15 MBM29F004TC/004BC-70/90 operations. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended program operation is detected by the Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Byte Program operation. Note that DQ7 must be read from the Byte Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode MBM29F004TC/BC has Fast Mode function. This feature allows the system to program the device faster than using the standard program command sequence. The fast mode command sequence is initiated by setting the OE pin to VID and writing two unlock cycles. This is followed by a third write cycle containing the fast mode command, 20h. The device then enters the fast mode. Previously protected sectors of the device are now temporarily unprotected. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standerd program command sequence, resulting in faster total programming time. Tables 6 and 7 show the requirements for the command sequence. During the unlock bypass mode, only the Fast Program and Reset from Fast Mode commands are valid. To exit the fast mode, the system must issue the two-cycle unlock bypass reset command sequence with OE at VID. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. (Refer to the Figure 24 Extended algorithm.) (2) Fast Programming During Temporary Sector Unprotection Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . Sector Relock To relock Temporary Sector Unprotection or Extended Sector Protection, OE pin should be forced to V2H after Relock Sector command sequence with OE pin, that is forced VID. 16 MBM29F004TC/004BC-70/90 Extended Sector Protection Set-up This function operation is for the execution of Extended Sector Protection. This mode is excuted by forcing VIH on OE pin after a command sequences with OE pin, that is forced VID. Extended Sector Protection/Extended Sector Protection Set-up In this mode, the operation is initiated by writing the set-up command (60h) into the command register after Extended Sector Protection Set-up command. Then, the sector addresses pin (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins) , and write Extended Sector Protection Command (60h) . A sector is typically protected in 100 µs. To verify programming of the protection circuitry, the sector addresses pins (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write Extended Sector Protection command (60h) again. To terminate the operation it is necessary relock the sector. This command is the same function as the Sector Protection. Write Operation Status Detailed in Table 8 are all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows the user to determine which sectors are erasing and which are not. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Table 6 Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspend(Non-Erase Suspended Sector) ed Mode Hardware Sequence Flags DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle*1 Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle Toggle Data 1*2 1 N/A N/A In Progress *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes : • DQ0 and DQ1 are reserve pins for future use. • DQ4 is Fujitsu internal use only. 17 MBM29F004TC/004BC-70/90 DQ7 Data Polling The MBM29F004TC/BC device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. The Data polling is valid after the rising edge of the forth write pulse sequence. During the Embedded EraseTM Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 18. Data Polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase Suspend Mode. During Program in Erase Suspend, Data Polling will perform the same as in regular program execution outside of the suspend mode. For Chip Erase and Sector Erase, the Data Polling is valid after the rising edge of the sixth WE pluse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being programmed or erased. Otherwise, the status may not be valid and Data Polling at a protected sector may not be correctly performed. In this case, the Toggle Bit I will be recommended. Just prior to the completion of Embedded Algorithm operation, MBM29F004TC/BC data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, or sector erase time-out. See Figure 9 for the Data Polling timing specifications and waveforms. DQ6 Toggle Bit I The MBM29F004TC/TB also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase and Sector Erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. The Toggle Bit I is active during the Sector Erase time out. In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 µs and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 100 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagrams. 18 MBM29F004TC/004BC-70/90 DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce a “1”. This is a failure condition which indicaters that the program or erase cycle was not successfully completed. Data Polling DQ7, DQ6 is only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in Table 2. The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1”. Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. DQ3 Sector Erase Timer After the completion of the initial Sector Erase command sequence, the Sector Erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit I are valid after the initial Sector Erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the Sector Erase timer window is still open. If DQ3 is high (“1”) , the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”) the device will accept additional Sector Erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 6 : Hardware Sequence Flags. DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded EraseTM Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded EraseTM Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while DQ6 does not) . See also Table 6 and Figure 14. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from the erasing sector. Table 9 Toggle Bit Status Mode Program Erase Erase-Suspend Read* (Erase-Suspended Sector) Erase-Suspend Program 1 DQ7 DQ7 0 1 DQ7*2 DQ6 Toggles Toggles 1 Toggles DQ2 1 Toggles Toggles 1*2 *1 : These status flags apply when outputs are read from a sector that has been erase-suspended. *2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector. 19 MBM29F004TC/004BC-70/90 Data Protection The MBM29F004TC/BC is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completions of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 3.2 V (typically 3.7 V) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V. The Embedded Program Algorithm will be stopped under the VCC level is less than VLKO. The Embedded Program Algorithm will not be restart even if the VCC level satisfy the recommended VCC supply voltage again. Then, if the Embedded Program Algorithm is stopped during the program ro erase operation is in progress, the address data is not correct and the programming or erase command should be written again. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Sector Unprotection MBM29F004TC/BC features hardware Sector Protection at user’s side. This feature will disable both program and erase operations in protected sectors. The programming and erase command to the protected sector will be ignored. 20 MBM29F004TC/004BC-70/90 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins except A9 and OE*1, *2 VCC*1, *2 A9 and OE*1, *3 *1 : Voltage : GND = 0 V *2 : Minimum DC voltage on input and l/O pins are −0.5 V. During voltage transitions, inputs may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins are VCC + 0.5 V. During voltage transitions, inputs may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9 and OE pins are −0.5 V. During voltage transitions, A9, OE pins are + 13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and power supply. (VIN − VCC) do not exceed 9 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol Tstg TA VIN, VOUT VCC VIN Rating Min −55 −40 −2.0 −2.0 −2.0 Max +125 +85 +7.0 +7.0 +13.5 Unit °C °C V V V s RECOMMENDED OPERATING RANGES Parameter Ambient Temperature VCC Supply Voltage Symbol TA VCC GND Part No. MBM29F004TC/BC-70 MBM29F004TC/BC-90 MBM29F004TC/BC-70/-90 Value Min −20 −40 +4.5 Typ   5.0 0 Max +70 +85 +5.5 Unit °C °C V Note : Operating ranges define those limits between which the proper device function is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 21 MBM29F004TC/004BC-70/90 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.8 V −0.5 V −2.0 V 20 ns 20 ns 20 ns Figure 1 Maximum Undershoot Waveform VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 +13.5 V +13.0 V VCC + 0.5 V 20 ns 20 ns 20 ns Note : This waveform is applied for A9 and OE. Figure 3 Maximum Overshoot Waveform 2 22 MBM29F004TC/004BC-70/90 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current A9, OE Inputs Leakage Current VCC Active Current* 1 Symbol ILI ILO ILIT ICC1 ICC2 ICC3 VIL VIH VID VOL VOH1 VOH2 VLKO Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE = 12.5 V CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max, CE = VIH VCC = VCC Max, CE = VCC ± 0.3 V    IOL = 5.8 mA, VCC = VCC Min IOH = −2.5 mA, VCC = VCC Min IOH = −100 µA  Value Min −1.0 −1.0      −0.5 2.0 11.5  2.4 VCC − 0.4 3.2 Typ       1   12    3.7 Max + 1.0 + 1.0 + 50 35 50 1 5 0.8 VCC + 0.5 12.5 0.45   4.2 Unit µA µA µA mA mA mA µA V V V V V V V VCC Active Current*2 VCC Current (Standby) Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE) *3, *4 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage *1 : The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz) . The frequency component typically is 2 mA/MHz, with OE at VIH. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Applicable to sector protection function. *4 : (VID − VCC) do not exceed 9.0 V. 23 MBM29F004TC/004BC-70/90 s AC CHARACTERISTICS • Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time from Address, CE or OE, Whichever Occurs First Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tCE tOE tDF tDF tOH  CE = VIL OE = VIL OE = VIL     Value (Note) Test Setup 70      0 -70 Min Max  70 70 30 20 20  90      0 -90 Min Max  90 90 35 20 20  ns ns ns ns ns ns ns Unit Note : Test Conditions : Output Load : 1 TTL gate and 100 pF Input rise and fall times : 5 ns Input pulse levels : 0.45 V or 2.4 V Timing measurement reference level Input : 0.8 V and 2.0 V Output : 0.8 V and 2.0 V 5.0 V IN3064 or Equivalent Device Under Test 6.2 kΩ CL Diodes = IN3064 or Equivalent 2.7 kΩ Note : CL = 100 pF including jig capacitance Figure 4 Test Conditions 24 MBM29F004TC/004BC-70/90 • Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Read Hold Time Toggle Bit I and Data Polling Read Recover Time before Write Read Recover Time before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Byte Programming Operation Sector Erase Operation *1 VCC Setup Time Voltage Transition Time *2 Write Pulse Width *2 OE Setup Time to WE Active * CE Setup Time to WE Active * VID Rise and Fall Time Delay Time from Embedded Output Enable 2 2 Symbol JEDEC Standard Value (Note) -70 Min 70 0 45 30 0 0 0 10 0 0 0 0 0 0 35 35 20 20    50 4 100 4 4 500 30 Typ                   8 1         Max                     8        Min 90 0 45 45 0 0 0 10 0 0 0 0 0 0 45 45 20 20    50 4 100 4 4 500 35 -90 Typ                   8 1         Max                     8        ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs s s µs µs µs µs µs ns ns Unit tAVAV tAVWL tWLAX tDVWH tWHDX   tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2        tWC tAS tAH tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tWPP tOESP tCSP tVIDR tEOE *1: This does not include the preprogramming time. *2: This timing is only for Sector Protection operation. 25 MBM29F004TC/004BC-70/90 s ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Byte Programming Time Chip Programming Time Program/Erase Cycle Limits Min    100,000 Typ 1 8 4.2  Max 8 150 10  Unit s µs s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead  s PIN CAPACITANCE 1.TSOP (1) Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Value Typ 7 8 8.5 Max 8 10 10 Unit pF pF pF Note : Test conditions TA = 25 °C, f = 1.0 MHz 2.QFJ Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Value Typ 7 8 8.5 Max 8 10 10 Unit pF pF pF Note : Test conditions TA = 25 °C, f = 1.0 MHz 26 MBM29F004TC/004BC-70/90 s TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L": Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Change from H to L Will Be Change from L to H Changing, State Unknown Center Line is HighImpedance "Off" State tRC A18 to A0 tACC Address Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z DQ7 to DQ0 Output Valid Figure 5.1 AC Waveforms for Read Operation 27 MBM29F004TC/004BC-70/90 tRC A18 to A0 tACC Address Stable tOH DQ7 to DQ0 High-Z Output Valid Figure 5.2 AC Waveforms for Read Operation 28 MBM29F004TC/004BC-70/90 3rd Bus Cycle Data Polling PA tAS tAH PA tRC A18 to A0 555h tWC CE tCS tCH tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS tOH tDH PD DQ7 DOUT DOUT Data A0h Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. Figure 6 AC Waveforms for Alternate WE Controlled Program Operation 29 MBM29F004TC/004BC-70/90 3rd Bus Cycle Data Polling PA tAS tAH PA A18 to A0 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data A0h PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • This command requires Sector Protection Set-up. Figure 7 AC Waveforms for Alternate CE Controlled Program Operation 30 MBM29F004TC/004BC-70/90 A18 to A0 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 30h for Sector Erase 10h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Figure 8 AC Waveforms for Chip/Sector Erase Operation 31 MBM29F004TC/004BC-70/90 CE tCH tOE tDF OE tOEH WE tCE * DQ2 = Valid Data DQ7 Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE Output Valid High-Z RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation) . Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operation 32 MBM29F004TC/004BC-70/90 CE tOEH WE tOES OE DQ6 Data DQ6=Toggle DQ6=Toggle tOE DQ6= StopToggle Output Valid Note : DQ6 : Stop toggling (The device completes the automatic operation.) Figure 10 AC Waveforms for Toggle Bit 33 MBM29F004TC/004BC-70/90 A18, A17, A16, A15, A14, A13 A0 SAx SAy A1 A6 VID 5V A9 VID 5V OE tVLHT tOESP tWPP tVLHT tVLHT tVLHT WE tCSP CE Data tVCS 01h tOE VCC SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected Note : A-1 is VIL on byte mode. Figure 11 AC Waveforms Sector Protection 34 MBM29F004TC/004BC-70/90 VID VIH VSS tVIDR OE Address 555h 2AAh 555h Data AAh 55h 24h CE WE Temporary Sector Unprotect mode disabled. Read/reset mode enabled. Temporary Sector Unprotect Mode Enabled or Command Mode Sector Protect Enabled Notes : • To enable Temporary Sector Unprotection Mode, write 20h in data; to enable Command Mode Sector Protect, write 24h in data. • To enable Temporary Sector Unprotection Mode, OE must be at VIH; to enter Command Mode Sector Protect, OE must be held at VID. Figure 11 3-Byte Sector Unlock Sequence Timing Diagram VID VIH VSS tVIDR OE Address XXXh XXXh Data 90h F0h or 00h CE WE Temporary Sector Unprotect Mode Enabled Temporary Sector Unprotect mode disabled. Read/reset mode enabled. Figure 12 2-Byte Sector Relock Sequence Timing Diagram 35 MBM29F004TC/004BC-70/90 Time-out: 100 µs for PROGRAM VID VIH VSS OE tVIDR tVLHT Valid Valid Address Valid Sector Data 60h 60h 40h Valid CE WE 3-Byte Sector Unlock Sequence 2-Byte Sector Relock Sequence Notes : • To enable the Command Mode Sector Protect, write 24h in data in 3-Byte Unlock Sequence. • For sector protect, A6 = 0, A5 = 1, A1 = 1, A0 = 0. Figure 13 AC Waveforms for Command Mode Sector Protect Timing Diagram 36 MBM29F004TC/004BC-70/90 VCC VID 5V tVCS tVIDR OE A18 to A0 555h 2AAh 555h CE WE tVLHT D7 to D0 AAh 55h 20h/24h Note : To execute Temporary Sector Unprotection mode, 20h should be written. To execute Extended Sector Protection mode, 24h should be written. Figure 12 AC Waveforms for Temporary Sector Unprotection/Extended Sector-Protection set-up 37 MBM29F004TC/004BC-70/90 OE VID 5V tVLHT Add xxxh SAx SAx SAy A0 A1 A6 CE TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out Window = 100 µs (Min) Note : This command requires Sector Protection Set-up Figure 13 AC Waveforms for Extended Sector Protection 38 MBM29F004TC/004BC-70/90 Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 with OE Note : DQ2 is read from the erase-suspended sector. Figure 14 DQ2 vs. DQ6 tVIDR VID OE 5V A18 to A0 xxxh xxxh CE WE tVLHT D7 to D0 90h F0h or 00h Note : This command is to complete Temporary Sector Unprotection mode or Extended Sector Protection. Figure 15 AC Waveforms for Sector Relock 39 MBM29F004TC/004BC-70/90 s FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Embedded Program Algorithm in progress No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Figure 16 Embedded ProgramTM Algorithm 40 MBM29F004TC/004BC-70/90 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h 555h/10h Additional sector erase commands are optional. Figure 17 Embedded EraseTM Algorithm 41 MBM29F004TC/004BC-70/90 Start Read Byte (DQ7 to DQ0) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Note: VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector group addresses within the sector not being protected during sector erase or multiple sector erases operation. Figure 18 Data Polling Algorithm 42 MBM29F004TC/004BC-70/90 Start Read DQ7 to DQ0 Addr. = "H" or "L" *1 Read DQ7 to DQ0 Addr. = "H" or "L" DQ6 = Toggle? Yes No DQ5 = 1? Yes No *1, 2 Read DQ7 to DQ0 Addr. = "H" or "L" Read DQ7 to DQ0 Addr. = "H" or "L" DQ6 = Toggle? Yes Program/Erase Operation Not Complete.Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Figure 19 Toggle Bit Algorithm 43 MBM29F004TC/004BC-70/90 Start Setup Sector Group Addr. (A18, A17,A16, A15, A14, A13) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = CE = VIL Activate WE Pulse PLSCNT = PLSCNT + 1 Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group 1= ( Addr.A=, SA,=AVIL VIH, )* 6 A0 No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group? No Fail Remove VID from A9 Write Reset Command Yes Sector Group Protection Completed Figure 20 Sector Group Protection Algorithm 44 MBM29F004TC/004BC-70/90 Start OE = VID Temporary Sector Unprotect Command Sequence Write OE = VIH *1 Perform Erase or Program Operations OE = VID Temporary Sector Unprotect Command Sequence Write OE = VIH Temporary Sector *2 Unprotection Completed Temporary Sector Unprotect Command Sequence (Address/Command) 555h/AAh Temporary Sector Unprotect Relock Command Sequence (Address/Command) ×××h/90h 2AAh/55h ×××h/F0h or 00h 555h/20h *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. Figure 21 Temporary Sector Unprotection Algorithm 45 MBM29F004TC/004BC-70/90 Start OE = VID Wait to 4 µs Extended Sector Protection Set up Command Sequence Write OE = VIH Device is Operating in Temporary Sector Unprotection Mode NO Extended Sector Protection Setup Command (Address/Command) 555h/AAh 2AAh/55h Extended Sector Protection Entry? YES Setup Sector Protection write ×××h/60h PLSCNT = 1 Protect Sector write SPA/60h Addr = SA, A1 = VIL, A1 = VIH, A6 = VIL OE = VIL Verify Sector Protection write 40h to Sector Address SPA/40h A1 = VIH, Addr = SA, A6, A0 = VIL 555h/24h ( PLSCNT = PLSCNT + 1 ) ( ) OE =VIL Read from Sector Address A1 = VIH, Addr = SA, A6, A0 = VIL ( ) NO PLSCNT = 25? YES OE = VID Write Temporary Sector Unprotection Unprotection Command Sequence OE = VIH NO Data = 01h ? YES Protect Other Sector ? NO OE = VID Write Temporary Sector Unprotection Unprotection Command Sequence OE = VIH Sector Protection Completed YES Setup Next Sector Address Temporary Sector Unprotection Relock Command (Address/Command) ×××h/90h Fail ×××h/F0h or 00h Figure 22 46 Extended Sector Protection Algorithm MBM29F004TC/004BC-70/90 FAST MODE ALGORITHM Start OE = VID 555h/AAh 2AAh/55h Set Fast Mode 555h/20h OE = VIH XXXh/A0h Program Address/Program Data Data Polling Device In Fast Program Verify Byte? Yes Increment Address No Last Address? Yes Programming Completed No OE = VID XXXXh/90h Reset Fast Mode XXXXh/00h OE = VIH Fast Program Completed Figure 24 Embedded ProgramTM Algorithm for Fast Mode 47 MBM29F004TC/004BC-70/90 s ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of : MBM29F004 TC -90 PD PACKAGE TYPE PD = 32-Pin Rectangular Plastic Leaded Chip Carrier (PLCC) PFTN = 32-Pin Thin Small Outline Package (TSOP) Normal Bend PFTR = 32-Pin Thin Small Outline Package (TSOP) Reverse Bend SPEED OPTION See Product Selector Guide BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29F004 4 Mega-bit (512 K × 8-Bit) CMOS Flash Memory 5.0 V Read, Write, and Erase Valid Combinations MBM29F004TC-70 MBM29F004TC-90 MBM29F004BC-70 MBM29F004BC-90 PFTN PFTR PD Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. 48 MBM29F004TC/004BC-70/90 Part No. MBM29F004TC-70PFTN MBM29F004TC-90PFTN MBM29F004TC-70PFTR MBM29F004TC-90PFTR MBM29F004TC-70PD MBM29F004TC-90PD MBM29F004BC-70PFTN MBM29F004BC-90PFTN MBM29F004BC-70PFTR MBM29F004BC-90PFTR MBM29F004BC-70PD MBM29F004BC-90PD Package 32-pin plastic TSOP (1) (FPT-32P-M24) (Normal Bend) 32-pin plastic TSOP (1) (FPT-32P-M25) (Reverse Bend) 32-pin plastic QFJ (PLCC) (LCC-32P-M02) 32-pin plastic TSOP (1) (FPT-32P-M24) (Normal Bend) 32-pin plastic TSOP (1) (FPT-32P-M25) (Reverse Bend) 32-pin plastic QFJ (PLCC) (LCC-32P-M02) Access (ns) 70 90 70 90 70 90 70 90 70 90 70 90 Bottom Sector Top Sector 49 MBM29F004TC/004BC-70/90 s PACKAGE DIMENSIONS 32-pin plastic TSOP (1) (FPT-32P-M24) Note 1) * : Resn protrusion. (Each side : +0.15 (.006) Max). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. Details of "A" part LEAD No. 1 32 0.25(.010) INDEX 0~8˚ 0.60±0.15 (.024±.006) 16 17 0.17 –0.08 .007 –.003 +0.03 +.001 20.00±0.20 (.787±.008) *18.40±0.20 (.724±.008) 0.50(.020) *8.00±0.20 (.315±.008) 0.10±0.05(.004±.002) (Stand off) 1.10 –0.05 .043 –.002 (Mounting height) +0.10 +.004 "A" 0.10(.004) 0.22±0.05 (.009±.002) 0.10(.004) M C 2002 FUJITSU LIMITED F32035S-c-4-4 Dimensions in mm (inches) (Continued) 50 MBM29F004TC/004BC-70/90 (Continued) 32-pin plastic TSOP (1) (FPT-32P-M25) LEAD No. 1 Note 1) * : Resn protrusion. (Each side : +0.15 (.006) Max). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 32 Details of "A" part 0.60±0.15 (.024±.006) INDEX 0~8˚ 0.25(.010) 16 17 0.22±0.05 (.009±.002) 0.17 –0.08 .007 –.003 +0.03 +.001 0.10(.004) M 0.10(.004) 0.50(.020) 0.10±0.05(.004±.002) (Stand off) "A" *18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) *8.00±0.20 (.315±.008) 1.10 –0.05 .043 –.002 (Mounting height) +0.10 +.004 C 2002 FUJITSU LIMITED F32036S-c-4-5 Dimensions in mm (inches) (Continued) 51 MBM29F004TC/004BC-70/90 (Continued) 32-pin plastic QFJ (PLCC) (LCC-32P-M02) 12.37±0.13 (.487±.005) 11.43±0.08 (.450±.003) 4 1 32 30 3.40±0.16 (.134±.006) 2.25±0.38 (.089±.015) 0.64(.025) MIN 7.62(.300)REF 1.27±0.13 (.050±.005) 5 29 INDEX 13.97±0.08 14.94±0.13 (.550±.003) (.588±.005) 12.95±0.51 (.510±.020) 10.16(.400) REF 13 21 14 20 R0.95(.037) TYP 0.66(.026) TYP 0.20 –0.02 .008 –.001 0.43(.017) TYP 10.41±0.51 (.410±.020) +0.05 +.002 0.10(.004) No : LEAD No. C 1994 FUJITSU LIMITED C32021S-2C-4 Dimensions in mm (inches) 52 MBM29F004TC/004BC-70/90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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