MBM29F160TE70

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20879-6E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29F160TE70/90 MBM29F160BE70/90 s DESCRIPTION The MBM29F160TE/BE is a 16M-bit, 5.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29F160TE/BE is offered in a 48-pin TSOP (1) package. The device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F160TE/BE offers access times of 55 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The MBM29F160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. s PRODUCT LINE UP Part No. Power Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) 70 70 30 MBM29F160TE/BE 70 VCC = 5.0 V ± 10 % 90 90 40 90 s PACKAGES 48-pin plastic TSOP (1) Marking Side Marking Side (FPT-48P-M19) (FPT-48P-M20) MBM29F160TE70/90/MBM29F160BE70/90 (Continued) The MBM29F160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded ProgramTM* Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29F160TE/BE is erased when shipped from the factory. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. The MBM29F160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29F160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29F160TE70/90/MBM29F160BE70/90 s FEATURES • 0.23 µm Process Technology • Single 5.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (1) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type) • Minimum 100,000 program/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Low VCC write inhibit ≤ 4.2 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Hardware RESET pin Resets internal state machine to the read mode • Sector protection Hardware method disables any combination of sectors from program or erase operations • Temporary sector unprotection Temporary sector unprotection via the RESET pin • In accordance with CFI (Common Flash Memory Interface) • WP Input pin (Hardware Protect) At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At open, allows removal of boot sector protection (MBM29F160TE/BE) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29F160TE70/90/MBM29F160BE70/90 s PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 Normal Bend (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M20) 4 MBM29F160TE70/90/MBM29F160BE70/90 s PIN DESCRIPTIONS Pin name A19 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/ Temporary Sector Unprotection Selects 8-bit or 16-bit mode Hardware Write Protection Pin Not Connected Internally Device Ground Device Power Supply Function s LOGIC SYMBOL A-1 20 A19 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP RY/BY 16 or 8 5 MBM29F160TE70/90/MBM29F160BE70/90 s BLOCK DIAGRAM DQ15 to DQ0 VCC VSS RY/BY Buffer RY/BY Erase Voltage Generator Input/Output Buffer WE BYTE RESET WP Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch State Control STB Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase Address Latch X-Decoder Cell Matrix A19 to A0 A-1 6 MBM29F160TE70/90/MBM29F160BE70/90 s DEVICE BUS OPERATIONS MBM29F160TE/BE User Bus Operation (BYTE = VIH) Operation Auto-Select Manufacture Code *1 Auto-Select Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Protection *2, *4 Verify Sector Protection * * Reset (Hardware)/Standby Boot Block Write Protection 2, 4 CE L L L H L L L L X X X OE L L L X H H VID L X X X WE H H H X H L H X X X A0 L H A0 X X A0 L L X X X A1 L L A1 X X A1 H H X X X A6 L L A6 X X A6 L L X X X A9 VID VID A9 X X A9 VID VID X X X DQ15 to DQ0 Code Code DOUT High-Z High-Z DIN X Code X High-Z X RESET H H H H H H H H VID L X WP X X X X X X X X X X L Temporary Sector Unprotection MBM29F160TE/BE User Bus Operation (BYTE = VIL) Operation Auto-Select Manufacture Code *1 Auto-Select Device Code * Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Protection *2, *4 Verify Sector Protection *2, *4 Temporary Sector Unprotection Reset (Hardware)/Standby Boot Block Write Protection 1 CE L L L H L L L L X X X OE L L L X H H VID L X X X WE H H H X H L H X X X DQ15 /A-1 L L A-1 X X A-1 L L X X X A0 L H A0 X X A0 L L X X X A1 L L A1 X X A1 H H X X X A6 L L A6 X X A6 L L X X X A9 VID VID A9 X X A9 VID VID X X X DQ7 to DQ0 RESET WP Code Code DOUT High-Z High-Z DIN X Code X High-Z X H H H H H H H H VID L X X X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH. = pulse input. See “sDC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29F160TE/BE Standard Command Definitions Table”. *2: Refer to “7. Sector Protection” in sFUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 5.0 V ± 10 % 7 MBM29F160TE70/90/MBM29F160BE70/90 MBM29F160TE/BE Standard Command Definitions Table Command Sequence *1, 2, 3, 5 Bus Write Cycles Req'd First Bus Write Cycle Addr Data Second Bus Write Cycle Addr Data Third Bus Write Cycle Addr Data Fourth Bus Read/Write Cycle Addr Data Fifth Bus Write Cycle Addr Data Sixth Bus Write Cycle Addr Data Read/Reset *6 Read/Reset *6 Autoselect Byte/Word Program *3, 4 Chip Erase Sector Erase *3 Sector Erase Suspend Sector Erase Resume Word /Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word /Byte Word /Byte 1 3 3 4 6 6 1 1 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh RA 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h RD 55h 55h 55h 55h 55h — 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh — F0h 90h A0h 80h 80h — RA — PA 555h AAAh 555h AAAh — RD — PD AAh AAh — — — — 2AAh 555h 2AAh 555h — — — — 55h 55h — — — — 555h AAh SA — — — — 10h 30h Erase can be suspended during sector erase with addr. (“H” or “L”). Data (B0h) Erase can be resumed after suspend with addr. (“H” or “L”). Data (30h) *1 : Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA). *2 : Bus operations are defined in “MBM29F160TE/BE User Bus Operation Tables (BYTE = VIH and BYTE = VIL)”. *3 : RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. *4 : RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. *5 : The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 Byte Mode: AAAh or 555h to addresses A10 to A-1 *6 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Note : The command combinations not described in “MBM29F160TE/BE Standard Command Definitions Table” and “MBM29F160TE/BE Extended Command Definitions Table” are illegal. 8 MBM29F160TE70/90/MBM29F160BE70/90 MBM29F160TE/BE Extended Command Definitions First Bus Second Bus Third Bus Bus Write Write Cycle Write Cycle Write Cycle Cycles Req'd Command Sequence Set to Fast Mode Fast Program *1 Word Byte Word Byte Fourth Bus Read Cycle Addr — — — Data — — — Addr 555h AAAh XXXh XXXh XXXh XXXh 55h Data AAh A0h 90h Addr 2AAh 555h PA XXXh XXXh Data 55h PD F0h *3 Addr 555h AAAh — — Data 20h — — 3 2 2 2 Reset from Fast Word Mode *1 Byte Query Command *2 Word 98h — — — — — — Byte AAh SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD : Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1: This command is valid while fast mode. *2: Addresses from system set to A6 to A0. The other addresses are “Don’t Care”. *3: The data “00h” is also acceptable. MBM29F160TE/BE Sector Protection Verify Autoselect Code A6 A1 A0 A19 to A12 A-1*1 X Byte Word Byte Word X X Sector Addresses Type Manufacture’s Code Code (HEX) 04h D2h 22D2h D8h 22D8h 01h*2 VIL VIL VIL VIL VIL VIL VIL VIH VIL VIH VIH VIL VIL VIL X VIL X VIL MBM29F160TE Device Code MBM29F160BE Sector Protection *1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. Extended Autoselect Code Table Type Manufacture’s Code Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h A-1/0 A-1 0 A-1 0 0 Hi-Z 0 Hi-Z 0 0 0 Hi-Z 1 Hi-Z 1 0 0 Hi-Z 0 Hi-Z 0 0 0 Hi-Z 0 Hi-Z 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 MBM29F160 (B)* D2h (W) 22D2h Device TE Hi-Z Hi-Z Hi-Z 0 1 0 Code MBM29F160 (B)* D8h BE (W) 22D8h Hi-Z Hi-Z Hi-Z 0 0 1 0 0 0 01h A-1/0 Sector Protection (B): Byte mode, (W): Word mode Hi-Z: High-Z *: At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 9 MBM29F160TE70/90/MBM29F160BE70/90 s FLEXIBLE SECTOR-ERASE ARCHITECTURE • • • • One 8K word, two 4K words, one 16K word and thirty-one 32K words sectors in word mode. One 16K byte, two 8K bytes, one 32K byte and thirty-one 64K bytes sectors in byte mode. Individual-sector, multiple-sector, or bulk-erase capability. Individual or multiple-sector protection is user definable. Sector Address Table (MBM29F160TE) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X (× 8) Address Range 00000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F9FFFh 1FA000h to 1FBFFFh 1FC000h to 1FFFFFh (× 16) Address Range 00000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh 80000h to 87FFFh 88000h to 8FFFFh 90000h to 97FFFh 98000h to 9FFFFh A0000h to A7FFFh A8000h to AFFFFh B0000h to B7FFFh B8000h to BFFFFh C0000h to C7FFFh C8000h to CFFFFh D0000h to D7FFFh D8000h to DFFFFh E0000h to E7FFFh E8000h to EFFFFh F0000h to F7FFFh F8000h to FBFFFh FC000h to FCFFFh FD000h to FDFFFh FE000h to FFFFFh 10 MBM29F160TE70/90/MBM29F160BE70/90 Sector Address Table (MBM29F160BE) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X (× 8) Address Range 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh 100000h to 1FFFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh (× 16) Address Range 00000h to 01FFFh 02000h to 02FFFh 03000h to 03FFFh 04000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh 80000h to 87FFFh 88000h to 8FFFFh 90000h to 97FFFh 98000h to 9FFFFh A0000h to A7FFFh A8000h to 8FFFFh B0000h to B7FFFh B8000h to BFFFFh C0000h to C7FFFh C8000h to CFFFFh D0000h to D7FFFh D8000h to DFFFFh E0000h to E7FFFh E8000h to EFFFFh F0000h to F7FFFh F8000h to FFFFFh 11 MBM29F160TE70/90/MBM29F160BE70/90 MBM29F160TE Top Boot Sector Architecture Sector Size (× 8) Address Range 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 32 Kbytes or 16 Kwords 8 Kbytes or 4 Kwords 8 Kbytes or 4 Kwords 16 Kbytes or 8 Kwords 00000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F9FFFh 1FA000h to 1FBFFFh 1FC000h to 1FFFFFh Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 (× 16) Address Range 00000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh 80000h to 87FFFh 88000h to 8FFFFh 90000h to 97FFFh 98000h to 9FFFFh A0000h to A7FFFh A8000h to AFFFFh B0000h to B7FFFh B8000h to BFFFFh C0000h to C7FFFh C8000h to CFFFFh D0000h to D7FFFh D8000h to DFFFFh E0000h to E7FFFh E8000h to EFFFFh F0000h to F7FFFh F8000h to FBFFFh FC000h to FCFFFh FD000h to FDFFFh FE000h to FFFFFh 12 MBM29F160TE70/90/MBM29F160BE70/90 MBM29F160BE Bottom Boot Sector Architecture Sector Size (× 8) Address Range (× 16) Address Range 16 Kbytes or 8 Kwords 8 Kbytes or 4 Kwords 8 Kbytes or 4 Kwords 32 Kbytes or 16 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 64 Kbytes or 32 Kwords 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh 00000h to 01FFFh 02000h to 02FFFh 03000h to 03FFFh 04000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh 80000h to 87FFFh 88000h to 8FFFFh 90000h to 97FFFh 98000h to 9FFFFh A0000h to A7FFFh A8000h to AFFFFh B0000h to B7FFFh B8000h to BFFFFh C0000h to C7FFFh C8000h to CFFFFh D0000h to D7FFFh D8000h to DFFFFh E0000h to E7FFFh E8000h to EFFFFh F0000h to F7FFFh F8000h to FFFFFh Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 13 MBM29F160TE70/90/MBM29F160BE70/90 Common Flash Memory Interface Code Table Description Query-unique ASCII string “QRY” Primary OEM Command Set 02h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VCC Max (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/ word write 2N µs Typical timeout for Min size buffer write 2N µs Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual sector erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 02h : x8/ x16 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device A6 to A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0045h Description Erase Block Region 1 Information A6 to A0 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 45h 46h DQ15 to DQ0 0000h 0000h 0040h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h 0050h 0052h 0049h 0031h 0031h 0000h 0002h Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 0055h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0015h 0002h 0000h 0000h 0000h 0004h Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 00h = Required Erase Suspend 02h = To Read & Write Sector Protect X = Number of sectors in per group Sector Temporary Unprotect 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC Min (Acceleration) Supply 00h = Not Supported VACC Max (Acceleration) Supply 00h = Not Supported Boot Type 02h = MBM29F160BE 03h = MBM29F160TE 47h 0001h 48h 49h 4Ah 4Bh 4C 4Dh 4Eh 0001h 0004h 0000h 0000h 0000h 0000h 0000h 4Fh 00XXh 14 MBM29F160TE70/90/MBM29F160BE70/90 s FUNCTIONAL DESCRIPTION 1. Read Mode The MBM29F160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC - tOE time.) When reading out a data without changing addresses after power-u, it is necessary to input hardware reset or change CE pin from “H” to “L”. 2. Standby Mode There are two ways to implement the standby mode on the MBM29F160TE/BE devices. One is by using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ± 0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode, the outputs are in the high-impedance state, independent of the OE input. 3. Output Disable If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state. 4. Autoselect The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors. (See “MBM29F160TE/BE Sector Protection Verify Autoselect Code Table” and “Expanded Autoselect Code Table” in sDEVICE BUS OPERATIONS.) This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1 and A6 (A-1). (See “MBM29F160TE/BE User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” in sDEVICE BUS OPERATIONS.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29F160TE/BE is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29F160TE/BE Standard Command Definitions Table” in sDEVICE BUS OPERATIONS. Byte 0 (A0 = VIL) represents the manufacture’s code (Fujitsu = 04h) and byte 1 (A0 = VIH) represents the device identifier code (MBM29F160TE = D2h and MBM29F160BE = D8h for x 8 mode; MBM29F160TE = 22D2h and MBM29F160BE = 22D8h for x 16 mode). These two bytes/words are given in “MBM29F160TE/BE Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” (sDEVICE BUS OPERATIONS). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See “MBM29F160TE/BE Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in sDEVICE BUS OPERATIONS.) 15 MBM29F160TE70/90/MBM29F160BE70/90 5. Write Device erasure and programming are accomplished via the command register. The command register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. 6. Write Protect (WP) The write Protect function provides a hardware method of protecting certain boot sectors without using VID. If the system asserts VIL on the WP pin, the device disables program and erase functions in the “outermost” 16K byte boot sectors independently of whether this sector was protected or unprotected using the method described in “Sector / Sector Block Protection and Unprotection”. The outmost 16K byte boot sector is the sector containing the lowest addresses in a bottom-boot-configured devices, or the sector containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP pin, the devices reverts to whether the outmost 16K byte boot sector was last set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on whether it was last protected or unprotected using the method describe in “Sector / Sector Block Protection and Unprotection”. 7. Sector Protection The MBM29F160TE/BE features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A6 = VIL. The sector addresses (A19, A18, A17, A16, A15, A14, A13 and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29F160TE/BE)” in sFLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See “13. AC Waveforms for Sector Protection Timing Diagram” in sTIMING DIAGRAM and “6. Temporary Sector Unprotection Algorithm” in sFLOW CHART for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13 and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL in byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29F160TE/BE Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in sDEVICE BUS OPERATIONS for Autoselect codes. 8. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29F160TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. Refer to “14. Temporary Sector Unprotection Timing Diagram” in sTIMING DIAGRAM and “6. Temporary Sector Unprotection Algorithm” in sFLOW CHART. 16 MBM29F160TE70/90/MBM29F160BE70/90 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. “MBM29F160TE/BE Standard Command Definitions Table” in sDEVICE BUS OPERATIONS defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. 1. Read/Reset Command The read or reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. 2. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h for ×16 (XX02h for ×8) retrieves the device code (MBM29F160TE = D2h and MBM29F160BE = D8h for ×8 mode; MBM29F160TE = 22D2h and MBM29F160BE = 22D8h for ×16 mode). (See “MBM29F160TE/BE Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in sDEVICE BUS OPERATIONS.) All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit. The sector state (protection or unprotection) will be indicated by address XX02h for ×16 (XX04h for ×8). Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13 and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode verification on the protected sector. (See “MBM29F160TE/BE User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” in sDEVICE BUS OPERATIONS.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command sequence. 3. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See “3. AC Waveforms for Alternate WE Controlled Program Operations” and “4. AC Waveforms for Alternate CE Controlled Program Operations” in sTIMING DIAGRAM.) The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware 17 MBM29F160TE70/90/MBM29F160BE70/90 Sequence Flags Table”.) Therefore, the device requires that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “1. Embedded ProgramTM Algorithm” in sFLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. 4. Chip Erase Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See “8. Write Operation Status”.) at which time the device returns to read mode. (See “5. AC Waveforms for Chip/Sector Erase Operations” in sTIMING DIAGRAM.) “2. Embedded EraseTM Algorithm” in sFLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 5. Sector Erase Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30h) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing six-bus cycle operations on “MBM29F160TE/BE Standard Command Definitions Table” in sDEVICE BUS OPERATIONS. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 µs time-out window the timer is reset. Monitor DQ3 to determine if the sector erase timer window is still open. (See “12. DQ3”, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to “8. Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. (See “5. AC Waveforms for Chip/Sector Erase Operations” in sTIMING DIAGRAM.) The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See “8. Write Operation Status”.) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase Time] × Number of Sector Erase. 18 MBM29F160TE70/90/MBM29F160BE70/90 “2. Embedded EraseTM Algorithm” in sFLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 6. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See “13. DQ2”.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 7. Extended Command (1) Fast Mode MBM29F160TE/BE has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to “7. Embedded Programming Algorithm for Fast Mode” in sFLOW CHART Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to “7. Embedded Programming Algorithm for Fast Mode” in sFLOW CHART Extended algorithm.) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command 19 MBM29F160TE70/90/MBM29F160BE70/90 write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to “Common Flash Memory Interface Code Table” in sFLEXIBLE SECTOR-ERASE ARCHITECTURE. To terminate operation, it is necessary to write the read/reset command sequence into the register. 8. Write Operation Status Status Hardware Sequence Flags Table DQ6 DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 Toggle Toggle 1 Data Toggle *1 Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle Toggle Data 1 *2 1 N/A N/A Embedded Program Algorithm Embedded/Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded/Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode In Progress *1: Performing successive read operations from any address will cause DQ6 to toggle. *2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes: • DQ1 and DQ0 are reserve pins for future use. • DQ4 is Fujitsu internal use only. 9. DQ7 Data Polling The MBM29F160TE/BE device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “3. Data Polling Algorithm” in sFLOW CHART. For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29F160TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See “6. AC Waveforms for Data Polling during Embedded Algorithm Operations” in sTIMING DIAGRAM for the Data Polling timing specifications and diagrams. 20 MBM29F160TE70/90/MBM29F160BE70/90 10. DQ6 Toggle Bit I The MBM29F160TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the sixwrite pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 100 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See “7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in sTIMING DIAGRAM and “4. Toggle Bit Algorithm” in sFLOW CHART for the Toggle Bit I timing specifications and diagrams. 11. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in “MBM29F160TE/BE User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” in sDEVICE BUS OPERATIONS. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. 12. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags Table”. 13. DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the 21 MBM29F160TE70/90/MBM29F160BE70/90 device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ2. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. Toggle Bit Status Table Mode Program Erase Erase Suspend Read (Erase Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle *1 DQ2 1 Toggle Toggle 1 *2 *1: Performing successive read operations from any address will cause DQ6 to toggle. *2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” and “15. DQ2 vs. DQ6” in sTIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. 14. RY/BY Ready/Busy Pin The MBM29F160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29F160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. See “8. RY/BY Timing Diagram during Program/Erase Operations” in sTIMING DIAGRAM and 12 for a detailed timing diagram. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel. 15. RESET Hardware Reset Pin The MBM29F160TE/BE device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least tRP in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional tRH before it allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to “9. RESET, RY/BY Timing Diagram” in sTIMING DIAGRAM for the timing diagram. Refer to “8. Temporary Sector Unprotection” in sFUNCTIONAL DESCRIPTION for additional functionality. 22 MBM29F160TE70/90/MBM29F160BE70/90 If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will need to be erased again before they can be programmed. 16. Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F160TE/BE device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to “10. Timing Diagram for Word Mode Configuration” and “11. Timing Diagram for Byte Mode Configuration” in sTIMING DIAGRAM for the timing diagrams. 17. Data Protection The MBM29F160TE/BE is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 18. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V. If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. 19. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers. 20. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. 21. Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 22. Sector Protection Device user is able to protect each sector individually to store and protect data. Protection circuit voids both write and erase commands that are addressed to protected sectors. Any commands to write or erase addressed to protected sector are ignore. Refer to “7. Sector Protection” in s FUNCTIONAL DESCRIPTION. 23 MBM29F160TE70/90/MBM29F160BE70/90 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET *1, *2 Power Supply Voltage *1 A9, OE and RESET * * 1, 3 Symbol Tstg TA VIN, VOUT VCC VIN Rating Min –55 –40 –2.0 –2.0 –2.0 Max +125 +85 +7.0 +7.0 +13.5 Unit °C °C V V V *1: Voltage is defined on the basis of VSS = GND = 0 V. *2: Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on A9, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.5 V which may overshoot to +14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage* Symbol TA VCC Value Min –40 +4.50 Max +85 +5.50 Unit °C V * : Voltage is defined on the basis of VSS = GND = 0 V. Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24 MBM29F160TE70/90/MBM29F160BE70/90 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Figure 1 Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 20 ns +14.0 V +13.5 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE and RESET. Figure 3 Maximum Overshoot Waveform 2 25 MBM29F160TE70/90/MBM29F160BE70/90 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current VCC Active Current *1 VCC Active Current *2 Symbol ILI ILO ILIT ICC1 ICC2 Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH VCC = VCC Max, CE = VIH, RESET = VIH VCC = VCC Max, CE = VCC ± 0.3 V, RESET = WP = VCC ± 0.3 V VCC = VCC Max, RESET = VIL VCC=VCC Max, RESET=VSS ± 0.3 V, WP = VCC ± 0.3 V — — Byte Word Value Min –1.0 –1.0 — — — — — — — –0.5 2.0 Max +1.0 +1.0 50 40 50 60 1 5 1 5 0.8 VCC + 0.5 Unit µA µA µA mA mA mA µA mA µA V V VCC Current (Standby) ICC3 VCC Current (Standby, RESET) ICC4 Input Low Level Input High Level Voltage for Autoselect, Sector Protection and Temporary Sector Unprotection (A9, OE, RESET) *3 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage VIL VIH VID — 11.5 12.5 V VOL VOH1 VOH2 VLKO IOL = 5.8 mA, VCC = VCC Min IOH = –2.5 mA, VCC = VCC Min IOH = –100 µA — — 2.4 VCC – 0.4 3.2 0.45 — — 4.2 V V V V *1: The lCC current listed includes both the DC operating current and the frequency dependent component. *2: lCC active while Embedded Erase or Embedded Program is in progress. *3: (VID – VCC) do not exceed 9 V. Note: Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 26 MBM29F160TE70/90/MBM29F160BE70/90 s AC CHARACTERISTICS • Read Only Operations Characteristics Symbol Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High *1: Test Conditions Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX — — 70 *1 Min 70 — — — — — 0 — — Max — 70 70 30 20 20 — 20 5 90 — — — — — 0 — — 90 *2 Min Max — 90 90 40 20 20 — 20 5 JEDEC Standard Test Setup — CE = VIL, OE = VIL OE = VIL — — — — — — Unit ns ns ns ns ns ns ns µs ns tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH *2: Test Conditions Output Load: 1 TTL gate and 100 pF Input rise and fall times: 5 ns Input pulse levels: 0.45 V or 2.4 V Timing measurement reference level Input: 0.8 V and 2.0 V Output: 0.8 V and 2.0 V 5.0 V Diode = 1N3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diode = 1N3064 or Equivalent Notes: CL = 30 pF including jig capacitance (MBM29F160TE70, MBM29F160BE70) CL = 100 pF including jig capacitance (MBM29F160TE90, MBM29F160BE90) Figure 4 Test Conditions 27 MBM29F160TE70/90/MBM29F160BE70/90 • Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Read Hold Time Toggle and Data Polling Read Recover Time Before Write Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation *1 Delay Time from Embedded Output Enable VCC Setup Time Voltage Transition Time * Write Pulse Width * 2 2 2 Symbol JEDEC Standard 70 Min Typ Max Min 90 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs s ns µs µs µs µs µs ns ns ns ns ns ns ns tAVAV tAVWL tWLAX tDVWH tWHDX — — tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word tWHWH1 tWHWH2 — — — — — — — — — — — — — 2 tWC tAS tAH tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tEOE tVCS tVLHT tWPP tOESP tCSP tRB tRH tBUSY tFLQZ tFHQV tVIDR tRP 70 0 45 30 0 0 0 10 0 0 0 0 0 0 35 35 20 20   1  50 4 100 4 4 0 50    500 500                   8 16                                    70        70 30 70   90 0 45 45 0 0 0 10 0 0 0 0 0 0 45 45 20 20   1  50 4 100 4 4 0 50    500 500                   8 16                                    90        90 40 90   OE Setup Time to WE Active * CE Setup Time to WE Active * Recover Time From RY/BY RESET Hold Time Before Read Program/Erase Valid to RY/BY Delay BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Rise Time to VID * 2 RESET Pulse Width *1: This does not include the preprogramming time. *2: This timing is for Sector Protection operation. 28 MBM29F160TE70/90/MBM29F160BE70/90 s ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Min Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle — — — — 100,000 Typ 1 8 16 16.8 — Max 8 150 µs 200 40 — s cycle s Excludes preprogramming time prior to erasure Excludes system-level overhead Excludes system-level overhead — Unit Comments s TSOP (1) PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8 7.5 Max 7.5 10 9 Unit pF pF pF Notes : •Test conditions TA = +25°C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 29 MBM29F160TE70/90/MBM29F160BE70/90 s TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from "H" to "L" May Change from "L" to "H" "H" or "L" ; Any Change Permitted OUTPUTS Will Be Steady Will Be Change from "H" to "L" Will Be Change from "L" to "H" Changing, State Unknown Center Line Is High-Impedance "Off" State Does Not Apply 1. AC Waveforms Read Operations tRC Address tACC Address Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z Outputs Output Valid 30 MBM29F160TE70/90/MBM29F160BE70/90 2. AC Waveforms for Hardware Reset/Read Operations tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid 3. AC Waveforms for Alternate WE Controlled Program Operations 3rd Bus Cycle Data Polling PA tAS tAH PA tRC Address 555h tWC CE tCS tCH tCE OE tGHWL tWP tWPH tWHWH1 tOE WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes: • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 31 MBM29F160TE70/90/MBM29F160BE70/90 4. AC Waveforms for Alternate CE Controlled Program Operations 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH PD DQ7 DOUT Data A0h Notes: • • • • • • PA is address of the memory location to be programmed. PD is data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 32 MBM29F160TE70/90/MBM29F160BE70/90 5. AC Waveforms for Chip/Sector Erase Operations Address 555h 2AAh 555h 555h 2AAh SA* tWC tAS tAH CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 30h for Sector Erase 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase. Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 33 MBM29F160TE70/90/MBM29F160BE70/90 6. AC Waveforms for Data Polling during Embedded Algorithm Operations CE tCH tOE tDF OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Output Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation). 7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations CE tOEH WE tOES OE * tOH DQ6 = Stop Toggling tOE DQ7 to DQ0 Data Valid DQ6 Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Toggle * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) 34 MBM29F160TE70/90/MBM29F160BE70/90 8. RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last WE signal WE Entlre programming or erase operations RY/BY tBUSY 9. RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY 10. Timing Diagram for Word Mode Configuration CE OE BYTE DQ14 to DQ0 tELFH tFHQV DQ7 to DQ0 DQ14 to DQ0 DQ15/A -1 A -1 DQ15 35 MBM29F160TE70/90/MBM29F160BE70/90 11. Timing Diagram for Byte Mode Configuration CE OE BYTE DQ14 to DQ0 tELFL DQ14 to DQ0 DQ7 to DQ0 DQ15/A -1 DQ15 tFLQZ A -1 12. BYTE Timing Diagram for Write Operations Falling edge of the last write signal CE or WE BYTE tSET (tAS) Input Valid tHOLD (tAH) 36 MBM29F160TE70/90/MBM29F160BE70/90 13. AC Waveforms for Sector Protection Timing Diagram A19, A18, A17 A16, A15, A14 A13, A12 SAX SAY A6, A0 A1 VID 5V A9 tVLHT tVIDR VID 5V OE tVLHT tWPP tVIDR tVLHT WE tOESP tVLHT CE tCSP Data tVCS tOE 01h VCC SAX: Sector Address for initial sector SAY: Sector Address for next sector Note: A-1 is VIL on byte mode. 37 MBM29F160TE70/90/MBM29F160BE70/90 14. Temporary Sector Unprotection Timing Diagram VCC tVCS VID 3V RESET CE tVIDR tVLHT 3V WE tVLHT RY/BY Program or Erase Command Sequence tVLHT Unprotection period 15. DQ2 vs. DQ6 Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Rasume Erase Suspend Read Erase Erase Complate WE Erase Suspend Read DQ6 DQ2 Toggle DQ2 and DQ6 With OE or CE Note : DQ2 is read from the erase-suspended sector. 38 MBM29F160TE70/90/MBM29F160BE70/90 s FLOW CHART 1. Embedded ProgramTM Algorithm Start Write Program Command Sequence (See Below) Data Polling Davice Verify Byte ? Yes Increment Address No Last Address ? Yes Programming Completed No Program Command Sequence* (Address/Command) : 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data * : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. 39 MBM29F160TE70/90/MBM29F160BE70/90 2. Embedded EraseTM Algorithm Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device No Data = FFh? Yes Erasure Completed Chip Erase Command Sequence* (Address/Command) : Individual Sector/Multlple Sector* Erase Command Sequence (Address/Command) : 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address/ 30h Sector Address/ 30h Sector Address/ 30h Additional sector erase commands are optional. * : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. 40 MBM29F160TE70/90/MBM29F160BE70/90 3. Data Polling Algorithm VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data ? No No DQ5 = 1 ? Yes Read Byte (DQ7 to DQ0) Addr. = VA Yes DQ7 = Data ? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 41 MBM29F160TE70/90/MBM29F160BE70/90 4. Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = “H” or “L” *1 Read DQ7 to DQ0 Addr. = “H” or “L” DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read DQ7 to DQ0 Addr. = “H” or “L” No *1, *2 Read DQ7 to DQ0 Addr. = “H” or “L” *1, *2 DQ6 = Toggle ? No Yes Program/Erase Operation Not Complete. Write Reset Ccommand. Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 42 MBM29F160TE70/90/MBM29F160BE70/90 5. Sector Protection Algorithm Start Setup Sector Addr, (A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Increment PLSCNT Activate WE Pulse Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector (A1 = VIH, A0 = VIL Addr. = SA, A6 = VIL) * No PLSCNT = 25 ? Yes Pemove VID from A9 Write Reset Command No Data = 01h ? Yes Protect Another Sector ? No Device Failed Remove VID from A9 Write Reset Command Yes Sector Protection Completed * : A-1 is VIL on byte mode. 43 MBM29F160TE70/90/MBM29F160BE70/90 6. Temporary Sector Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Unprotection Completed*2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. 44 MBM29F160TE70/90/MBM29F160BE70/90 7. Embedded Programming Algorithm for Fast Mode Start 555h/AAh 2AAh/55h Set Fast Mode* 555h/20h XXXXh/A0h Program Address/Program Data Data Polling Device Verify Byte ? Yes Increment Address No Last Address ? Yes Programming Completed No in Fast Program XXXXh/90h Reset Fast Mode XXXXh/F0h * : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. 45 MBM29F160TE70/90/MBM29F160BE70/90 s ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29F160 T E 70 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP (1) ) Normal Bend TR = 48-Pin Thin Small Outline Package (TSOP (1) ) Reverse Bend SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29F160 16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory 5.0 V-only Read, Write and Erase 46 MBM29F160TE70/90/MBM29F160BE70/90 s PACKAGE DIMENSIONS 48-pin plastic TSOP (1) (FPT-48P-M19) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48 LEAD No. 1 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) * 12.00±0.20 (.472±.008) 1.10 –0.05 +0.10 +.004 .043 –.002 (Mounting height) 0.50(.020) "A" 0.10(.004) 0.17 –0.08 .007 –.003 C +0.03 +.001 0.10±0.05 (.004±.002) (Stand off height) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued) 47 MBM29F160TE70/90/MBM29F160BE70/90 (Continued) 48-pin plastic TSOP (1) (FPT-48P-M20) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48 LEAD No. 1 INDEX Details of "A" part 0.60±0.15 (.024±.006) 0~8˚ 0.25(.010) 24 25 0.17 –0.08 +0.03 +.001 0.10(.004) .007 –.003 0.50(.020) 0.22±0.05 (.009±.002) 0.10(.004) M 0.10±0.05 (.004±.002) (Stand off height) "A" 1.10 –0.05 +0.10 +.004 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) .043 –.002 (Mounting height) * 12.00±0.20(.472±.008) C 2003 FUJITSU LIMITED F48030S-c-6-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. 48 MBM29F160TE70/90/MBM29F160BE70/90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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