V
S25FL016A
16 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
S25FL016A Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S25FL016A_00
Revision C
Amendment 3
Issue Date January 7, 2008
Data
Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S25FL016A
S25FL016A_00_C3 January 7, 2008
S25FL016A
16 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6 V read and program operations
Package Option
– – – – Industry Standard Pinouts 16-pin SO package (300 mils) 8-pin SO package (208 mils) 8-Contact WSON Package (6x8 mm), Pb Free
Memory Architecture
– Thirty-two sectors with 512 Kb each
Program
– Page Program (up to 256 bytes) in 1.4 ms (typical) – Program operations are on a page by page basis
Performance Characteristics
Speed
– 50 MHz clock rate (maximum)
Erase
– 0.5 s typical sector erase time – 10 s typical bulk erase time
Power Saving Standby Mode
– Standby Mode 50 µA (max) – Deep Power Down Mode 1.3 µA (typical)
Cycling Endurance
– 100,000 cycles per sector typical
Data Retention
– 20 years typical
Memory Protection Features
Memory Protection
– W# pin works in conjunction with Status Register Bits to protect specified memory areas – Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only
Device ID
– JEDEC standard two-byte electronic signature – RES command one-byte electronic signature for backward compatibility
Process Technology
– Manufactured on 0.20 µm MirrorBit® process technology
Software Features
– SPI Bus Compatible Serial Interface
General Description
The S25FL016A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of thirty-two sectors, each with 512 Kb memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0 volt VCC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require a VPP supply.
Publication Number S25FL016A_00
Revision C
Amendment 3
Issue Date January 7, 2008
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.
Data
Sheet
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2. 3. 4. 5. 6. 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 12 12 13 13
8. 9.
Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 Write Status Register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.11 Deep Power Down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.12 Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 18 19 19 20 21 22 23 23 24
10. 11. 12. 13. 14. 15. 16. 17.
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 SOC008 wide—8-pin Plastic Small Outline Package (208 mils Body Width) . . . . . . . . . . . . 17.2 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . . 17.3 WSON 8-contact (6 x 8 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 34
18.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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S25FL016A
S25FL016A_00_C3 January 7, 2008
Data
Sheet
Figures
Figure 2.1 Figure 2.2 Figure 2.3 Figure 6.1 Figure 6.2 Figure 7.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 10.1 Figure 12.1 Figure 12.2 Figure 15.1 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 Mb 8-Pin WSON Package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 17 Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 18 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Release from Deep Power Down (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 24 Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 31
January 7, 2008 S25FL016A_00_C3
S25FL016A
5
Data
Sheet
Tables
Table 5.1 Table 7.1 Table 8.1 Table 8.2 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 12.1 Table 13.1 Table 14.1 Table 15.1 Table 16.1 S25FL016A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 S25FL016A Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 S25FL016A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 S25FL016A Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 S25FL016A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6
S25FL016A
S25FL016A_00_C3 January 7, 2008
Data
Sheet
1. Block Diagram
SRAM
PS
Array - L Logic
X D E C
Array - R
RD
DATA PATH
IO
GND
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
HOLD# VCC NC NC NC NC CS# SO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCK SI NC NC NC NC GND W#
January 7, 2008 S25FL016A_00_C3
S25FL016A
HOLD#
CS#
SCK
SI
SO
VCC
7
Data
Sheet
Figure 2.2 8-pin Plastic Small Outline Package (SO)
CS# SO W# GND
1 2 3 4
8 7 6 5
VCC HOLD# SCK SI
Figure 2.3 16 Mb 8-Pin WSON Package (6 x 8 mm)
CS# SO
W# GND
1 2
WSON
8 7 6 5
VCC HOLD# SCK SI
3 4
8
S25FL016A
S25FL016A_00_C3 January 7, 2008
Data
Sheet
3. Input/Output Descriptions
Signal SO SI SCK I/O Output Input Input Description Signal Data Output: Transfers data serially out of the device on the falling edge of SCK. Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. Chip Select: Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Supply Voltage Ground
CS#
Input
HOLD#
Input
W# VCC GND
Input Input Input
4. Logic Symbol
VCC
SI SCK CS# W# HOLD#
SO
GND
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Data
Sheet
5. Ordering Information
The ordering part number is formed by a valid combination of the following:
S25FL 016 A 0L M A I 00 1 PACKING TYPE (Note 1) 0 = Tray 1 = Tube 3 = 13” Tape and Reel MODEL NUMBER (Additional Ordering Options) 01 = 8-pin SO package 00 = 16-pin SO / 8-contact WSON package TEMPERATURE RANGE I = Industrial (–40°C to + 85°C) PACKAGE MATERIALS A = Standard F = Lead (Pb)-free PACKAGE TYPE M = 8-pin / 16-pin SO package N = 8-contact WSON Package SPEED 0L = 50 MHz
DEVICE TECHNOLOGY A = 0.20 µm MirrorBit® Process Technology DENSITY 016 = 16 Mbit DEVICE FAMILY
S25FL Spansion® Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
5.1
Valid Combinations
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. Table 5.1 S25FL016A Valid Combinations Table
S25FL016A Valid Combinations Base Ordering Part Number S25FL016A Speed Option 0L Package & Temperature MAI, MFI NAI, NFI Model Number 00, 01 00 Package Marking Packing Type 0, 1, 3 (Note 1) 0, 1, 3 (Note 1)
(Note 2)
FL016A + (Temp) +
(Note 3)
Notes 1. Contact your local sales office for availability. 2. Package marking omits leading “S25” and speed, package, and model number form. 3. A for standard package (non-Pb free); F for Pb-free package.
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S25FL016A_00_C3 January 7, 2008
Data
Sheet
6. Spansion SPI Modes
A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes. When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes: SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0) SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3) Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master
SI SCK SCK SO SI SCK SO SI SCK SO SI
SPI Memory Device CS3 CS2 CS1
CS# W# HOLD#
SPI Memory Device
SPI Memory Device
CS#
W#
HOLD#
CS#
W#
HOLD#
Note The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.
Figure 6.2 SPI Modes Supported
CS# CPOL CPHA Mode 0 Mode 3 0 1 0 1 SCK SCK SI SO MSB MSB
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Data
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7. Device Operations
All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time).
7.1
Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation. Before this can be applied, the bytes of the memory need to be first erased to all 1’s (FFh) before any programming.
7.2
Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.
7.3
Monitoring Write Operations Using the Status Register
The host system can determine when a Write Status Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit.
7.4
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status Register operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to IDP.
7.5
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.2, S25FL016A Status Register on page 19): Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected against program and erase commands. Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
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7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods: The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – Page Program (PP) – Sector Erase (SE) – Bulk Erase (BE) – Write Disable (WRDI) – Write Status Register (WRSR) Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not programmed or erased. Table 7.1 shows the sizes and address ranges of protected areas that are defined by Status Register bits BP2:BP0. Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable (SRWD) bit together provide write protection. Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands consist of a clock pulse count that is a multiple of eight before executing them. Table 7.1 S25FL016A Protected Area Sizes
Status Register Block Protect Bits BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Address Range None 1F0000h–1FFFFFh 1E0000h–1FFFFFh 1C0000h–1FFFFFh 180000h–1FFFFFh 100000h–1FFFFFh 000000h–1FFFFFh 000000h–1FFFFFh Memory Array Protected Sectors (0) (1) SA31 (2) SA31:SA30 (4) SA31:SA28 (8) SA31:SA24 (16) SA31:SA16 (32) SA31:SA0 (32) SA31:SA0 Unprotected Address Range 000000h–1FFFFFh 000000h–1EFFFFh 000000h–1DFFFFh 000000h–1BFFFFh 000000h–17FFFFh 000000h–0FFFFFh None None Unprotected Sectors SA31:SA0 SA30:SA0 SA29:SA0 SA27:SA0 SA23:SA0 SA15:SA0 None None Protected Portion of Total Memory Area 0 1/32 1/16 1/8 1/4 1/2 All All
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write Status Register, program or erase operation that is currently in progress. The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of SCK (non-standard use). The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (nonstandard use) See Figure 7.1. The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the Hold mode. CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low.
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Figure 7.1 Hold Mode Operation
SCK HOLD#
Hold Condition (standard use)
Hold Condition (non-standard use)
8. Sector Address Table
Table 8.1 shows the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or device-wide basis using the SE or BE commands. Table 8.2 shows the starting and ending address for each sector. The complete set of sectors comprises the memory array of the Flash device. Table 8.1 S25FL016A Device Organization
Each Device has 2,097,152 8,192 32 Each Sector has 65,536 256 — Each Page has 256 — — bytes pages sectors
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Table 8.2 S25FL016A Sector Address Table
Sector SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h Address Range 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh
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9. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on the rising edge of SCK. Table 9.4 on page 25 lists the complete set of commands. Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed (FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation. The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of eight. The device ignores any attempt to access the memory array during a Write Status Register, program, or erase operation, and continues the operation uninterrupted.
9.1
Read Data Bytes (READ)
The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. Figure 9.1 and Table 9.4 on page 25 detail the READ command sequence. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The READ command is terminated by driving CS# high at any time during data output. The device rejects any READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. Figure 9.1 Read Data Bytes (READ) Command Sequence
CS#
Mode 3
0
1
23
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCK
Mode 0
Command
24-Bit Address
SI
23 22 21
MSB
3210
Data Out 1 Data Out 2
SO
Hi-Z
765432
MSB
107
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9.2
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# low. The FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. The FAST_READ command sequence is shown in Figure 9.2 and Table 9.4 on page 25. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The FAST_READ command is terminated by driving CS# high at any time during data output. The device rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence
CS#
Mode 3 0 1 2 5 6 7 8 9 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
3
4
10
47
SCK
Mode 0
Command SI SO
Hi-Z
24-Bit Address
23 22 21 3 2 1 0 7
Dummy Byte
6 5 4 3 2 1 0
7 MSB
6
5
4
3
2
1
0
7 MSB DATA OUT 2
DATA OUT 1
9.3
Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification, to the host system. JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer assigns the device identification: the first byte provides the memory type; the second byte indicates the memory capacity. See Table 9.1 on page 18 or Table 9.4 on page 25 for device ID data. The host system must first select the device by driving CS# low. The RDID command is then written to SI, and each bit is latched on the rising edge of SCK. The 24-bit device identification data is output from the memory array on SO at a frequency fSCK, on the falling edge of SCK. The RDID command sequence is shown in Figure 9.3 and Table 9.4 on page 25. Driving CS# high after the device identification data has been read at least once terminates the READ_ID command. Driving CS# high at any time during data output also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted.
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Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence
CS#
SCK
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15 16
17 18
28 29 30 31
Mode 0
Command SI Manufacturer Identification SO Hi-Z
MSB
Device Identification 15 14 13 3 2 1 0
Table 9.1 Read Identification (RDID) Data-Out Sequence
Device Identification Manufacturer Identification 01h Memory Type 02h Memory Capacity 14h
9.4
Write Enable (WREN)
The Write Enable (WREN) command (see Figure 9.4) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. Figure 9.4 Write Enable (WREN) Command Sequence
CS#
Mode 3
01
23
4
567
SCK
Mode 0
Command SI Hi-Z SO
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9.5
Write Disable (WRDI)
The Write Disable (WRDI) command (see Figure 9.5) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a Write Status Register, program, or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high. Any of following conditions resets the WEL bit: Power-up Write Disable (WRDI) command completion Write Status Register (WRSR) command completion Page Program (PP) command completion Sector Erase (SE) command completion Bulk Erase (BE) command completion Figure 9.5 Write Disable (WRDI) Command Sequence
CS#
Mode 3
01234567
SCK Mode 0
Command
SI
Hi-Z SO
9.6
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.2 shows the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, or Write Status Register operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress. Figure 9.6 shows the RDSR command sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. Table 9.2 S25FL016A Status Register
Bit 7 6 5 4 3 2 1 Status Register Bit SRWD — — BP2 BP1 BP0 WEL Write Enable Latch 1 = Device accepts Write Status Register, program, or erase commands 0 = Ignores Write Status Register, program, or erase commands 0 WIP Write in Progress 1 = Device Busy. A Write Status Register, program, or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands. Block Protect 000–111 = Protects upper half of address range in 5 sizes. See Table 7.1 on page 13. Bit Function Status Register Write Disable — — Description 1 = Protects when W# is low 0 = No protection, even when W# is low Not used Not used
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Figure 9.6 Read Status Register (RDSR) Command Sequence
CS#
Mode 3
01
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Mode 0
Command SI
SO
Hi-Z
76543210765432107
MSB
Status Register Out
MSB
Status Register Out
The following describes the status and control bits of the Status Register. Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register, program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such operation is in progress. Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program, or erase operation. WEL cannot be directly set by the WRSR command. Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see Table 7.1 on page 13) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the device ignores any Write Status Register (WRSR) command.
9.7
Write Status Register (WRSR)
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRSR command. Table 9.2, S25FL016A Status Register on page 19 shows the status register bits and their functions. The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI (Figure 9.7). The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always read as 0 and have no user significance. The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR commands once it enters the Hardware Protected Mode (HPM). Table 9.3 on page 21 shows that W# must be driven low and the SRWD bit must be 1 for this to occur.
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Figure 9.7 Write Status Register (WRSR) Command Sequence
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK Mode 0 Command
Status Register In
SI Hi-Z
7 MSB
6
5
4
3
2
1
0
SO
Table 9.3 Protection Modes
W# Signal 1 1 0 0 SRWD Bit 1 0 0 1 Mode Software Protected (SPM) Hardware Protected (HPM) Write Protection of the Status Register Status Register is writable (if the WREN command has set the WEL bit). The values in the SRWD, BP2, BP1 and BP0 bits can be changed. Status Register is Hardware write protected. The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed. Protected Area (See Note) Protected against program and erase commands Unprotected Area (See Note) Ready to accept Page Program and Sector Erase commands Ready to accept Page Program and Sector Erase commands
Protected against program and erase commands
Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 13.
Table 9.3 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit. However, the device disables HPM only when W# is driven high. Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM). If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be used.
9.8
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the PP command, three address bytes, and at least one data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence is shown in Figure 9.8 and Table 9.4 on page 25. The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256 bytes sent at the starting address of the specified page. This may result in data being programmed into different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses. The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tPP. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page 13).
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Figure 9.8 Page Program (PP) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
39
SCK
Mode 0
Command
24-Bit Address 23 22 21 MSB 3 2 1 0 7 6 5
Data Byte 1 4 3 2 1 0
SI
MSB
2072
2074
2075
2073
2076
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2077
2078
1 0
SCK
Data Byte 2 Data Byte 3 1 0 7 6 5 4 3 2 1 0 7 MSB 6 Data Byte 256 5 4 3 2
SI
7 MSB
6
5
4
3
2
MSB
9.9
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see Table 7.1 on page 13) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.9 and Table 9.4 on page 25. The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute an SE command that specifies a sector that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page 13). Figure 9.9 Sector Erase (SE) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
SCK
Mode 0
Command
24-bit Address
23
MSB
SI
Hi-Z
22
21
3
2
1
0
SO
22
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9.10
Bulk Erase (BE)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the entire duration of the BE sequence. The command sequence is shown in Figure 9.10 and Table 9.4 on page 25. The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise the device does not execute the command. The BE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tBE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1 on page 13). Otherwise, the device ignores the command. Figure 9.10 Bulk Erase (BE) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
SI SO
Hi-Z
9.11
Deep Power Down (DP)
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when the device is not in active use, and ignores all commands except for the Release from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection against unintended write operations. The standard standby mode, which the device goes into automatically when CS# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the entire duration of the DP sequence. The command sequence is shown in Figure 9.11 and Table 9.4 on page 25. The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise the device does not execute the command. After a delay of tDP, the device enters the DP mode and current reduces from ISB to IDP (see Table 14.1 on page 28). Once the device has entered the DP mode, all commands are ignored except the RES command (which releases the device from the DP mode). The RES command also provides the Electronic Signature of the device to be output on SO, if desired (see Section 9.12 and 9.12.1). DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted.
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Figure 9.11 Deep Power Down (DP) Command Sequence
CS#
tDP
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
SI
Hi-Z
SO
Standby Mode
Deep Power-down Mode
9.12
Release from Deep Power Down (RES)
The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the Deep Power Down mode, all commands except RES are ignored. The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire duration of the sequence. The command sequence is shown in Figure 9.12 and Table 9.4 on page 25. The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions from DP mode to the standby mode after a delay of tRES (see Table 16.1 on page 29). In the standby mode, the device can execute any read or write command. Figure 9.12 Release from Deep Power Down (RES) Command Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Command
tRES
SI
Hi-Z
SO
Deep Power-down Mode
Standby Mode
24
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9.12.1
Release from Deep Power Down and Read Electronic Signature (RES)
The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.13 and Table 9.4 on page 25 for the command sequence and signature value. The Electronic Signature is not to be confused with the identification data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead. After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to output the Electronic Signature repeatedly. When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as previously described. The RES command always provides access to the Electronic Signature of the device and can be applied even if DP mode has not been entered. Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the operation continues uninterrupted. Figure 9.13 Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SCK
Command
3 Dummy Bytes
tRES
1 0
SI SO
Hi-Z
23 22 21
MSB
3
2
7
MSB
6
5
4
3
2
1
0
Electronic ID out
Deep Power-down Mode
Standby Mode
Table 9.4 Command Definitions
Operation Command READ Read FAST_READ RDID WREN Write Control WRDI SE Erase BE Program Status Register PP RDSR WRSR DP Power Saving RES Bulk (Chip) Erase Page Program Read from Status Register Write to Status Register Deep Power Down Release from Deep Power Down Release from Deep Power Down and Read Electronic Signature (Note 2) C7H (1100 0111) 02H (0000 0010) 05H (0000 0101) 01H (0000 0001) B9H (1011 1001) ABH (1010 1011) ABH (1010 1011) 0 3 0 0 0 0 0 0 0 0 0 0 0 3 0 1 to 256 1 to ∞ 1 0 0 1 to ∞ Write Disable Sector Erase 04H (0000 0100) D8H (1101 1000) 0 3 0 0 0 0 Description Read Data Bytes Read Data Bytes at Higher Speed Read Identification (Note 1) Write Enable One-Byte Command Code 03H (0000 0011) 0BH (0000 1011) 9FH (1001 1111) 06H (0000 0110) Address Bytes 3 3 0 0 Dummy Byte 0 1 0 0 Data Bytes 1 to ∞ 1 to ∞ 1 to 3 0
Notes 1. The S25FL016A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (14h). 2. The S25FL016A has an Electronic Signature ID of 14h.
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10. Power-up and Power-down
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows (see Figure 10.1 and Table 10.1 on page 26): At power-up, VCC (min) plus a period of tPU At power-down, VSS A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements. No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the WEL bit is reset (0). Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed. When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all operations are disabled and the device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Register, program, or erase operation is in progress. Figure 10.1 Power-Up Timing Diagram
Vcc
(max)
Vcc
Vcc
(min)
t PU
Full Device Access
Time
Table 10.1 Power-Up Timing Characteristics
Symbol VCC(min) tPU Parameter VCC (minimum) VCC (min) to device operation Min 2.7 10 Max Unit V ms
11. Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status Register contains 00h (all Status Register bits are 0).
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12. Absolute Maximum Ratings
Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond those indicated in this section and in the Operating Ranges section of this document is not implied. Device operation for extended periods at the limits listed in this section may affect device reliability. Table 12.1 Absolute Maximum Ratings
Description Ambient Storage Temperature Voltage with Respect to Ground: All Inputs and I/Os Rating –65°C to +150°C –0.5 V to VCC+0.5 V
Notes 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 12.2. Maximum DC voltage on output and I/O pins is 3.6 V. During voltage transitions output pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 12.2. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 12.1 Maximum Negative Overshoot Waveform
20 ns +0.8 V –0.5 V –2 V 20 ns 20 ns
Figure 12.2 Maximum Positive Overshoot Waveform
20 ns V CC +2.0 V V CC +0.5 V 2.0 V 20 ns 20 ns
13. Operating Ranges
Table 13.1 Operating Ranges
Description Ambient Operating Temperature (TA) Positive Power Supply Industrial Voltage Range Rating –40°C to +85°C 2.7 V to 3.6 V
Note Operating ranges define those limits between which functionality of the device is guaranteed.
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14. DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 15.1 on page 28, when relying on the quoted parameters. Table 14.1 DC Characteristics (CMOS Compatible)
Parameter VCC ICC1 ICC2 ICC3 ICC4 ICC5 ISB IDP ILI ILO VIL VIH VOL VOH Description Supply Voltage SCK = 0.1 VCC/0.9VCC Active Read Current SCK = 0.1 VCC/0.9VCC Active Page Program Current Active WRSR Current Active Sector Erase Current Active Bulk Erase Current Standby Current Deep Power Down Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA, VCC = VCC min IOH = –0.1 mA VCC – 0.2 CS# = VCC CS# = VCC CS# = VCC CS# = VCC VCC = 3.0 V CS# = VCC VCC = 3.0 V CS# = VCC VIN = GND to VCC VIN = GND to VCC –0.3 0.7 VCC 21 1.3 33 MHz VCC = 3.0V 50 MHz Test Conditions (See Note) Min 2.7 Typ. 3 9 14 17.5 Max 3.6 12 19 28 24 24 24 50 5 1 1 0.3 VCC VCC + 0.5 0.4 Unit V mA mA mA mA mA mA µA µA µA µA V V V V
Note Typical values are at TA = 25°C and 3.0 V.
15. Test Conditions
Figure 15.1 AC Measurements I/O Waveform
0.8 VCC Input Levels 0.2 VCC Input and Output Timing Reference levels 0.7 VCC 0.5 VCC 0.3 VCC
Table 15.1 Test Specifications
Symbol CL Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage Min 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC 0.5 VCC Max Unit pF ns V V V
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16. AC Characteristics
Table 16.1 AC Characteristics
Symbol (Notes) FSCK FSCK tCRT tCFT tWH tWL tCS tCSS (3) tCSH (3) tHD (3) tCD (3) tHC tCH tV tHO tHD:DAT tSU:DAT tR tF tLZ (3) tHZ (3) tDIS (3) tWPS (3) tWPH (3) tW tDP tRES tPP tSE tBE Parameter SCK Clock Frequency READ command SCK Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock Rise Time (Slew Rate) Clock Fall Time (Slew Rate) SCK High Time SCK Low Time CS# High Time CS# Setup Time CS# HOLD Time HOLD# Setup Time (relative to SCK) HOLD# Hold Time (relative to SCK) HOLD# Setup Time (relative to SCK) HOLD# Hold Time (relative to SCK) Output Valid Output Hold Time Data in Hold Time Data in Setup Time Input Rise Time Input Fall Time HOLD# to Output Low Z HOLD# to Output High Z Output Disable Time Write Protect Setup Time Write Protect Hold Time Write Status Register Time CS# High to Deep Power Down Mode Release DP Mode Page Programming Time Sector Erase Time Bulk Erase Time 1.4 (1) 0.5 (1) 10 (1) 15 15 67 150 3 30 3 (2) 3 (2) 96 (2) 0 5 5 5 5 10 10 10 Min D.C. D.C. 0.1 0.1 9 9 100 5 5 5 5 5 5 10 Typ (Notes) Max (Notes) 33 50 Unit MHz MHz V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms μs μs ms sec sec
Notes 1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern 2. Under worst-case conditions of 90°C; VCC = 2.7V; 100,000 cycles 3. Not 100% tested
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Figure 16.1 SPI Mode 0 (0,0) Input Timing
CS# tCS
tCSH SCK
tCSS
tCSH
tCSS
tSU:DAT tHD:DAT SI MSB IN
tCRT
tCFT LSB IN
SO
Hi-Z
Figure 16.2 SPI Mode 0 (0,0) Output Timing
CS#
tWH
SCK
tV tHO tHO LSB OUT tV tWL tDIS
SO
Figure 16.3 HOLD# Timing
CS#
tCH tHD tHC
SCK
tCD tHZ tLZ
SO
SI
HOLD#
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Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1
W#
tWPS tWPH
CS#
SCK
SI
SO
Hi-Z
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17. Physical Dimensions
17.1 SOC008 wide—8-pin Plastic Small Outline Package (208 mils Body Width)
3 D A 5 4 0.20 C D A-B H SEE DETAIL B WITH PLATING
9
b1
3 E1
4
c E (b) 7 SECTION A-A 0.33 C A-B D H
c1
E1/2
E/2
BASE METAL
e B 5
b 0.25 M C 0.10 C
q2 0.07 R MIN. GAUGE PLANE A q1 L L1 DETAIL B A q SEATING PLANE L2
A
A2
0.10 C SEATING PLANE A1 C C
NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N θ θ1 θ2 0˚ 5˚ 0˚ MIN 0.069 0.002 0.067 0.014 0.013 0.0075 0.006 MAX 0.085 0.0098 0.075 0.019 0.018 0.0095 0.008 MIN 1.753 0.051 1.70 0.356 0.330 0.191 0.152 MAX 2.159 0.249 1.91 0.483 0.457 0.241 0.203 5. 6. 7. 8. 4. . SOC 008 (inches) SOC 008 (mm) 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
0.208 BSC 0.315 BSC 0.208 BSC .050 BSC 0.020 0.030
5.283 BSC 8.001 BSC 5.283 BSC 1.27 BSC 0.508 0.762
.055 REF .010 BSC 8 8˚ 15˚
1.40 REF 0.25 BSC 8 0˚ 5˚ 0˚ 8˚ 15˚
9.
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 3432 \ 16-038.03 \ 10.28.04
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17.2
SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width)
NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N h θ θ1 θ2 0.10 0˚ 5˚ 0˚ SO3 016 (inches) MS-013(D)AA MIN 0.093 0.004 0.081 0.012 0.011 0.008 0.008 MAX 0.104 0.012 0.104 0.020 0.019 0.013 0.012 SO3 016 (mm) MS-013(D)AA MIN 2.35 0.10 2.05 0.31 0.27 0.20 0.20 MAX 2.65 0.30 2.55 0.51 0.48 0.33 0.30 5. 6. 7. 8. 4. . 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE.
3601 \ 16-038.03 \ 8.31.6
0.406 BSC 0.406 BSC 0.295 BSC .050 BSC 0.016 0.050
10.30 BSC 10.30 BSC 7.50 BSC 1.27 BSC 0.40 1.27
.055 REF .010 BSC 16 0.30 8˚ 15˚
1.40 REF 0.25 BSC 16 0.25 0˚ 5˚ 0˚ 0.75 8˚ 15˚
9.
10.
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17.3
WSON 8-contact (6 x 8 mm) No-Lead Package
D N A B (DATUM A) PIN #1 ID R0.20 1 2 D2 D2/2 NX L
E2/2 9. E E2
0.30 DIA TYP. 8.
2X
0.10 C 1 2X 0.10 C 0.10 C 9. 0.05 C SEATING PLANE A C 2
TOP VIEW
N
N-1
K NX b 4. 0.10 M C A B . e 0.05 M C . SEE DETAIL "A"
e (ND-1) X 5. A1
SIDE VIEW
DATUM A
BOTTOM VIEW
L e/2
L1 10. TERMINAL TIP e 4.
DETAIL "A"
NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. MAX NOTE 2. ALL DIMENSIONS ARE IN MILLIMETERS, SYM θ IS IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 3 5 0.55 0.45 4.90 6.50 4 4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. 6. 7. 8. 0.80 0.05 10 12 2 9. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. PIN #1 ID ON TOP WILL BE LASER MARKED. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
QUAD FLAT NO LEAD PACKAGES (WSNB) - PLASTIC DIMENSIONS SYMBOL e N ND L b D2 E2 D E A A1 L1 θ K 0 0.70 0.00 0.45 0.35 4.70 6.30 MIN NOM 1.27 BSC 8 4 0.50 0.40 4.80 6.40 6.00 BSC 8.00 BSC 0.75 0.02 0.15 MAX. --0.20 MIN.
10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT.
3408\ 16-038.28a
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18. Revision History
Section Revision A (July 13, 2004) Global Revision A1 (September 13, 2004) Connection Diagrams Ordering Information Table Revision A2 (December 16, 2004) Read Identification (RDID) Revision A3 (March 3, 2005) Ordering Information Read Identification (RDID) Revision A4 (March 29, 2005) DC Characteristics Global Revision A5 (June 21, 2005) Distinctive Characteristics Ordering Information Valid Combination Table Power-up and Power-down section DC Characteristics AC Characteristics Revision A6 (December 21, 2005) Global Ordering Information Valid Combination Table Revision B0 (April 18, 2005) Global AC Characteristics table Revision B1 (June 29, 2006) DC Characteristics Revision C0 (August 28, 2006) Global Revision C1 (February 16, 2007) Global Absolute Maximum Ratings Revision C2 (June 29, 2007) Device Operations Revision C3 (January 7, 2008) Ordering Information Added Tray packing option for 8-pin and 16-pin SOIC packages. Added sentence to Byte or Page Programming Deleted Preliminary status from document. Added overshoot and undershoot information. Rewrote entire document for better flow and clarity. No specifications were changed. Changed typical and maximum specifications for ICC2. Changed document status from Advance Information to Preliminary. Changed title from family of devices to specific device. Updated tW specifications. Added 8-pin SO package to Distinctive Characteristics, Connection Diagram, and Ordering Information, and Physical Dimensions sections. Added Tray to packing type. Updated. Updated Page Program speed. Update Deep Power Down Mode time. Update timing numbers. Added Tray to packing type. Updated Packing Type. Updated this section. Removed Figure 19. Updated Table 7 Power-up Timing. Added and updated values in Table 8. Updated Figure 21. Updated table. Removed Commercial temperature range. Added new commercial temperature range. Updated package and temperature, and package marking information. Added note on standard package A and Pb-free package F information. Updated memory capacity of the device in the second byte from 15h to 14h. Changed memory capacity of the device in the second byte from 14h to 15h. Added the WSON 6x8mm pin out. Changed OPN to reflect Device technology identification change from M to A for CS99S MirrorBit technology. Initial release. Description
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Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004-2008 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
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