S25FL040A0LNAI013

S25FL040A 4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage S25FL040A Cover Sheet Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S25FL040A_00 Revision B0 Issue Date August 31, 2006 Data Sheet (Preliminary) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. ii S25FL040A S25FL040A_00_B0 August 31, 2006 S25FL040A 4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage Data Sheet (Preliminary) Distinctive Characteristics Architectural Advantages Single power supply operation – Full voltage range: 2.7 to 3.6 V read and program operations Process Technology – Manufactured on 0.20 µm MirrorBitTM process technology Package Option – – – – Industry Standard Pinouts 8-pin SO package (150 mils) 8-pin SO package (208 mils) 8-Contact WSON Package (5 x 6 mm) Memory Architecture – 4Mb uniform 64KB sector product: Backward compatible with S25FL004A 4Mb device; same pin out, command set and uniform sector size (64KB) – 4Mb small sector product: Offer Top Boot & Bottom Boot devices; Seven sectors of 64KB and One 64KB sector (Top or bottom) broken into two sectors of 16KB each, two sectors of 4KB each, and two sectors of 12KB each. Performance Characteristics Speed – 50 MHz clock rate (maximum) Program – Page Program (up to 256 bytes) in 1.5 ms (typical) – Program operations are on a page by page basis Power Saving Standby Mode – Standby Mode 20 µA (max) – Deep Power Down Mode 1.5 µA (typical) Erase – 0.5 s typical sector erase time – 3 s typical bulk erase time Memory Protection Features Memory Protection – W# pin works in conjunction with Status Register Bits to protect specified memory areas – Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only Cycling Endurance – 100,000 cycles per sector typical Data Retention – 20 years typical Device ID – JEDEC standard two-byte electronic signature – RES command one-byte electronic signature for backward compatibility Software Features – SPI Bus Compatible Serial Interface Publication Number S25FL040A_00 Revision B0 Issue Date August 31, 2006 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Data Sheet (Preliminary) General Description The S25FL040A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device with with erasable sectors for boot code and parameter storage. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0 volt VCC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require a VPP supply. The S25FL040A device in uniform 64KB sector configuration is compatible with the S25FL004A device. 2 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2. 3. 4. 5. 6. 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 10 10 10 12 8. 9. Sector Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.1 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.4 Read Identification (Read_ID) [RDID Alternate] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.5 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.6 Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.7 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.8 Write Status Register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.9 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.10 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.11 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.12 Deep Power Down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.13 Release from Deep Power Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.13.1 Release from Deep Power Down and Read Electronic Signature (RES) . . . . . . . . . .24 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 SOA 008—Narrow 8-pin Plastic Small Outline 150 mils Body Width Package . . . . . . . . . . . 17.2 SOC 008—Wide 8-pin Plastic Small Outline 208 mils Body Width Package. . . . . . . . . . . . . 17.3 USON 8L (5 x 6 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 32 33 10. 11. 12. 13. 14. 15. 16. 17. 18. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 August 31, 2006 S25FL040A_00_B0 S25FL040A 3 Data Sheet (Preliminary) List of Figures Figure 2.1 Figure 2.2 Figure 6.1 Figure 6.2 Figure 7.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 10.1 Figure 15.1 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 8-pin Plastic Small Outline Package (SO 150 mil, SO 208 mil) . . . . . . . . . . . . . . . . . . . . . . . . 6 8L USON (5 x 6 mm) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 15 Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 16 READ_ID Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Deep Power Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Release from Deep Power Down (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 24 Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 30 List of Tables Table 5.1 Table 7.1 Table 7.2 Table 7.3 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 10.1 Table 12.1 Table 13.1 Table 14.1 Table 15.1 Table 16.1 S25FL040A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 S25FL040A Protected Area Sizes (Top Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 S25FL040A Protected Area Sizes (Bottom Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 S25FL040A Protected Area Sizes (Uniform Sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 S25FL040A Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Sector Address Table - S25FL040A (Top Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Sector Address Table - S25FL040A (Bottom Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 S25FL040A Sector Address Table (Uniform Sectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 READ_ID Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 S25FL040A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 1. Block Diagram SRAM PS Array - L Logic X D E C Array - R RD DATA PATH IO SI SCK SO GND HOLD# CS# VCC August 31, 2006 S25FL040A_00_B0 S25FL040A 5 Data Sheet (Preliminary) 2. Connection Diagrams Figure 2.1 8-pin Plastic Small Outline Package (SO 150 mil, SO 208 mil) CS# SO W# GND 1 2 3 4 8 7 6 5 VCC HOLD# SCK SI Figure 2.2 8L USON (5 x 6 mm) Package CS# SO W# GND 1 2 3 4 8 7 6 5 VCC HOLD# SCK SI 6 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 3. Input/Output Descriptions Signal Name SO (Signal Data Output) SI (Serial Data Input) SCK (Serial Clock) I/O Output Input Input Description Transfers data serially out of the device on the falling edge of SCK. Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Supply Voltage Ground CS# (Chip Select) Input HOLD# (Hold) Input W# (Write Protect) VCC GND Input Input Input 4. Logic Symbol VCC SI SCK CS# W# HOLD# SO GND August 31, 2006 S25FL040A_00_B0 S25FL040A 7 Data Sheet (Preliminary) 5. Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 040 A 0L M A I 00 1 PACKING TYPE (Note 1) 0 = Tray 1 = Tube 3 = 13” Tape and Reel MODEL NUMBER (Additional Ordering Options) 00 = 64 KBytes Uniform Sector 01 = Top Boot Sector 02 = Bottom Boot Sector TEMPERATURE RANGE I = Industrial (–40°C to + 85°C) PACKAGE MATERIALS A = Standard F = Lead (Pb)-free PACKAGE TYPE V = 8-Pin Plastic Small Outline Package (150 mil) M = 8-Pin Plastic Small Outline Package (208 mil) N = 8-contact WSON Package SPEED 0L = 50 MHz DEVICE TECHNOLOGY A = 0.20 µm MirrorBit™ Process Technology DENSITY 040 = 4 Mbit DEVICE FAMILY S25FL SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL040A Valid Combinations Table S25FL040A Valid Combinations Base Ordering Part Number S25FL040A Speed Option 0L Package & Temperature Model Number MAI, MFI, VAI, VFI, NAI, NFI 00, 01, 02 Packing Type 0, 1, 3 (Note 1) Package Marking (Note 2) FL040A + (Note 3) + (Note 4) Notes 1. Contact your local sales office for availability. 2. Package marking omits leading “S25” and speed, package, and model number form. 3. A for standard package (non-Pb free); F for Pb-free package. 4. I for Uniform Sector product; T for Top Boot product; B for Bottom Boot product. 5.1 Valid Combinations Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. 8 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 6. Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes. When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes: SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0) SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3) Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master SI SCK SCK SO SI SCK SO SI SCK SO SI SPI Memory Device CS3 CS2 CS1 CS# W# HOLD# SPI Memory Device SPI Memory Device CS# W# HOLD# CS# W# HOLD# Note The Write Protect (W#) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. Figure 6.2 SPI Modes Supported CS# CPOL CPHA Mode 0 Mode 3 0 1 0 1 SCK SCK SI SO MSB MSB August 31, 2006 S25FL040A_00_B0 S25FL040A 9 Data Sheet (Preliminary) 7. Device Operations All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time). 7.1 Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation. 7.2 Sector Erase / Bulk Erase The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level. 7.3 Monitoring Write Operations Using the Status Register The host system can determine when a Write Status Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. 7.4 Active Power and Standby Power Modes The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status Register operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to IDP. 7.5 Status Register The Status Register contains the status and control bits that can be read or set by specific commands (Table 9.3, S25FL040A Status Register on page 18): Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected against program and erase commands. Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. 7.6 Data Protection Modes Spansion SPI Flash memory devices provide the following data protection methods: The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – Page Program (PP) – Sector Erase (SE) – Bulk Erase (BE) 10 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) – Write Disable (WRDI) – Write Status Register (WRSR) Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not programmed or erased. Table 7.1 and Table 7.2 show the sizes and address ranges of protected areas that are defined by Status Register bits BP2:BP0. Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable (SRWD) bit together provide write protection. Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands consist of a clock pulse count that is a multiple of eight before executing them. Table 7.1 S25FL040A Protected Area Sizes (Top Boot) Status Register Block Protect Bits BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Address Range None 7C000–7FFFF 78000–7FFFF 70000–7FFFF 60000–7FFFF 40000–7FFFF 00000–7FFFF 00000–7FFFF Memory Array Protected Sectors (0) None (1) SA12 (2) SA12:SA11 (6) SA12:SA7 (7) SA12:SA6 (9) SA12:SA4 (13) SA12:SA0 (13) SA12:SA0 Unprotected Address Range 00000–7FFFF 00000–7BFFF 00000–77FFF 00000–6FFFF 00000–5FFFF 00000–3FFFF None None Unprotected Sectors SA12:SA0 SA11:SA0 SA10:SA0 SA6:SA0 SA5:SA0 SA3:SA0 None None Protected Portion of Total Memory Area None (0) Upper 1/32 (16 KB) Upper 1/16 (32 KB) Upper 1/8 (64 KB) Upper 1/4 (128 KB) Upper 1/2 (256 KB) All (512 KB) All (512 KB) Table 7.2 S25FL040A Protected Area Sizes (Bottom Boot) Status Register Block Protect Bits BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Address Range None 00000–03FFF 00000–07FFF 00000–0FFFF 00000–1FFFF 00000–3FFFF 00000–7FFFF 00000–7FFFF Memory Array Protected Sectors (0) (1) SA0 (2) SA1:SA0 (6) SA5:SA0 (7) SA6:SA0 (9) SA8:SA0 (13) SA12:SA0 (13) SA12:SA0 Unprotected Address Range 00000–7FFFF 04000–7FFFF 08000–7FFFF 10000–7FFFF 20000–7FFFF 40000–7FFFF None None Unprotected Sectors SA12:SA0 SA12:SA1 SA12:SA2 SA12:SA4 SA12:SA5 SA12:SA7 None None Protected Portion of Total Memory Area 0 Lower 1/32 (16 KB) Lower 1/16 (32 KB) Lower 1/8 (64 KB) Lower 1/4 (128 KB) Lower 1/2 (256 KB) All (512 KB) All (512 KB) August 31, 2006 S25FL040A_00_B0 S25FL040A 11 Data Sheet (Preliminary) Table 7.3 S25FL040A Protected Area Sizes (Uniform Sector) Status Register Block Protect Bits BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Address Range None 70000–7FFFF 60000–7FFFF 40000–7FFFF 00000–7FFFF 00000–7FFFF 00000–7FFFF 00000–7FFFF Memory Array Protected Sectors (0) (1) SA7 (2) SA7:SA6 (4) SA7:SA4 (8) SA7:SA0 (8) SA7:SA0 (8) SA7:SA0 (8) SA7:SA0 Unprotected Address Range 00000–7FFFF 00000–6FFFF 00000–5FFFF 00000–3FFFF None None None None Unprotected Sectors SA7:SA0 SA6:SA0 SA5:SA0 SA3:SA0 None None None None Protected Portion of Total Memory Area 0 Upper 1/8 (64 KB) Lower 1/4 (128 KB) Lower 1/2 (256 KB) All (512 KB) All (512 KB) All (512 KB) All (512 KB) 7.7 Hold Mode (HOLD#) The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write Status Register, program or erase operation that is currently in progress. The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, on page 12, standard use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of SCK (non-standard use). The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (nonstandard use) See Figure 7.1. The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the Hold mode. CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. Figure 7.1 Hold Mode Operation SCK HOLD# Hold Condition (standard use) Hold Condition (non-standard use) 12 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 8. Sector Address Table Table 8.1 shows the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sector- or device-wide basis using the SE or BE commands. Table 8.4 shows the starting and ending address for each sector. The complete set of sectors comprises the memory array of the Flash device. Table 8.1 S25FL040A Device Organization Each Device has Each Sector has 65,536 (64 KB sector) 16,384 (16 KB sector) 12,288 (12 KB sector) 4,096 (4 KB sector) 256 (64 KB sector) 64 (16 KB sector) 48 (12 KB sector) 16 (4 KB sector) — Each Page has 524,288 256 bytes 2,048 — pages 12 (boot), 7 (uniform) — sectors Table 8.2 Sector Address Table - S25FL040A (Top Boot) Sector SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Size 16K Byte 16K Byte 4K Byte 4K Byte 12K Byte 12K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 7C000h 78000h 77000h 76000h 73000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h Address Range 7FFFFh 7BFFFh 77FFFh 76FFFh 75FFFh 72FFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh Table 8.3 Sector Address Table - S25FL040A (Bottom Boot) Sector SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Size 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 64K Byte 12K Byte 12K Byte 4K Byte 4K Byte 16K Byte 16K Byte 70000h 60000h 50000h 40000h 30000h 20000h 10000h 0D000h 0A000h 09000h 08000h 04000h 00000h Address Range 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh 0CFFFh 09FFFh 08FFFh 07FFFh 03FFFh August 31, 2006 S25FL040A_00_B0 S25FL040A 13 Data Sheet (Preliminary) Table 8.4 S25FL040A Sector Address Table (Uniform Sectors) Sector SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h Address Range 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh 9. Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on the rising edge of SCK. Table 9.5 on page 24 lists the complete set of commands. Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. The Read Data Bytes (READ), Read Status Register (RDSR), Read Data Bytes at Higher Speed (FAST_READ) and Read Identification (RDID) command sequences are followed by a data output sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation. The Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of eight. The device ignores any attempt to access the memory array during a Write Status Register, program, or erase operation, and continues the operation uninterrupted. 9.1 Read Data Bytes (READ) The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 33 MHz. The host system must first select the device by driving CS# low. The READ command is then written to SI, followed by a 3-byte address (A23-A0). Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. Figure 9.1 and Table 9.5 detail the READ command sequence. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The READ command is terminated by driving CS# high at any time during data output. The device rejects any READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. 14 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 9.1 Read Data Bytes (READ) Command Sequence CS# Mode 3 0 1 23 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Mode 0 Command 24-Bit Address SI 23 22 21 MSB 3210 Data Out 1 Data Out 2 SO Hi-Z 765432 MSB 107 9.2 Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# low. The FAST_READ command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. The FAST_READ command sequence is shown in Figure 9.2 and Table 9.5. The first byte specified can be at any location. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The FAST_READ command is terminated by driving CS# high at any time during data output. The device rejects any FAST_READ command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS# Mode 3 0 1 2 5 6 7 8 9 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 3 4 10 47 SCK Mode 0 Command SI SO Hi-Z 24-Bit Address 23 22 21 3 2 1 0 7 Dummy Byte 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB DATA OUT 2 DATA OUT 1 9.3 Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification, to the host system. JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer assigns the device identification: the first byte provides the memory type; the second byte indicates the memory capacity. See Table 9.1 or Table 9.5 for device ID data. The host system must first select the device by driving CS# low. The RDID command is then written to SI, and each bit is latched on the rising edge of SCK. The 24-bit device identification data is output from the memory array on SO at a frequency fSCK, on the falling edge of SCK. August 31, 2006 S25FL040A_00_B0 S25FL040A 15 Data Sheet (Preliminary) The RDID command sequence is shown in Figure 9.3 and Table 9.5. Driving CS# high after the device identification data has been read at least once terminates the READ_ID command. Driving CS# high at any time during data output also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence CS# SCK Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 Mode 0 Command SI Manufacturer Identification SO Hi-Z MSB Device Identification 15 14 13 3 2 1 0 Table 9.1 READ_ID Data Data Address Manufacturer Identification Device Identification (Memory Capacity) 00000h 00001h Uniform 01h 12h Top Boot 01h 25h Bottom Boot 01h 26h 9.4 Read Identification (Read_ID) [RDID Alternate] The READ_ID instruction provides the S25FL040A manufacturer and device information. This command should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The device information can be read from by writing the 8-bit command (90H) follwed by address bits. Following the READ_ID instruction, the manufacturer’s ID is located at address 00000H and the device ID (Memory Capacity) is located at address 00001H. Once the device is in READ_ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until CE# is driven high. 16 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 9.4 READ_ID Command Timing Diagram CS# 0 SCK Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI 23 22 21 MSB 3 2 1 0 Manufacture Identification Device Identification High Impedance SO 7 6 5 4 3 2 1 0 Table 9.2 READ_ID Data-Out Sequence Data Address Manufacturer Identification Device Identification (Memory Capacity) 00000h 00001h Uniform 01h 12h Top Boot 01h 25h Bottom Boot 01h 26h 9.5 Write Enable (WREN) The Write Enable (WREN) command (see Figure 9.5) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. Figure 9.5 Write Enable (WREN) Command Sequence CS# Mode 3 01 23 4567 SCK Mode 0 Command SI Hi-Z SO 9.6 Write Disable (WRDI) The Write Disable (WRDI) command (see Figure 9.6) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a Write Status Register, program, or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high. Any of following conditions resets the WEL bit: Power-up August 31, 2006 S25FL040A_00_B0 S25FL040A 17 Data Sheet (Preliminary) Write Disable (WRDI) command completion Write Status Register (WRSR) command completion Page Program (PP) command completion Sector Erase (SE) command completion Bulk Erase (BE) command completion Figure 9.6 Write Disable (WRDI) Command Sequence CS# Mode 3 01234567 SCK Mode 0 Command SI Hi-Z SO 9.7 Read Status Register (RDSR) The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.3 shows the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, or Write Status Register operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress. Figure 9.7 shows the RDSR command sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. Table 9.3 S25FL040A Status Register Bit 7 6 5 4 3 2 1 Status Register Bit SRWD — — BP2 BP1 BP0 WEL Write Enable Latch 1 = Device accepts Write Status Register, program, or erase commands 0 = Ignores Write Status Register, program, or erase commands 0 WIP Write in Progress 1 = Device Busy. A Write Status Register, program, or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands. Block Protect 000–111 = Protects upper half of address range in 5 sizes. See Table 7.1. Bit Function Status Register Write Disable — — Description 1 = Protects when W# is low 0 = No protection, even when W# is low Not used Not used 18 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 9.7 Read Status Register (RDSR) Command Sequence CS# Mode 3 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Mode 0 Command SI SO Hi-Z 76543210765432107 MSB Status Register Out MSB Status Register Out The following describes the status and control bits of the Status Register. Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register, program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such operation is in progress. Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program, or erase operation. WEL cannot be directly set by the WRSR command. Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see Table 7.1 on page 11) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the device ignores any Write Status Register (WRSR) command. 9.8 Write Status Register (WRSR) The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRSR command. Table 9.3, S25FL040A Status Register on page 18 shows the status register bits and their functions. The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI (Figure 9.8). The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always read as 0 and have no user significance. The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR commands once it enters the Hardware Protected Mode (HPM). Table 9.4 shows that W# must be driven low and the SRWD bit must be 1 for this to occur. August 31, 2006 S25FL040A_00_B0 S25FL040A 19 Data Sheet (Preliminary) Figure 9.8 Write Status Register (WRSR) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Mode 0 Command Status Register In SI Hi-Z 7 MSB 6 5 4 3 2 1 0 SO Table 9.4 Protection Modes W# Signal 1 1 0 0 SRWD Bit 1 0 0 1 Mode Software Protected (SPM) Hardware Protected (HPM) Write Protection of the Status Register Status Register is writable (if the WREN command has set the WEL bit). The values in the SRWD, BP2, BP1 and BP0 bits can be changed. Status Register is Hardware write protected. The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed. Protected Area (See Note) Protected against program and erase commands Unprotected Area (See Note) Ready to accept Page Program and Sector Erase commands Ready to accept Page Program and Sector Erase commands Protected against program and erase commands Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 11. Table 9.4 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit. However, the device disables HPM only when W# is driven high. Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM). If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be used. 9.9 Page Program (PP) The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the PP command, three address bytes, and at least one data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence is shown in Figure 9.9 and Table 9.5. The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256 bytes sent at the starting address of the specified page. This may result in data being programmed into different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses. The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tPP. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page 11). 20 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 9.9 Page Program (PP) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Mode 0 Command 24-Bit Address 23 22 21 MSB 3 2 1 0 7 6 5 Data Byte 1 4 3 2 1 0 SI MSB 2072 2074 2075 2073 2076 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2077 2078 1 0 SCK Data Byte 2 Data Byte 3 1 0 7 6 5 4 3 2 1 0 7 MSB 6 Data Byte 256 5 4 3 2 SI 7 MSB 6 5 4 3 2 MSB 9.10 Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see Table 7.1 on page 11) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.10 and Table 9.5. The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute an SE command that specifies a sector that is protected by the Block Protect bits (BP2:BP0) (see Table 7.1 on page 11). Figure 9.10 Sector Erase (SE) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCK Mode 0 Command 24-bit Address 23 MSB SI Hi-Z 22 21 3 2 1 0 SO August 31, 2006 S25FL040A_00_B0 S25FL040A 2079 21 Data Sheet (Preliminary) 9.11 Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the entire duration of the BE sequence. The command sequence is shown in Figure 9.11 and Table 9.5. The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise the device does not execute the command. The BE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tBE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1 on page 11). Otherwise, the device ignores the command. Figure 9.11 Bulk Erase (BE) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI SO Hi-Z 9.12 Deep Power Down (DP) The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when the device is not in active use, and ignores all commands except for the Release from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection against unintended write operations. The standard standby mode, which the device goes into automatically when CS# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the entire duration of the DP sequence. The command sequence is shown in Figure 9.12 and Table 9.5. The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise the device does not execute the command. After a delay of tDP, the device enters the DP mode and current reduces from ISB to IDP (see Table 14.1 on page 26). Once the device has entered the DP mode, all commands are ignored except the RES command (which releases the device from the DP mode). The RES command also provides the Electronic Signature of the device to be output on SO, if desired (see sections 9.13 and 9.13.1). DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Status Register operation, and continues the operation uninterrupted. 22 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 9.12 Deep Power Down (DP) Command Sequence CS# tDP Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI Hi-Z SO Standby Mode Deep Power-down Mode 9.13 Release from Deep Power Down (RES) The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the Deep Power Down mode, all commands except RES are ignored. The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire duration of the sequence. The command sequence is shown in Figure 9.13 and Table 9.5. The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions from DP mode to the standby mode after a delay of tRES (see Table 16.1 on page 27). In the standby mode, the device can execute any read or write command. Figure 9.13 Release from Deep Power Down (RES) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command tRES SI Hi-Z SO Deep Power-down Mode Standby Mode 9.13.1 Release from Deep Power Down and Read Electronic Signature (RES) The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.14 and Table 9.5 for the command sequence and signature value. The Electronic Signature is not to be confused with the identification data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead. After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to output the Electronic Signature repeatedly. August 31, 2006 S25FL040A_00_B0 S25FL040A 23 Data Sheet (Preliminary) When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as previously described. The RES command always provides access to the Electronic Signature of the device and can be applied even if DP mode has not been entered. Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the operation continues uninterrupted. Figure 9.14 Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCK Command 3 Dummy Bytes tRES 1 0 SI SO Hi-Z 23 22 21 MSB 3 2 7 MSB 6 5 4 3 2 1 0 Electronic ID out Deep Power-down Mode Standby Mode Table 9.5 Command Definitions Operation Command READ FAST_READ Read RDID READ_ID WREN Write Control WRDI SE Erase BE Program Status Register WRSR DP Power Saving RES Write to Status Register Deep Power Down Release from Deep Power Down Release from Deep Power Down and Read Electronic Signature (Note 2) 01H (0000 0001) B9H (1011 1001) ABH (1010 1011) ABH (1010 1011) 0 0 0 0 0 0 0 3 PP RDSR Bulk (Chip) Erase Page Program Read from Status Register C7H (1100 0111) 02H (0000 0010) 05H (0000 0101) 0 3 0 0 0 0 0 1 to 256 1 to ∞ 1 0 0 1 to ∞ Write Disable Sector Erase 04H (0000 0100) D8H (1101 1000) 0 3 0 0 0 0 Description Read Data Bytes Read Data Bytes at Higher Speed Read Identification (Note 1) Read Manufacture and Device Identification (Note 1) Write Enable One-Byte Command Code 03H (0000 0011) 0BH (0000 1011) 9FH (1001 1111) 90H (1001 0000) 06H (0000 0110) Address Bytes 3 3 0 3 0 Dummy Byte 0 1 0 0 0 Data Bytes 1 to ∞ 1 to ∞ 1 to 3 1 to ∞ 0 Notes 1. The S25FL040A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (12h for uniform sector, 25h for top boot, 26h for bottom boot). 2. The S25FL040A has an Electronic Signature ID of 12h. 10. Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows (see Figure 10.1 and Table 10.1): At power-up, VCC (min) plus a period of tPU At power-down, VSS 24 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements. No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the WEL bit is reset (0). Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed. When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all operations are disabled and the device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Register, program, or erase operation is in progress. Figure 10.1 Power-Up Timing Diagram Vcc (max) Vcc Vcc (min) t PU Full Device Access Time Table 10.1 Power-Up Timing Characteristics Symbol VCC(min) tPU Parameter VCC (minimum) VCC (min) to device operation Min 2.7 10 Max Unit V ms 11. Initial Delivery State The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status Register contains 00h (all Status Register bits are 0). 12. Absolute Maximum Ratings Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond those indicated in this section and in the Operating Ranges section of this document is not implied. Device operation for extended periods at the limits listed in this section may affect device reliability. Table 12.1 Absolute Maximum Ratings Description Ambient Storage Temperature Voltage with Respect to Ground: All Inputs and I/Os Rating –65°C to +150°C –0.3 V to 4.5 V August 31, 2006 S25FL040A_00_B0 S25FL040A 25 Data Sheet (Preliminary) 13. Operating Ranges Table 13.1 Operating Ranges Description Ambient Operating Temperature (TA) Commerical Industrial Positive Power Supply Voltage Range Rating 0°C to +70°C –40°C to +85°C 2.7 V to 3.6 V Note Operating ranges define those limits between which functionality of the device is guaranteed. 14. DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 15.1 on page 27, when relying on the quoted parameters. Table 14.1 DC Characteristics (CMOS Compatible) Parameter Description Test Conditions (See Note) Min Typ. Max Unit VCC Supply Voltage SCK = 0.1 VCC/0.9VCC 33 MHz VCC = 3.0V, 50 MHz 2.7 3 3.6 9 13 V mA mA mA mA mA mA µA µA µA µA V V V V ICC1 Active Read Current SCK = 0.1 VCC/0.9VCC ICC2 ICC3 ICC4 ICC5 ISB IDP ILI ILO VIL VIH VOL VOH Active Page Program Current Active WRSR Current Active Sector Erase Current Active Bulk Erase Current Standby Current Deep Power Down Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CS# = VCC CS# = VCC CS# = VCC CS# = VCC VCC = 3.0 V CS# = VCC VCC = 3.0 V CS# = VCC VIN = GND to VCC VIN = GND to VCC –0.3 0.7 VCC IOL = 1.6 mA, VCC = VCC min IOH = –0.1 mA VCC – 0.2 13.5 22 24 24 24 20 1.5 50 5 1 1 0.3 VCC VCC + 0.5 0.4 Note Typical values are at TA = 25°C and 3.0 V. 15. Test Conditions Figure 15.1 AC Measurements I/O Waveform 0.8 VCC Input Levels 0.2 VCC Input and Output 0.7 VCC 0.5 VCC 0.3 VCC 26 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Table 15.1 Test Specifications Symbol CL Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage Min 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC 0.5 VCC Max Unit pF ns V V V 16. AC Characteristics Table 16.1 AC Characteristics Symbol (Notes) FSCK FSCK tCRT tCFT tWH tWL tCS tCSS (3) tCSH (3) tHD (3) tCD (3) tHC tCH tV tHO tHD:DAT tSU:DAT tR tF tLZ (3) tHZ (3) tDIS (3) tWPS (3) tWPH (3) tW tDP tRES tPP tSE tBE Parameter SCK Clock Frequency READ command SCK Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock Rise Time (Slew Rate) Clock Fall Time (Slew Rate) SCK High Time SCK Low Time CS# High Time CS# Setup Time CS# HOLD Time HOLD# Setup Time (relative to SCK) HOLD# Hold Time (relative to SCK) HOLD# Setup Time (relative to SCK) HOLD# Hold Time (relative to SCK) Output Valid Output Hold Time Data in Hold Time Data in Setup Time Input Rise Time Input Fall Time HOLD# to Output Low Z HOLD# to Output High Z Output Disable Time Write Protect Setup Time Write Protect Hold Time Write Status Register Time CS# High to Deep Power Down Mode Release DP Mode Page Programming Time Sector Erase Time Bulk Erase Time 1.5 (1) 0.5 (1) 3 (1) 15 15 67 150 3 30 3 (2) 3 (2) 24 (2) 0 5 5 5 5 10 10 10 Min D.C. D.C. 0.1 0.1 9 9 100 5 5 5 5 5 5 10 10 Typ (Notes) Max (Notes) 25 50 Unit MHz MHz V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms μs μs ms sec sec Notes 1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern 2. Under worst-case conditions of 90°C; VCC = 2.7V; 100,000 cycles 3. Not 100% tested August 31, 2006 S25FL040A_00_B0 S25FL040A 27 Data Sheet (Preliminary) Figure 16.1 SPI Mode 0 (0,0) Input Timing CS# tC S tCSH SCK tCSS tCSH tCSS tSU:DAT tHD:DAT SI MSB IN tCRT tCFT LSB IN SO Hi-Z Figure 16.2 SPI Mode 0 (0,0) Output Timing CS# tWH SCK tV tHO tHO LSB OUT tV tWL tDIS SO 28 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) Figure 16.3 HOLD# Timing CS# tCH tHD tHC SCK tCD tHZ tLZ SO SI HOLD# Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# tWPS tWPH CS# SCK SI SO Hi-Z August 31, 2006 S25FL040A_00_B0 S25FL040A 29 Data Sheet (Preliminary) 17. Physical Dimensions 17.1 SOA 008—Narrow 8-pin Plastic Small Outline 150 mils Body Width Package 3 D A 5 4 0.20 C D A-B H SEE DETAIL B WITH PLATING 9 b1 3 E1 4 c E (b) 7 SECTION A-A 0.33 C A-B D H c1 E1/2 E/2 BASE METAL e B 5 b 0.25 M C 0.10 C q2 0.07 R MIN. GAUGE PLANE A q1 L L1 DETAIL B A q SEATING PLANE L2 A A2 0.10 C SEATING PLANE A1 C C NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N θ θ1 θ2 0˚ 5˚ 0˚ MIN 0.069 0.002 0.067 0.014 0.013 0.0075 0.006 MAX 0.085 0.0098 0.075 0.019 0.018 0.0095 0.008 MIN 1.753 0.051 1.70 0.356 0.330 0.191 0.152 MAX 2.159 0.249 1.91 0.483 0.457 0.241 0.203 5. 6. 7. 8. 4. . SOC 008 (inches) SOC 008 (mm) 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0.208 BSC 0.315 BSC 0.208 BSC .050 BSC 0.020 0.030 5.283 BSC 8.001 BSC 5.283 BSC 1.27 BSC 0.508 0.762 .055 REF .010 BSC 8 8˚ 15˚ 1.40 REF 0.25 BSC 8 0˚ 5˚ 0˚ 8˚ 15˚ 9. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 3432 \ 16-038.03 \ 10.28.04 30 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 17.2 SOC 008—Wide 8-pin Plastic Small Outline 208 mils Body Width Package 3 D A 5 4 0.20 C D A-B H SEE DETAIL B WITH PLATING 9 b1 3 E1 4 c E (b) 7 SECTION A-A 0.33 C A-B D H c1 E1/2 E/2 BASE METAL e B 5 b 0.25 M C 0.10 C q2 0.07 R MIN. GAUGE PLANE A q1 L L1 DETAIL B A q SEATING PLANE L2 A A2 0.10 C SEATING PLANE A1 C C NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N θ θ1 θ2 0˚ 5˚ 0˚ MIN 0.069 0.002 0.067 0.014 0.013 0.0075 0.006 MAX 0.085 0.0098 0.075 0.019 0.018 0.0095 0.008 MIN 1.753 0.051 1.70 0.356 0.330 0.191 0.152 MAX 2.159 0.249 1.91 0.483 0.457 0.241 0.203 5. 6. 7. 8. 4. . SOC 008 (inches) SOC 008 (mm) 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0.208 BSC 0.315 BSC 0.208 BSC .050 BSC 0.020 0.030 5.283 BSC 8.001 BSC 5.283 BSC 1.27 BSC 0.508 0.762 .055 REF .010 BSC 8 8˚ 15˚ 1.40 REF 0.25 BSC 8 0˚ 5˚ 0˚ 8˚ 15˚ 9. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 3432 \ 16-038.03 \ 10.28.04 August 31, 2006 S25FL040A_00_B0 S25FL040A 31 Data Sheet (Preliminary) 17.3 USON 8L (5 x 6 mm) No-Lead Package QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC DIMENSIONS SYMBOL e N ND L b D2 E2 D E A A1 K θ 0 0.45 0.00 0.55 0.35 3.90 3.30 MIN NOM 1.27 BSC 8 4 0.60 0.40 4.00 3.40 5.00 BSC 6.00 BSC 0.50 0.02 0.20 MAX. --12 2 0.55 0.05 0.65 0.45 4.10 3.50 4 3 5 MAX NOTE NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. 6. 7. 8. 9. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. PIN #1 ID ON TOP WILL BE LASER MARKED. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 3448\ 16-038.28 \ 04.15.05 32 S25FL040A S25FL040A_00_B0 August 31, 2006 Data Sheet (Preliminary) 18. Revision History Section Revision A (January 26, 2006) Global Revision A4 (June 29, 2006) DC Characteristics Revision B0 (August 31, 2006) Global Rewrote entire document for better flow and clarity. No specifications were changed. Added typical specification and changed maximum specification for ICC2. Initial release. Description Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. August 31, 2006 S25FL040A_00_B0 S25FL040A 33