S29CD032G0MFAA112

S29CD-G Flash Family S29CD032G, S29CD016G 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O™ featuring 170 nm Process Technology Data Sheet PRELIMINARY Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Note: This document supercedes datasheet information for the S29CD016G revision A4, and S29CD032G revision B0. The S29CD-G device is the factory-recommended migration path. Please refer to specifications and ordering information found in this document. Publication Number S29CD-G_00 Revision B Amendment 0 Issue Date November 14, 2005 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Preliminary Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 S29CD-G Flash Family S29CD032G, S29CD016G 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O™ featuring 170 nm Process Technology Data Sheet PRELIMINARY Distinctive Characteristics Architecture Advantages Simultaneous Read/Write operations — Read data from one bank while executing erase/ program functions in other bank — Zero latency between read and write operations — Two bank architecture: large bank/small bank 75%/25% User-Defined x32 Data Bus Dual Boot Block — Top and bottom boot sectors in the same device Flexible sector architecture — CD032G: Eight 2K Double Word, Sixty-two 16K Double Word, and Eight 2K Double Word sectors — CD016G: Eight 2K Double Word, Thirty-two 16K Double Word, and Eight 2K Double Word sectors Secured Silicon Sector (256 Bytes) — Factory locked and identifiable: 16 bytes for secure, random factory Electronic Serial Number; Also know as Electronic Marking Manufactured on 170 nm Process Technology Programmable Burst interface — Interfaces to any high performance processor — Linear Burst Read Operation: 2, 4, and 8 double word linear burst with or without wrap around Program Operation — Performs synchronous and asynchronous write operations of burst configuration register settings independently Single power supply operation — Optimized for 2.5 to 2.75 volt read, erase, and program operations Compatibility with JEDEC standards (JC42.4) — Software compatible with single-power supply Flash — Backward-compatible with AMD/Fujitsu Am29LV/ MBM29LV and Am29F/MBM29F flash memories — Standby mode: CMOS: 60 µA max 1 million write cycles per sector typical 20 year data retention typical VersatileI/O™ control — Generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.65 V to 3.60 V compatible I/O signals Software Features Persistent Sector Protection — Locks combinations of individual sectors and sector groups to prevent program or erase operations within that sector (requires only VCC levels) Password Sector Protection — Locks combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-definable 64-bit password Supports Common Flash Interface (CFI) Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion Hardware Features Program Suspend/Resume & Erase Suspend/ Resume — Suspends program or erase operations to allow reading, programming, or erasing in same bank Hardware Reset (RESET#), Ready/Busy# (RY/ BY#), and Write Protect (WP#) inputs ACC input — Accelerates programming time for higher throughput during system production Package options — 80-pin PQFP — 80-ball Fortified BGA — Pb-free package option also available — Known Good Die Performance Characteristics High performance read access — Initial/random access times of 48 ns (32 Mb) and 54 ns (16 Mb) — Burst access times of 7.5 ns (32 Mb) or 9 ns (16Mb) Ultra low power consumption — Burst Mode Read: 90 mA @ 75 MHz max — Program/Erase: 50 mA max Publication Number S29CD-G_00 Revision B Amendment 0 Issue Date November 14, 2005 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Preliminary General Description The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash Memory with VersatileI/O™ manufactured on 170 nm Process Technology. The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be configured for 1,048,576 double words. The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash memory device that can be configured for 524,288 double words. To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst Address Valid (ADV#), and Clock (CLK). Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write functions. A 12.0-volt VPP is not required for program or erase operations, although an acceleration pin is available if faster programming performance is required. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The software command set is compatible with the command sets of the 5 V Am29F or MBM29F and 3 V Am29LV or MBM29LV Flash families. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. See Simultaneous Read/Write Operations Overview. The device provides a 256-byte Secured Silicon Sector that contains Electronic Marking Information for easy device traceability. In addition, the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection is a command sector protection method that replaces the old 12 V controlled protection method; Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank. The device defaults to the Persistent Sector Protection mode. The customer must then choose if the Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always available, independent of the other protection method chosen. The VersatileI/O™ (VCCQ) feature allows the output voltage generated on the device to be determined based on the VIO level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. 2 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The password and software sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system at VCC level. The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 3 Preliminary Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram of Simultaneous Read/Write Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PRQ080–80-Lead Plastic Quad Flat Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 S29CD032G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 S29CD016G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Memory Map and Sector Protect Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Device Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VersatileI/O™ (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Simultaneous Read/Write Operations Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Overview ........................................................................................................................................................................................24 Program/Erase Suspend and Simultaneous Operation .....................................................................................................24 Common Flash Interface (CFI) and Password Program/Verify and Simultaneous Operation .............................24 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Accelerated Program and Erase Operations .......................................................................................................................25 Autoselect Functions ...................................................................................................................................................................25 Automatic Sleep Mode (ASM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Standby Mode ................................................................................................................................................................................25 RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Linear Burst Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CE# Control in Linear Mode .................................................................................................................................................. 28 ADV# Control In Linear Mode .............................................................................................................................................. 28 RESET# Control in Linear Mode ............................................................................................................................................ 29 OE# Control in Linear Mode .................................................................................................................................................. 29 IND/WAIT# Operation in Linear Mode .............................................................................................................................. 29 Burst Access Timing Control ...................................................................................................................................................30 Initial Burst Access Delay Control .........................................................................................................................................30 Burst CLK Edge Data Delivery ................................................................................................................................................30 Burst Data Hold Control ...........................................................................................................................................................30 Asserting RESET# During A Burst Access ............................................................................................................................31 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Initial Access Delay Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Sector and Sector Groups .........................................................................................................................................................33 Persistent Sector Protection ....................................................................................................................................................33 Password Sector Protection .....................................................................................................................................................33 WP# Hardware Protection ......................................................................................................................................................33 Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Persistent Protection Bit (PPB) ................................................................................................................................................34 Persistent Protection Bit Lock (PPB Lock) ..........................................................................................................................34 Dynamic Protection Bit (DYB) ................................................................................................................................................34 Persistent Sector Protection Mode Locking Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Password Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Password and Password Mode Locking Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 64-bit Password ............................................................................................................................................................................36 Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Secured Silicon OTP Sector and Simultaneous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Persistent Protection Bit Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Low VCC Write Inhibit ...............................................................................................................................................................37 Write Pulse Glitch Protection ...................................................................................................................................................38 Logical Inhibit .................................................................................................................................................................................38 Power-Up Write Inhibit .............................................................................................................................................................38 VCC and VIO Power-up And Power-down Sequencing ....................................................................................................38 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reading Array Data in Non-burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reading Array Data in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Autoselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Accelerated Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Unlock Bypass Entry Command ..............................................................................................................................................45 Unlock Bypass Program Command ........................................................................................................................................45 Unlock Bypass Chip Erase Command .................................................................................................................................. 46 Unlock Bypass CFI Command ................................................................................................................................................. 46 Unlock Bypass Reset Command ............................................................................................................................................. 46 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Sector Erase and Program Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Sector Erase and Program Suspend Operation Mechanics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Sector Erase and Program Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Configuration Register Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Configuration Register Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Common Flash Interface (CFI) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Password Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Password Verify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Password Protection Mode Locking Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Persistent Sector Protection Mode Locking Bit Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PPB Lock Bit Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DYB Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Password Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PPB Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 All PPB Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DYB Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PPB Lock Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DYB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PPB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PPB Lock Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Non-volatile Protection Bit Program And Erase Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 5 Preliminary DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Industrial (I) Devices ...................................................................................................................................................................63 Extended (E) Devices ..................................................................................................................................................................63 VCC Supply Voltages ....................................................................................................................................................................63 VIO Supply Voltages .....................................................................................................................................................................63 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Zero Power Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 VCC and VIO Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Asynchronous Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Burst Mode Read for 32 Mb & 16 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Tables Table 1. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 01, Bottom Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Bottom Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 5. Device Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 6. Allowable Conditions for Simultaneous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 7. S29CD-G Flash Family Autoselect Codes (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 8. 32- Bit Linear and Burst Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 9. Valid Configuration Register Bit Definition for IND/WAIT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 10. Burst Initial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 11. Configuration Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 12. Configuration Register After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 14. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 15. CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 16. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17. CFI Primary Vendor-Specific Extended Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 18. Allowed Operations During Erase/Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 19. Memory Array Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 20. Sector Protection Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 21. Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 22. Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 7 Preliminary Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Asynchronous Read Operation ............................................................................................................................................................................ 27 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation ........................................................................... 29 Initial Burst Delay Control ..................................................................................................................................................................................... 30 Program Operation .................................................................................................................................................................................................. 45 Erase Operation ........................................................................................................................................................................................................48 Data# Polling Algorithm.......................................................................................................................................................................................... 57 Toggle Bit Algorithm ................................................................................................................................................................................................60 Maximum Negative Overshoot Waveform ...................................................................................................................................................... 62 Maximum Positive Overshoot Waveform......................................................................................................................................................... 62 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)................................................................................................ 65 Typical ICC1 vs. Frequency ...................................................................................................................................................................................... 65 Test Setup.................................................................................................................................................................................................................... 66 Input Waveforms and Measurement Levels ..................................................................................................................................................... 66 VCC and VIO Power-up Diagram.......................................................................................................................................................................... 67 Conventional Read Operations Timings............................................................................................................................................................68 Burst Mode Read....................................................................................................................................................................................................... 70 Asynchronous Command Write Timing............................................................................................................................................................70 Synchronous Command Write/Read Timing..................................................................................................................................................... 71 RESET# Timings......................................................................................................................................................................................................... 72 WP# Timing................................................................................................................................................................................................................ 72 Chip/Sector Erase Operation Timings................................................................................................................................................................ 74 Back-to-Back Cycle Timings .................................................................................................................................................................................. 74 Data# Polling Timings (During Embedded Algorithms) ................................................................................................................................ 75 Toggle Bit Timings (During Embedded Algorithms)....................................................................................................................................... 75 DQ2 vs. DQ6 for Erase/Erase Suspend Operations...................................................................................................................................... 76 Synchronous Data Polling Timing/Toggle Bit Timings.................................................................................................................................... 76 Sector Protect/Unprotect Timing Diagram ...................................................................................................................................................... 77 Alternate CE# Controlled Write Operation Timings................................................................................................................................... 78 8 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Product Selector Guide Part Number Standard Voltage Range: VCC = 2.5 – 2.75 V VIO = 1.65 – 2.75 V 0R (75 MHz) (32 Mb Only) 48 7.5 FBGA 75 3 52 S29CD-G Flash Family (S29CD032G, S29CD016G) Synchronous/Burst or Asynchronous 0P (66 MHz) 54 9 FBGA/ 9.5 PQFP 66 3 58 20 0M (56 MHz) 64 10 FBGA/ 10 PQFP 56 3 69 0J (40 MHz) 67 17 40 2 71 28 Speed Option (Clock Rate) Max Initial/Asynchronous Access Time, ns (tACC) Max Burst Access Delay (ns) Max Clock Rate (MHz) Min Initial Clock Delay (clock cycles) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 9 Preliminary Ordering Information The order number (Valid Combination) is formed by the following: S29CD032G 0J F A I 0 0 0 Packing Type 0 2 3 = = = Tray 7” Tape and Reel 13” Tape and Reel Additional Ordering Options (16th Character) Top or Bottom Boot 0 1 = = Top Boot Bottom Boot Additional Ordering Options (15th Character) Mask Revision 0 1 2 = = = A A1 (16 Mb only) with 7E, 36, 01/00 Autoselect ID A1 (16 Mb only) with 7E, 08, 01/00 Autoselect ID Temperature Range and Quality Grade A I M N = = = = Industrial (–40°C to +85°C), GT grade Industrial (–40°C to +85°C) Extended (–40°C to +125°C), GT grade Extended (–40°C to +125°C) Material Set A F = = Standard Pb-free Option Package Type Q F = = Plastic Quad Flat Package (PQFP) Fortified Ball Grid Array, 1.0 mm pitch package Clock Frequency 0J 0M 0P 0R = = = = 40 56 66 75 MHz MHz MHz MHz (32 Mb Only) Device Number/description S29CD032G/S29CD016G 32 or 16 Megabit (1 M or 512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Manufactured on 110 nm floating gate technology Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations S29CD032G S29CD016G 1. 2. 3. QAI, QFI, QAN, QFN FAI, FFI, FAN, FFN 0R (32 MB Only), 0P, 0M, 0J 00, 01 The ordering part number that appears on BGA packages omits the leading “S29”. Contact your local sales representative for GT grade options. Refer to the KGD data sheet supplement for die/wafer sales. 10 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Block Diagram VCC VSS DQmax–DQ0 Amax–A0 Erase Voltage Generator WE# RESET# ACC WP# WORD# VIO Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder VCC Detector Y-Gating Address Latch Timer X-Decoder Cell Matrix ADV# CLK Burst State Control IND/ WAIT# Burst Address Counter Amax–A0 DQmax–DQ0 Amax–A0 Note: Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 11 Preliminary Block Diagram of Simultaneous Read/Write Circuit VCC VSS OE# Y-Decoder Amax–A0 Upper Bank Address Upper Bank Latches and Control Logic Amax–A0 RESET# WE# CE# ADV# DQmax–DQ0 Amax–A0 STATE CONTROL & COMMAND REGISTER Status X-Decoder DQmax–DQ0 Amax–A0 DQmax–DQ0 Control X-Decoder DQmax–DQ0 Lower Bank Amax–A0 Lower Bank Address Note: Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0. 12 S29CD-G Flash Family Latches and Control Logic Y-Decoder S29CD-G_00_B0 November 14, 2005 Preliminary Connection Diagrams IND/WAIT# RESET# RY/BY# ADV# VCCQ WE# WP# MCH OE# CE# DQ16 DQ17 DQ18 DQ19 VCCQ VSS DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VCCQ VSS DQ28 DQ29 DQ30 DQ31 MCH A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 80-Pin PQFP 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A10 A11 A12 A13 ACC A14 A15 VSS A3 A4 A5 A6 A7 A8 VCC A9 CLK VCC VSS NC NC NC DQ15 DQ14 DQ13 DQ12 VSS VCCQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSS VCCQ DQ3 DQ2 DQ1 DQ0 A19 (32 Mb) / NC (16 Mb) A18 A17 A16 Note: On 16 Mb device, pin 44 (A19) is NC. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 13 Preliminary Physical Dimensions PRQ080–80-Lead Plastic Quad Flat Package 6 3 PIN S D D1 D3 PIN R 0˚MIN. PIN ONE I.D. 0.30 ± 0.05 R GAGE 0.25 PLANE E3 -A-BE1 E 3 6 L 0˚-7˚ 7˚ TYP. b 4 ccc C A 0.20 MIN. FLAT SHOULDER 7˚ TYP. aa a M C A B S D S DETAIL X SEE NOTE 3 PIN P -DSEE DETAIL X e BASIC A2 A1 S S A 2 -A-CSEATING PLANE PIN Q b c SECTION S-S PACKAGE JEDEC SYMBOL A A1 A2 b c D D1 D3 e E E1 E3 aaa ccc L P Q R S 0.73 MIN -0.25 2.70 0.30 0.15 17.00 13.90 --23.00 19.90 ---- PQR 080 MO-108(B)CB-1 NOM --2.80 --17.20 14.00 12.0 0.80 23.20 20.00 18.40 0.20 0.10 0.88 24 40 64 80 1.03 MAX 3.35 -2.90 0.45 0.23 17.40 14.10 --23.40 20.10 ---SEE NOTE 3 REFERENCE SEE NOTE 3 REFERENCE BASIC, SEE NOTE 7 SEE NOTE 4 NOTES NOTES: 1. 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -ADIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION. CONTROLLING DIMENSIONS: MILLIMETER. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH INNERMOST AND OUTERMOST POINTS. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN ±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR PITCH < 0.5 mm. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500) 1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm 2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm. COPLANARITY IS MEASURED PER SPECIFICATION 06-500. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE WITHIN ±0.0085". 3. 4. 5. 6. 7. 8. 9. 3213\38.4C 14 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Connection Diagrams 80-Ball Fortified BGA A8 A2 A7 A3 A6 A6 A5 VSS A4 ACC A3 VCC A2 A14 A1 A15 B8 A1 B7 A4 B6 A5 B5 A8 B4 A9 B3 A12 B2 A13 B1 A16 C8 A0 C7 MCH C6 A7 C5 NC C4 A10 C3 D8 DQ29 D7 DQ30 D6 DQ31 D5 NC D4 NC D3 E8 VCCQ E7 DQ26 E6 DQ28 E5 DQ27 E4 DQ1 E3 F8 VSS F7 DQ24 F6 DQ25 F5 RY/BY# F4 DQ5 F3 DQ6 F2 DQ7 F1 VSS G8 VCCQ G7 DQ23 G6 DQ21 G5 DQ22 G4 DQ9 G3 DQ10 G2 DQ8 G1 VCCQ H8 DQ20 H7 J8 DQ16 J7 K8 MCH K7 NC K6 WE# K5 VCC K4 VSS K3 CLK K2 RESET# K1 VCCQ DQ18 IND/WAIT# H6 DQ19 H5 DQ17 H4 WP# H3 DQ11 H2 DQ12 H1 DQ13 J6 OE# J5 CE# J4 NC J3 ADV# J2 DQ14 J1 DQ15 A11 A19 (32 Mb)/ DQ2 NC (16 Mb) C2 D2 E2 A18 C1 A17 DQ0 D1 DQ3 DQ4 E1 VCCQ Note: On 16 Mb device, ball D3 (A19) is NC. Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 15 Preliminary Physical Dimensions LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) 0.20 C 2X D A D1 eD K J H G F E D C B A 8 7 6 7 SE eE 5 E 4 3 E1 0 φ0 .5 2 1 1.00±0.5 A1 CORNER ID. (INK OR LASER) B 1.00±0.5 A1 CORNER TOP VIEW 0.20 C 2X 6 NXφb φ0.25 M C A B φ0.10 M C SD 7 A1 CORNER BOTTOM VIEW A A2 A1 SEATING PLANE C 0.25 C 0.15 C SIDE VIEW PACKAGE JEDEC LAA 080 N/A 13.00 x 11.00 mm PACKAGE NOTE NOTES: 1. 2. MAX 1.40 --PROFILE HEIGHT STANDOFF BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.70 BALL DIAMETER BALL PITCH - D DIRECTION BALL PITCH - E DIRECTION SOLDER BALL PLACEMENT 8. 9. 7 6 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW , SD OR SE = e/2 N/A "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 3214\38.12C SYMBOL A A1 A2 D E D1 E1 MD ME N φb eD eE SD/SE MIN -0.40 0.60 NOM ---13.00 BSC. 11.00 BSC. 9.00 BSC. 7.00 BSC. 10 8 80 0.50 0.60 1.00 BSC. 1.00 BSC. 0.50 BSC 16 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Pin Configuration A0–A19 DQ0–DQ31 CE# OE# WE# VSS NC RY/BY# = = = = = = = = 20-bit address bus for 32 Mb device, (19-bit for 16 Mb). A9 supports 12 V autoselect inputs. 32-bit data inputs/outputs/float Chip Enable Input. This signal is asynchronous relative to CLK for the burst mode. Output Enable Input. This signal is asynchronous relative to CLK for the burst mode. Write enable. This signal is asynchronous relative to CLK for the burst mode. Device ground Pin not connected internally Ready/Busy output and open drain. When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. Load Burst Address input. Indicates that the valid address is present on the address inputs. End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs. Provides data valid feedback only when the burst length is set to continuous. Write Protect input. When WP# = VOL, the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. Acceleration input. When taken to 12 V, program and erase operations are accelerated. When not used for acceleration, ACC = VSS to VCC. Output Buffer Power Supply (1.65 V to 2.75 V) Chip Power Supply (2.5 V to 2.75 V) or (3.00 V to 3.60 V) Hardware reset input Must Connect High (to VCC) CLK = ADV# IND# = = WAIT# WP# = = ACC = VIO (VCCQ) VCC RESET# MCH = = = = November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 17 Preliminary Logic Symbols S29CD032G 20 A0–A19 CLK CE# OE# WE# RESET# ADV# ACC WP# VIO (VCCQ) IND/WAIT# DQ0–DQ31 32 RY/BY# S29CD016G 19 A0–A18 CLK CE# OE# WE# RESET# ADV# ACC WP# VIO (VCCQ) IND/WAIT# DQ0–DQ31 32 RY/BY# 18 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Memory Map and Sector Protect Groups The following tables lists the address ranges for all sectors and sector groups, and the sector sizes. Table 23. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot Sector Sector x32 Group Address Range Note 4 (A19:A0) Bank 0, Small Bank Note 2 SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh 18000h–1BFFFh 1C000h–1FFFFh 20000h–23FFFh 24000h–27FFFh 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh 34000h–37FFFh 38000h–3BFFFh 3C000h–3FFFFh Sector Size (KDwords) 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Sector Sector x32 Group Address Range Note 4 (A19:A0) Bank 1, Large Bank Note 2 40000h–43FFFh SG12 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh 64000h–67FFFh 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh 74000h–77FFFh 78000h–7BFFFh 7C000h–7FFFFh 80000h–83FFFh 84000h–87FFFh 88000h–8BFFFh 8C000h–8FFFFh 90000h–93FFFh 94000h–97FFFh 98000h–9BFFFh 9C000h–9FFFFh A0000h–A3FFFh A4000h–A7FFFh A8000h–ABFFFh AC000h–AFFFFh B0000h–B3FFFh B4000h–B7FFFh B8000h–BBFFFh BC000h–BFFFFh C0000h–C3FFFh C4000h–C7FFFh C8000h–CBFFFh CC000h–CFFFFh D0000h–D3FFFh D4000h–D7FFFh D8000h–DBFFFh DC000h–DFFFFh E0000h–E3FFFh E4000h–E7FFFh E8000h–EBFFFh EC000h–EFFFFh F0000h–F3FFFh F4000h–F7FFFh F8000h–FBFFFh FC000h–FC7FFh FC800h–FCFFFh FD000h–FD7FFh FD800h–FDFFFh FE000h–FE7FFh FE800h–FEFFFh FF000h–FF7FFh FF800h–FFFFFh Sector Size (KDwords) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 SA0 Note 1 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 Note 3 SA77 Note 3 SG13 SG14 SG9 SG15 SG10 SG16 SG11 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 Notes: 1. 2. 3. 4. Secured Silicon Sector overlays this sector when enabled. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1. This sector has the additional WP# pin sector protection feature. Sector groups are for Sector Protection. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 19 Preliminary Table 24. 32 Mb Memory Map and Sector Protect Groups for Ordering Option 01, Bottom Boot Sector x32 Sector Group Address Range Size Note 4 (A19:A0) (KDwords) Bank 0, Large Bank Note 2 SA0 Note 1 SG0 00000h–007FFh 2 SA1 Note 1 SG1 00800h–00FFFh 2 SA2 SG2 01000h–017FFh 2 SA3 SG3 01800h–01FFFh 2 SA4 SG4 02000h–027FFh 2 SA5 SG5 02800h–02FFFh 2 SA6 SG6 03000h–037FFh 2 SA7 SG7 03800h–03FFFh 2 SA8 04000h–07FFFh 16 SA9 SG8 08000h–0BFFFh 16 SA10 0C000h–0FFFFh 16 SA11 10000h–13FFFh 16 SA12 14000h–17FFFh 16 SG9 SA13 18000h–1BFFFh 16 SA14 1C000h–1FFFFh 16 SA15 20000h–23FFFh 16 SA16 24000h–27FFFh 16 SG10 SA17 28000h–2BFFFh 16 SA18 2C000h–2FFFFh 16 SA19 30000h–33FFFh 16 SA20 34000h–37FFFh 16 SG11 SA21 38000h–3BFFFh 16 Sector SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 3C000h–3FFFFh 40000h–43FFFh 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh 64000h–67FFFh 68000h–6BFFFh 70000h–73FFFh 74000h–77FFFh 78000h–7BFFFh 7C000h–7FFFFh 80000h–83FFFh 84000h–87FFFh 88000h–8BFFFh 8C000h–8FFFFh 90000h–93FFFh 94000h–97FFFh 98000h–9BFFFh 9C000h–9FFFFh A0000h–A3FFFh A4000h–A7FFFh A8000h–ABFFFh AC000h–AFFFFh B0000h–B3FFFh B4000h–B7FFFh B8000h–BBFFFh BC000h–BFFFFh 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Sector Sector x32 Sector Group Address Range Size Note 4 (A19:A0) (KDwords) Bank 1, Small Bank (Note 2) C0000h–C3FFFh 16 C4000h–C7FFFh 16 SG20 C8000h–CBFFFh 16 CC000h–CFFFFh 16 D0000h–D3FFFh 16 D4000h–D7FFFh 16 SG21 D8000h–DBFFFh 16 DC000h–DFFFFh 16 E0000h–E3FFFh 16 E4000h–E7FFFh 16 SG22 E8000h–EBFFFh 16 EC000h–EFFFFh 16 F0000h–F3FFFh 16 SG23 F4000h–F7FFFh 16 F8000h–FBFFFh 16 SG24 FC000h–FC7FFh 2 SG25 FC800h–FCFFFh 2 SG26 FD000h–FD7FFh 2 SG27 FD800h–FDFFFh 2 SG28 FE000h–FE7FFh 2 SG29 FE800h–FEFFFh 2 SG30 FF000h–FF7FFh 2 SG31 FF800h–FFFFFh 2 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Note 3 SG12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 Notes: 1. 2. 3. 4. This sector has the additional WP# pin sector protection feature. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1. Secured Silicon Sector overlays this sector when enabled. Sector groups are for Sector Protection. 20 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Table 25. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Top Boot Sector Sector Group x32 Address Range (A18:A0) Sector Size (KDwords) Sector Sector Group x32 Address Range (A18:A0) Sector Size (KDwords) Bank 0, Small Bank Note 2 SA0 Note 1 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SG9 SG8 SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh 18000h–1BFFFh 1C000h–1FFFFh 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Note 2 SA45 Note 2 Bank 1, Large Bank Note 2 20000h–23FFFh SG10 24000h–27FFFh 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh SG11 34000h–37FFFh 38000h–3BFFFh 3C000h–3FFFFh 40000h–43FFFh SG12 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh SG13 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh SG14 64000h–67FFFh 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh SG15 74000h–77FFFh 78000h–7BFFFh SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 7C000h–7C7FFh 7C800h–7CFFFh 7D000h–7D7FFh 7D800h–7DFFFh 7E000h–7E7FFh 7E800h–7EFFFh 7F000h–7F7FFh 7F800h–7FFFFh 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 Notes: 1. 2. 3. 4. Secured Silicon Sector overlays this sector when enabled. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2. This sector has the additional WP# pin sector protection feature. Sector groups are for Sector Protection. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 21 Preliminary Table 26. 16 Mb, Memory Map and Sector Protect Groups for Ordering Option 00, Bottom Boot Sector x32 Sector Group Address Range Size Note 4 (A19:A0) (KDwords) Bank 0, Large Bank Note 2 SA0 Note 1 SG0 00000h–007FFh 2 SA1 Note 1 SG1 00800h–00FFFh 2 SA2 SG2 01000h–017FFh 2 SA3 SG3 01800h–01FFFh 2 SA4 SG4 02000h–027FFh 2 SA5 SG5 02800h–02FFFh 2 SA6 SG6 03000h–037FFh 2 SA7 SG7 03800h–03FFFh 2 SA8 04000h–07FFFh 16 SA9 SG8 08000h–0BFFFh 16 SA10 0C000h–0FFFFh 16 SA11 10000h–13FFFh 16 SA12 14000h–17FFFh 16 SG9 SA13 18000h–1BFFFh 16 SA14 1C000h–1FFFFh 16 SA15 20000h–23FFFh 16 SA16 24000h–27FFFh 16 SG10 SA17 28000h–2BFFFh 16 SA18 2C000h–2FFFFh 16 SA19 30000h–33FFFh 16 SA20 34000h–37FFFh 16 SG11 SA21 38000h–3BFFFh 16 SA22 3C000h–3FFFFh 16 SA23 40000h–43FFFh 16 SA24 44000h–47FFFh 16 SG12 SA25 48000h–4BFFFh 16 SA26 4C000h–4FFFFh 16 SA27 50000h–53FFFh 16 SA28 54000h–57FFFh 16 SG13 SA29 58000h–5BFFFh 16 SA30 5C000h–5FFFFh 16 SA31 60000h–63FFFh 16 SA32 64000h–67FFFh 16 SG14 SA33 68000h–6BFFFh 16 SA34 6C000h–6FFFFh 16 Sector Sector Sector x32 Sector Group Address Range Size Note 4 (A19:A0) (KDwords) Bank 1, Small Bank Note 2 70000h–73FFFh 16 SG15 74000h–77FFFh 16 78000h–7BFFFh 16 SG16 7C000h–7C7FFh 2 SG17 7C800h–7CFFFh 2 SG18 7D000h–7D7FFh 2 SG19 7D800h–7DFFFh 2 SG20 7E000h–7E7FFh 2 SG21 7E800h–7EFFFh 2 SG22 7F000h–7F7FFh 2 SG23 7F800h–7FFFFh 2 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Notes: 1. 2. 3. 4. This sector has the additional WP# pin sector protection feature. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2. Secured Silicon Sector overlays this sector when enabled. Sector groups are for Sector Protection. 22 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Device Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 27 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 27. Operation Read Asynchronous Write Synchronous Write Standby (CE#) Output Disable Reset Device Bus Operation CLK X X ADV# X X Addresses AIN AIN AIN X X X X X X X HIGH Z X Data (DQ0–DQ31) DOUT DIN DIN HIGH Z HIGH Z HIGH Z CE# OE# WE# RESET# L L L H L X L H H X H X H L L X H X H H H H H L PPB Protection Status (Note 2) L L H H X X 00000001h, (protected) Sector Address, A6 = H A9 = VID, A7 – A0 = 02h 00000000h (unprotect) A6 = L Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data bus Terminate Current Burst Read Cycle Terminate Current Burst Read Cycle with RESET# Terminate Current Burst Read Cycle; Start New Burst Read Cycle L L H X L X L X X H H H H H H H H H L H X H X X AIN X X X AIN X Burst Data Out HIGH Z HIGH Z X Legend: L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care. Notes: 1. 2. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB VersatileI/O™ (VIO) Control The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The output voltage generated on the device is determined based on the VIO (VCCQ) level. For the 2.6 V VCC Mask Option, a VIO of 1.65 V – 1.95 V allows the device to interface with I/Os lower than 2.5 V. Vcc = VIO (2.5 V to 2.75V) make the device appear as a 2.5 V only. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 23 Preliminary The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. Address access time (tACC) is the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses were stable for at least tACC–tOE time and CE# is asserted for at least tCE–tOE time). See Reading Array Data in Non-burst Mode and Reading Array Data in Burst Mode for more information. Refer to the Asynchronous Read Operations table for timing specifications and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Simultaneous Read/Write Operations Overview Overview The Simultaneous Read/Write feature allows embedded program or embedded erase operation to be executed in the Small Bank, while reading from the Large Bank. The opposite case is not valid. Table 28. Small Bank Allowable Conditions for Simultaneous Operation Large Bank Burst (Synchronous) Read or Asynchronous Read Burst (Synchronous) Read or Asynchronous Read Embedded Erase Embedded Program Note: Please refer to the Memory Map Table 23, Table 24, Table 25, and Table 26 for Small and Large Bank assignments. Program/Erase Suspend and Simultaneous Operation There is no restriction to implementing a program-suspend or erase-suspend during a simultaneous operation. Common Flash Interface (CFI) and Password Program/Verify and Simultaneous Operation Simultaneous read/write operation is disabled during the CFI and Password Program/Verify operation, including PPB program/erase and unlocking a password operation. Only array data can be read in the Large Bank during a simultaneous operation. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. See Sector Erase and Program Suspend Command on page 47 for details on programming data to the device using both standard and Unlock Bypass command sequences. 24 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary An erase operation can erase one sector, multiple sectors, or the entire device. Table 23, Table 24, Table 25, and Table 26 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. See Command Definitions on page 42 for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. When in Synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. CLK and ADV# address latch is supported in synchronous programming mode. During a synchronous write operation, to write a command or command sequence, (which includes programming data to the device and erasing sectors of memory), the system must drive ADV# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and CE# to VIH, when writing commands or data. Accelerated Program and Erase Operations The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH (12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses the higher voltage on the ACC pin to accelerate the operation. A sector that is being protected with the WP# pin is protected during accelerated program or Erase. Note: The ACC pin must not be at VHH during any operation other than accelerated programming, or device damage can result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect Mode on page 26 and Autoselect Command on page 43 for more information. Automatic Sleep Mode (ASM) The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is required to provide new data. ICC8 in DC Characteristics on page 64 represents the automatic sleep mode current specification. Standby Mode When the system is not responding or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at Vcc ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 in DC Characteristics on page 64 represents the standby current specification. Caution: entering the standby mode via the RESET# pin also resets the device to the read mode and floats the data I/O pins. Furthermore, entering ICC7 during a program or erase operation November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 25 Preliminary leaves erroneous data in the address locations being operated on at the time of the RESET# pulse. These locations require updating after the device resumes standard operations. See RESET#: Hardware Reset Pin on page 26 for further discussion of the RESET# pin and its functions. RESET#: Hardware Reset Pin The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic 0 on this pin forces the device out of any mode that is currently executing back to the reset state. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data output pins for the duration of the RESET pulse. All pins are don’t cares during the reset operation. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset operation is internally complete. This action requires between 1 µs and 7µs for either Chip Erase or Sector Erase. The RY/BY# pin can be used to determine when the reset operation is complete. Otherwise, allow for the maximum reset time of 11 µs. If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank after 500 ns if the bank was in the read/reset mode at the time RESET# was asserted. If one of the banks was in the middle of either a program or erase operation when RESET# was asserted, the user must wait 11 µs before accessing that bank. Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset. These locations need updating after the reset operation is complete. See Figure 19, R ESET# Timings, o n page 72 for timing specifications. Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization until VCC and VIO reaches steady state voltages. Output Disable Mode See Table 27 on page 23 Device Bus Operation for OE# Operation in Output Disable Mode. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 24 on page 20 (top boot devices) or Table 25 on page 21 (bottom boot devices). In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 23 on page 19 through Table 26 on page 22). Table 29 shows the remaining address bits that are don’t care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command. This method does not require VID. See Command Definitions on page 42 for details on using the autoselect mode. 26 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Table 29. Description S29CD-G Flash Family Autoselect Codes (High Voltage Method) CE# OE# WE# L L L L L L H H H A19 A5 to A10 A9 A8 A7 A6 to A3 A2 A1 A0 A11 A4 X X X X X X VID VID VID X X X X L L L L L X X L X L H X L H L L H L H L DQ7 to DQ0 0001h 007Eh 0036h (16Mb) 0009h (32Mb) 0000h Ordering Option 00 0001h Ordering Option 01 0000h (unprotected) 0001h (protected) Manufacturer ID: Spansion Autoselect Device Code Read Cycle 1 Read Cycle 2 Read Cycle 3 L L H X X VID X L L L H H H H PPB Protection Status L L H SA X VID X L L L L L H L Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes can also be accessed in-system via command sequences. See Table 40 on page 48 and Table 42 on page 55. Asynchronous Read Operation (Non-Burst) The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and is used for device selection. OE# is the output control and is used to gate data to the output pins if the device is selected. The device is powered-up in an asynchronous read mode. In the asynchronous mode the device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and is used for device selection. OE# is the output control and is used to gate data to the output pins if the device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses are stable for at least tACC–tOE time). CE# CLK ADV# Addresses Data OE# WE# IND/WAIT# VIH Float Float VOH Address 0 Address 1 Address 2 Address 3 D0 D1 D2 D3 D3 Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required. Figure 1. Asynchronous Read Operation Synchronous (Burst) Read Operation The device is capable of performing burst read operations to improve total system data throughput. The 2, 4, and 8 double word accesses are configurable as linear burst accesses. All burst November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 27 Preliminary operations provide wrap around linear burst accesses. Additional options for all burst modes include initial access delay configurations (2–16 CLKs) Device configuration for burst mode operation is accomplished by writing the Configuration Register with the desired burst configuration information. Once the Configuration Register is written to enable burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchronous timing as defined in the Configuration Register. However, the user must recognize burst operations past the 256 byte Secured Silicon boundary returns invalid data. Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations results in the data remaining valid while OE# is at VIL, regardless of the number of CLK cycles applied to the device. Linear Burst Read Operations Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (See Table 30 for all valid burst output sequences). The IND/WAIT# pin transitions active (VIL) during the last transfer of data during a linear burst read before a wrap around, indicating that the system should initiate another ADV# to start the next burst access. If the system continues to clock the device, the next access wraps around to the starting address of the previous burst access. The IND/WAIT# signal remains inactive (floating) when not active. See Table 30 for a complete 32 data bus interface order. Table 30. 32- Bit Linear and Burst Data Order Data Transfer Sequence (Independent of the WORD# pin) Two Linear Data Transfers Output Data Sequence (Initial Access Address) 0-1 (A0 = 0) 1-0 (A0 = 1) 0-1-2-3 (A0:A-1/A1-A0 = 00) 1-2-3-0 (A0:A-1/A1-A0 = 01) 2-3-0-1 (A:A-1/A1-A0 = 10) 3-0-1-2 (A0:A-1/A1-A0 = 11) 0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000) 1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001) 2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010) 3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011) 4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100) 5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101) 6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110) 7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111) Four Linear Data Transfers Eight Linear Data Transfers CE# Control in Linear Mode The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal. Restarting a burst cycle is accomplished by taking CE# and ADV# to VIL. ADV# Control In Linear Mode The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE# and ADV# are at VIL and the device is configured for either linear burst mode operation. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst transfers are invalid until ADV# transitions to VIH before a clock edge, which initiates a new burst sequence. 28 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary RESET# Control in Linear Mode The RESET# pin immediately halts the linear burst access when taken to VIL. The DQ data bus signal float. Additionally, the Configuration Register contents are reset back to the default condition where the device is placed in asynchronous access mode. OE# Control in Linear Mode The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. Deasserting the OE# pin to VIH during a burst operation floats the data bus. However, the device continues to operate internally as if the burst sequence continues until the linear burst is complete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse. The DQ bus remains in the float state until OE# is taken to VIL. IND/WAIT# Operation in Linear Mode The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs the system that the last address of a burst sequence is on the DQ data bus. For example, if a 2-double-word linear burst access is enabled using a 16-bit DQ bus (WORD# = VIL), the IND/WAIT# signal transitions active on the second access. If the same scenario is used, the IND/WAIT# signal has the same delay and setup timing as the DQ pins. Also, the IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/WAIT# signal floats and is not driven. If OE# is at VIL, the IND/ WAIT# signal is driven at VIH until it transitions to VIL indicating the end of burst sequence. The IND/WAIT# signal timing and duration is (See Configuration Register on page 31 for more information). The following table lists the valid combinations of the Configuration Register bits that impact the IND/WAIT# timing. Table 31. DOC 0 0 WC 0 1 CC 1 1 Valid Configuration Register Bit Definition for IND/WAIT# Definition IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLD edge IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge VIH CE# VIL CLK 3 Clock Delay ADV# Addresses Data Address 1 Address 1 Latched Address 2 Invalid D1 D2 D3 D0 OE# IND/WAIT# Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wraparound. Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 29 Preliminary Burst Access Timing Control In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial access delay, delivery of data on the CLK edge, and the length of time data is held. Initial Burst Access Delay Control The device contains options for initial access delay of a burst access. The initial access delay has no effect on asynchronous read operations. Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid. The burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever comes first. (Table 32 describes the initial access delay configurations.) Table 32. Burst Initial Access Delay Initial Burst Access (CLK cycles) CR13 0 0 0 0 0 0 0 0 CR12 0 0 0 0 1 1 1 1 CR11 0 0 1 1 0 0 1 1 1st CLK CR10 0 1 0 1 0 1 0 1 2nd CLK 3rd CLK 40 MHz (0J), 56 MHz (0M), 66 MHz (0P), 75 MHz (0R, 32 Mb only) 2 3 4 5 6 7 8 9 4th CLK 5th CLK CLK ADV# Addresses DQ31-DQ03 DQ31-DQ04 DQ31-DQ05 Notes: 1. 2. 3. 4. 5. Burst access starts with a rising CLK edge and when ADV# is active. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge. CR [13-10] = 1 or three clock cycles CR [13-10] = 2 or four clock cycles CR [13-10] = 3 or five clock cycles Valid Address Address 1 Latched Three CLK Delay Four CLK Delay D0 D1 D0 D2 D1 D0 D3 D2 D1 D4 D3 D2 Five CLK Delay Figure 3. Initial Burst Delay Control Burst CLK Edge Data Delivery The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6) is set to 1, and is the default configuration. Burst Data Hold Control The device is capable of holding data for one CLKs. The default configuration is to hold data for one CLK and is the only valid state. 30 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Asserting RESET# During A Burst Access If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. See Hardware Reset (RESET#) on page 71 for more information on the RESET# function. Configuration Register The device contains a Configuration Register for configuring read accesses. The Configuration Register is accessed by the Configuration Register Read and the Configuration Register Write commands. The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the Configuration Register commands. The Configuration Register is readable any time, however, writing the Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If the user attempts to write the Configuration Register while the Embedded Algorithm™ is active, the write operation is ignored and the contents of the Configuration Register remain unchanged. The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation, DQ31–DQ16 returns all zeroes. Table 33 shows the Configuration Register. Also, Configuration Register reads operate the same as Autoselect command reads. When the command is issued, the bank address is latched along with the command. Reads operations to the bank that was specified during the Configuration Register read command return Configuration Register contents. Read operations to the other bank return flash memory data. Either bank address is permitted when writing the Configuration Register read command. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 31 Preliminary Table 33. CR15 RM CR14 ASD CR13 IAD3 Configuration Register Definitions CR12 IAD2 CR11 IAD1 CR10 IAD0 CR9 DOC CR8 WC CR7 BS CR6 CC CR5 Reserved CR4 Reserved CR3 Reserved CR2 BL2 CR1 BL1 CR0 BL0 Configuration Register CR15 = Read Mode (RM) 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) CR14 = Reserved for Future Enhancements 0 = ASM enable 1 = ASM disable CR13–CR10 = Automatic Sleep Mode Disable Speed Options 40, 56, and 66 MHz: 0000 0001 0010 0011 = = = = 2 3 4 5 CLK CLK CLK CLK cycle cycle cycle cycle initial initial initial initial burst burst burst burst access access access access delay delay delay delay 0100 0101 0110 0111 = = = = 6 7 8 9 CLK CLK CLK CLK cycle cycle cycle cycle initial initial initial initial burst burst burst burst access access access access delay delay delay delay—Default CR9 = Data Output Configuration (DOC) 0 = Hold Data for 1-CLK cycle—Default 1 = Reserved CR8 = IND/WAIT# Configuration (WC) 0 = IND/WAIT# Asserted During Delay—Default 1 = IND/WAIT# Asserted One Data Cycle Before Delay CR7 = Burst Sequence (BS) 0 = Reserved 1 = Linear Burst Order—Default CR6 = Clock Configuration (CC) 0 = Reserved 1 = Burst Starts and Data Output on Rising Clock Edge—Default CR5–CR3 = Reserved For Future Enhancements (R) These bits are reserved for future use. Set these bits to 0. CR2–CR0 = Burst Length (BL2–BL0) 000 001 010 011 100 101 110 = = = = = = = Reserved, burst accesses disabled (asynchronous reads only) 64 bit (8-byte) Burst Data Transfer - x32 Linear 128 bit (16-byte) Burst Data Transfer - x32 Linear 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default) Reserved, burst accesses disabled (asynchronous reads only) Reserved, burst accesses disabled (asynchronous reads only) Reserved, burst accesses disabled (asynchronous reads only) 32 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Table 34. Configuration Register After Device Reset CR15 RM 1 CR14 Reserve 0 CR13 IAD3 0 CR12 IAD2 1 CR11 IAD1 1 CR10 IAD0 1 CR9 DOC 0 CR8 WC 0 CR7 BS 1 CR6 CC 1 CR5 Reserve 0 CR4 Reserve 0 CR3 Reserve 0 CR2 BL2 1 CR1 BL1 0 CR0 BL0 0 Initial Access Delay Configuration The frequency configuration informs the device of the number of clocks that must elapse after ADV# is driven active before data is available. This value is determined by the input clock frequency. Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups Sector and Sector Groups The distinction between sectors and sector groups is fundamental to sector protection. Sector are individual sectors that can be individually sector protected/unprotected. These are the outermost 4 Kword boot sectors, that is, SA0 to SA7 and SA70 to SA77. See Table 35 on page 35, Table 23 on page 19, Table 24 on page 20, Table 25 on page 21, and Table 26 on page 22. Sector groups are a collection of three or four adjacent 32 kword sectors. For example, sector group SG8 is comprised of sector SA8 to SA10. When any sector in a sector group is protected/ unprotected, every sector in that group is protection/unprotected. See Table 35, Table 23, Table 24, Table 25, and Table 26. Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. WP# Hardware Protection A write protect pin that can prevent program or erase to the two outermost 8 Kbytes sectors in the 75% bank. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method is used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This permanently sets the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This permanently sets the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit is set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 33 Preliminary the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked—A sector is protected and cannot be changed. Dynamically Locked—The sector is protected and can be changed by a simple command Unlocked—The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of bits are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four sectors (see the sector address tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB eras- ing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to 1, the PPBs cannot be changed. When cleared (0), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is 0. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs is set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to 1. Setting the PPB Lock disables all program and erase 34 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into the current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP# write protect pin adds a final level of hardware protection to the two outermost 8 Kbytes sectors in the 75% bank. When this pin is low it is not possible to change the contents of these two sectors. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a powercycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again, locks the PPBs and the device operates normally again. Note: To achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 35. DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 PPB Lock 0 1 0 0 0 1 1 1 Sector Protection Schemes Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable Table 35 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that an unauthorized user could not place the device in password protection mode. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 35 Preliminary Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each password check. This delay is intended to stop any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. One method of choosing a password would be to correlate it to the unique Electronic Serial Number (ESN) of the particular flash device. Another method could generate a database where all the passwords are stored, each of which correlates to a serial number on the device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2) It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see Password Verify Command). The password function 36 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The device features a hardware protection option using a write protect pin that prevents programming or erasing, regardless of the state of the sector’s Persistent or Dynamic Protection Bits. The WP# pin is associated with the two outermost 8Kbytes sectors in the 75% bank. The WP# pin has no effect on any other sector. When WP# is taken to VIL, programming and erase operations of the two outermost 8 Kbytes sectors in the 75% bank are disabled. By taking WP# back to VIH, the two outermost 8 Kbytes sectors are enabled for program and erase operations, depending upon the status of the individual sector Persistent or Dynamic Protection Bits. If either of the two outermost sectors Persistent or Dynamic Protection Bits are programmed, program or erase operations are inhibited. If the sector Persistent or Dynamic Protection Bits are both erased, the two sectors are available for programming or erasing as long as WP# remains at VIH. The user must hold the WP# pin at either VIH or VIL during the entire program or erase operation of the two outermost sectors in the 75% bank. Secured Silicon OTP Sector and Simultaneous Operation The Secured Silicon Sector is 256 Kbytes and is located in the Small Bank. For S29CD016G and S29CD032G devices. Spansion programs and permanently locks the Secured Silicon sector with Unique device identification. Please contact your sales representative for the Electronic Marking information. Since the Secured Silicon is permanent protected by Spansion, during Simultaneous Operation, the Secured Silicon sector cannot be erased or reprogrammed. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit back to a 1. If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection Mode. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal erase/program circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 37 Preliminary system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH). Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power-up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. VCC and VIO Power-up And Power-down Sequencing The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach the operating voltages. Once, VCC and VIO attain the operating voltages, de-assertion of RESET# to VIH is permitted. 38 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 13–16. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 13–16. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.spansion.com. Alternatively, contact an AMD representative for copies of these documents. Table 36. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h CFI Query Identification String Description Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 37. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0023h 0027h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0007h 0000h CFI System Interface String Description VCC Min. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt VCC Max. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single word/doubleword program 2N µs Typical timeout for Min. size buffer program 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for word/doubleword program 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 39 Preliminary Table 38. Addresses 27h Data 0016h Device Size = 2N byte Device Geometry Definition Description 28h 29h 0005h 0000h Flash Device Interface description (for complete description, please refer to CFI publication 100) 0000 = x8-only asynchronous interface 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via BYTE# with asynchronous interface 0003 = x 32-only asynchronous interface 0005 = supports x16 and x32 via WORD# with asynchronous interface Max. number of byte in multi-byte program = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 0000h 0000h 0003h 0007h 0000h 0020h 0000h 003Dh* 0000h Erase Block Region 2 Information 0000h (refer to the CFI specification or CFI publication 100) 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) * On 16 Mb device, data at address 31h is 1Dh. 40 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Table 39. CFI Primary Vendor-Specific Extended Query Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string PRI Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (DQ1, DQ0) 00 = Required, 01 = Not Required Silicon Revision Number (DQ5–DQ2 0000 = CS49 0001 = CS59 0010 = CS99 0011 = CS69 0100 = CS119 Erase Suspend (1 byte) 00 = Not Supported 01 = To Read Only 02 = To Read and Write Sector Protect (1 byte) 00 = Not Supported, X = Number of sectors in per group Temporary Sector Unprotect 00h = Not Supported, 01h = Supported Sector Protect/Unprotect scheme (1 byte) 01 =29F040 mode, 02 = 29F016 mode 03 = 29F400 mode, 04 = 29LV800 mode 05 = 29BDS640 mode (Software Command Locking) 06 = BDD160 mode (New Sector Protect) 07 = 29LV800 + PDL128 (New Sector Protect) mode Simultaneous Read/Write (1 byte) 00h = Not Supported, X = Number of sectors in all banks except Bank 1 Burst Mode Type 00h = Not Supported, 01h = Supported Page Mode Type 00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) ACC (Acceleration) Supply Maximum 00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) Top/Bottom Boot Sector Flag (1 byte) 00h = Uniform device, no WP# control, 01h = 8 x 8 Kb sectors at top and bottom with WP# control 02h = Bottom boot device 03h = Top boot device 04h = Uniform, Bottom WP# Protect 05h = Uniform, Top WP# Protect If the number of erase block regions = 1, then ignore this field Program Suspend 00 = Not Supported 01 = Supported Write Buffer Size 2(N+1) word(s) Bank Organization (1 byte) 00 = If data at 4Ah is zero XX = Number of banks Bank 1 Region Information (1 byte) XX = Number of Sectors in Bank 1 Bank 2 Region Information (1 byte) XX = Number of Sectors in Bank 2 Bank 3 Region Information (1 byte) XX = Number of Sectors in Bank 3 Bank 4 Region Information (1 byte) XX = Number of Sectors in Bank 4 Description 45h 0004h 46h 0002h 47h 48h 0001h 0000h 49h 0006h 4Ah 4Bh 4Ch 4Dh 4Eh 0037h 0001h 0000h 00B5h 00C5h 4Fh 0001h 50h 51h 57h 58h 59h 5Ah 5Bh 0001h 0000h 0002h 0017h 0037h 0000h 0000h November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 41 Preliminary Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 41 on page 54 and Table 42 on page 55 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. See AC Characteristics on page 67 for timing diagrams. Reading Array Data in Non-burst Mode The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Sector Erase and Program Suspend Command on page 47 for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See PPB Lock Bit Set Command on page 51. Asynchronous Read Operation (Non-Burst) on page 27 for more information. See Sector Erase and Program Resume Command on page 49 for more information on this mode. Reading Array Data in Burst Mode The device is capable of very fast Burst mode read operations. The configuration register sets the read configuration, burst order, frequency configuration, and burst length. Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are ignored. The device operates like a conventional Flash device. Data is available tACC/tCE nanoseconds after address becomes stable, CE# become asserted. The device enters the burst mode by enabling synchronous burst reads in the configuration register. The device exits burst mode by disabling synchronous burst reads in the configuration register. (See Command Definitions on page 42). The RESET# command does not terminate the Burst mode. System reset (power on reset) terminates the Burst mode. The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output Enable (OE#) to control normal read and write operations. Moreover, three additional control pins were added to allow easy interface with minimal glue logic to a wide range of microprocessors / microcontrollers for high performance Burst read capability. These additional pins are Address Valid (ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst mode read operation is a synchronous operation tied to the edge of the clock. The microprocessor / microcontroller supplies only the initial address, all subsequent addresses are automatically generated by the device with a timing defined by the Configuration Register definition. The Burst read cycle consists of an address phase and a corresponding data phase. During the address phase, the Address Valid (ADV#) pin is asserted (taken Low) for one clock period. Together with the edge of the CLK, the starting burst address is loaded into the internal Burst Address Counter. The internal Burst Address Counter can be configured to either 2, 4, and 8 double word linear burst, with or without wrap around. See I nitial Access Delay Configuration on page 33. 42 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary During the data phase, the first burst data is available after the initial access time delay defined in the Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK triggers the output data with the burst output delay and sequence defined in the Configuration Register. Table 41 on page 54 and Table 42 on page 55 show all the commands executed by the device. The device automatically powers up in the read/reset state. It is not necessary to issue a read/ reset command after power-up or hardware reset. Read/Reset Command After power-up or hardware reset, the device automatically enter the read state. It is not necessary to issue the reset command after power-up or hardware reset. Standard microprocessor cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted since the Configuration Register is at its reset state with burst accesses disabled. The Reset command is executed when the user needs to exit any of the other user command sequences (such as autoselect, program, chip erase, etc.) to return to reading array data. There is no latency between executing the Reset command and reading array data. The Reset command does not disable the Secured Silicon sector if it is enabled. This function is only accomplished by issuing the Secured Silicon Sector Exit command. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to VID. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect Command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The bank address (BA) is latched during the autoselect command sequence write operation to distinguish which bank the Autoselect command references. Reading the other bank after the Autoselect command is written results in reading array data from the other bank and the specified address. Following the command write, a read cycle from address (BA)XX00h retrieves the manufacturer code of (BA)XX01h. Three sequential read cycles at addresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID (see Table 41). (The Autoselect Command requires the user to execute the Read/Reset command to return the device back to reading the array contents.) Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 41 on page 54 and Table 42 on page 55 show the address and data requirements for the program command sequence. During the Embedded Program algorithm, the system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. (See Write Operation Status on page 56 for information on these status bits.) When the Embedded Program algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that an address change is required to begin read valid array data. Except for Program Suspend, any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 43 Preliminary operation. The command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. Accelerated Program Command The Accelerated Chip Program mode is designed to improve the Word or Double Word programming speed. Improving the programming speed is accomplished by using the ACC pin to supply both the wordline voltage and the bitline current instead of using the VPP pump and drain pump, which is limited to 2.5 mA. Because the external ACC pin is capable of supplying significantly large amounts of current compared to the drain pump, all 32 bits are available for programming with a single programming pulse. This is an enormous improvement over the standard 5-bit programming. If the user is able to supply an external power supply and connect it to the ACC pin, significant time savings are realized. In order to enter the Accelerated Program mode, the ACC pin must first be taken to VHH (12 V ± 0.5 V) and followed by the one-cycle command with the program address and data to follow. The Accelerated Chip Program command is only executed when the device is in Unlock Bypass mode and during normal read/reset operating mode. In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1. The Accelerated Program command is not permitted if the Secured Silicon sector is enabled. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 39 on page 41 and Table 41 on page 54 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 4 on page 45 illustrates the algorithm for the program operation. See Erase/Program Operations on page 73 for parameters, and to Figure 21 on page 74 and Figure 22 on page 74 for timing diagrams. 44 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 41 and Table 42 for program command sequence. Figure 4. Program Operation Unlock Bypass Entry Command The Unlock Bypass command, once issued, is used to bypass the unlock sequence for program, chip erase, and CFI commands. This feature permits slow PROM programmers to significantly improve programming/erase throughput since the command sequence often requires microseconds to execute a single write operation. Therefore, once the Unlock Bypass command is issued, only the two-cycle program and erase bypass commands are required. The Unlock Bypass Command is ignored if the Secured Silicon sector is enabled. To return back to normal operation, the Unlock Bypass Reset Command must be issued. The following four sections describe the commands that may be executed within the unlock bypass mode. Unlock Bypass Program Command The Unlock Bypass Program command is a two-cycle command that consists of the actual program command (A0h) and the program address/data combination. This command does not require the two-cycle unlock sequence since the Unlock Bypass command was previously issued. As with the standard program command, multiple Unlock Bypass Program commands can be issued once the Unlock Bypass command is issued. To return back to standard read operations, the Unlock Bypass Reset command must be issued. The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 45 Preliminary Unlock Bypass Chip Erase Command The Unlock Bypass Chip Erase command is a 2-cycle command that consists of the erase setup command (80h) and the actual chip erase command (10h). This command does not require the two-cycle unlock sequence since the Unlock Bypass command was previously issued. Unlike the standard erase command, there is no Unlock Bypass Erase Suspend or Erase Resume commands. To return back to standard read operations, the Unlock Bypass Reset command must be issued. The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled. Unlock Bypass CFI Command The Unlock Bypass CFI command is available for PROM programmers and target systems to read the CFI codes while in Unlock Bypass mode. See Common Flash Interface (CFI) Command on page 50 for specific CFI codes. To return back to standard read operations, the Unlock Bypass Reset command must be issued. The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled. Unlock Bypass Reset Command The Unlock Bypass Reset command places the device in standard read/reset operating mode. Once executed, normal read operations and user command sequences are available for execution. The Unlock Bypass Program Command is ignored if the Secured Silicon sector is enabled. Chip Erase Command The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single command. Chip erase is a six-bus cycle operation. There are two unlock write cycles, followed by writing the erase set-up command. Two more unlock write cycles are followed by the chip erase command. Chip erase does not erase protected sectors. The chip erase operation initiates the Embedded Erase algorithm, which automatically preprograms and verifies the entire memory to an all zero pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Note that a hardware reset immediately terminates the programming operation. The command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. The Embedded Erase algorithm erase begins on the rising edge of the last WE# or CE# pulse (whichever occurs first) in the command sequence. The status of the erase operation is determined three ways: Data# polling of the DQ7 pin (See DQ7: Data# Polling on page 56) Checking the status of the toggle bit DQ6 (See DQ6: Toggle Bit I on page 58) Checking the status of the RY/BY# pin (See RY/BY#: Ready/Busy# on page 56) Once erasure begins, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched. Note that an address change is required to begin read valid array data. Figure 5 on page 48 illustrates the Embedded Erase Algorithm. See the E rase/Program Operations on page 73 for parameters, and Figure 21 and Figure 22 for timing diagrams. Sector Erase Command The Sector Erase command is used to erase individual sectors or the entire flash memory contents. Sector erase is a six-bus cycle operation. There are two unlock write cycles, followed by writing the erase set-up command. Two more unlock write cycles are then followed by the erase command (30h). The sector address (any address location within the desired sector) is latched 46 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary on the falling edge of WE# or CE# (whichever occurs last) while the command (30h) is latched on the rising edge of WE# or CE# (whichever occurs first). Specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as described above, and then following it by additional writes of only the last cycle of the Sector Erase command to addresses or other sectors to be erased. The time between Sector Erase command writes must be less than 80 µs, otherwise the command is rejected. It is recommended that processor interrupts be disabled during this time to guarantee this critical timing condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 80 µs from the rising edge of the last WE# (or CE#) initiates the execution of the Sector Erase command(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset. Once the 80 µs window times out and erasure begins, only the Erase Suspend command is recognized (See Sector Erase and Program Suspend Command on page 47 and Sector Erase and Program Resume Command on page 49). If that occurs, the sector erase command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. Loading the sector erase registers may be done in any sequence and with any number of sectors. Sector erase does not require the user to program the device prior to erase. The device automatically preprograms all memory locations, within sectors to be erased, prior to electrical erase. When erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. The system is not required to provide any controls or timings during sector erase operations. The Erase Suspend and Erase Resume commands may be written as often as required during a sector erase operation. Automatic sector erase operations begin on the rising edge of the WE# or CE# pulse of the last sector erase command issued, and once the 80 µs time-out window expires. The status of the sector erase operation is determined three ways: Data# polling of the DQ7 pin Checking the status of the toggle bit DQ6 Checking the status of the RY/BY# pin Further status of device activity during the sector erase operation is determined using toggle bit DQ2 (See DQ2: Toggle Bit II on page 58). When the Embedded Erase algorithm is complete, the device returns to reading array data, and addresses are no longer latched. Note that an address change is required to begin read valid array data. Figure 5 on page 48 illustrates the Embedded™ Erase Algorithm, using a typical command sequence and bus operation. See the Erase/Program Operations on page 73 for parameters, and to Figure 21 and Figure 22 for timing diagrams. Sector Erase and Program Suspend Command The Sector Erase and Program Suspend command allows the user to interrupt a Sector Erase or Program operation and perform data read or programs in a sector that is not being erased or to the sector where a programming operation was initiated. This command is applicable only during the Sector Erase and Programming operation, which includes the time-out period for Sector Erase. Sector Erase and Program Suspend Operation Mechanics The Sector Erase and Program Suspend command is ignored if written during the execution of the Chip Erase operation or Embedded Program Algorithm (but resets the chip if written improperly during the command sequences). Writing the Sector Erase and Program command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Once in Erase Suspend, the device is available for reading (note that in the November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 47 Preliminary START Write Erase Command Sequence Data Poll from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1.See Table 41 and Table 42 for erase command sequence. 2.See DQ3: Sector Erase Timer for more information. Figure 5. Erase Operation Erase Suspend mode, the Reset command is not required for read operations and is ignored) or program operations in sectors not being erased. Any other command written during the Erase Suspend mode is ignored, except for the Sector Erase and Program Resume command. Writing the Erase and Program Resume command resumes the sector erase operation. The bank address of the erase suspended bank is required when writing this command If the Sector Erase and Program Suspend command is written during a programming operation, the device suspends programming operations and allows only read operations in sectors not selected for programming. Further nesting of either erase or programming operations is not permitted. Table 40 summarizes permissible operations during Erase and Program Suspend. (A busy sector is one that is selected for programming or erasure.): Table 40. Sector Busy Sector Non-busy sectors Allowed Operations During Erase/Program Suspend Program Suspend Program Resume Read Only Erase Suspend Erase Resume Read or Program When the Sector Erase and Program Suspend command is written during a Sector Erase operation, the chip takes between 0.1 µs and 20 µs to actually suspend the operation and go into the erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sector that is not erase suspended. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that were not erase suspended. Polling DQ6 on two immediately consecutive reads from a given address provides the system with the ability to determine if the device is in Erase or Program Suspend. Before the device enters Erase or Program Suspend, the DQ6 pin toggles between two immediately consecutive reads from the same address. After the device enters Erase suspend, DQ6 stops toggling between two im- 48 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary mediately consecutive reads to the same address. During the Sector Erase operation and also in Erase suspend mode, two immediately consecutive readings from the erase-suspended sector causes DQ2 to toggle. DQ2 does not toggle if reading from a non-busy (non-erasing) sector (stored data is read). No bits are toggled during program suspend mode. Software must keep track of the fact that the device is in a suspended mode. After entering the erase-suspend-read mode, the system may read or program within any nonsuspended sector: A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase suspend command is issued; read operations thereafter return array data. Read operations from the other bank return array data with no latency. A program operation while in the erase suspend mode is the same as programming in the regular program mode, except that the data must be programmed to a sector that is not erase suspended. Write operation status is obtained in the same manner as a normal program operation. Sector Erase and Program Resume Command The Sector Erase and Program Resume command (30h) resumes a Sector Erase or Program operation that was suspended. Any further writes of the Sector Erase and Program Resume command ignored. However, another Sector Erase and Program Suspend command can be written after the device resumes sector erase operations. Note that until a suspended program or erase operation resumes, the contents of that sector are unknown. The Sector Erase and Program Resume Command is ignored if the Secured Silicon sector is enabled. Configuration Register Read Command The Configuration Register Read command is used to verify the contents of the Configuration Register. Execution of this command is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration Register Read command is preceded by the standard two-cycle unlock sequence, followed by the Configuration Register Read command (C6h), and finally followed by performing a read operation to the bank address specified when the C6h command was written. Reading the other bank results in reading the flash memory contents. The contents of the Configuration Register are place on DQ15–DQ0. Contents of DQ31–DQ16 are XXXXh and should be ignored. The user should execute the Read/Reset command to place the device back in standard user operation after executing the Configuration Register Read command. The Configuration Register Read Command is fully operational if the Secured Silicon sector is enabled. Configuration Register Write Command The Configuration Register Write command is used to modify the contents of the Configuration Register. Execution of this command is only allowed while in user mode and is not available during Unlock Bypass mode or during Security mode. The Configuration Register Write command is preceded by the standard two-cycle unlock sequence, followed by the Configuration Register Write command (D0h), and finally followed by writing the contents of the Configuration Register to any address. The contents of the Configuration Register are placed on DQ31–DQ0. The contents of DQ31–DQ16 are XXXXh and are ignored. Writing the Configuration Register while an Embedded Algorithm™ or Erase Suspend modes are executing results in the contents of the Configuration Register not being updated. The Configuration Register Read Command is fully operational if the Secured Silicon sector is enabled. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 49 Preliminary Common Flash Interface (CFI) Command The Common Flash Interface (CFI) command provides device size, geometry, and capability information directly to the users system. Flash devices that support CFI, have a Query Command that returns information about the device to the system. The Query structure contents are read at the specific address locations following a single system write cycle where: A 98h query command code is written to 55h address location within the device’s address space The device is initially in any valid read state, such as Read Array or Read ID Data Other device statistics may exist within a long sequence of commands or data input; such sequences must first be completed or terminated before writing of the 98H Query command, otherwise invalid Query data structure output may result. Note that for data bus bits greater than DQ7 (DQ31–DQ8), the valid Query access code contains all zeroes (0s) in the upper DQ bus locations. Thus, the 16-bit Query command code is 0098h and the 32-bit Query command code is 00000098h. To terminate the CFI operation, it is necessary to execute the Read/Reset command. The CFI command is not permitted if the Secured Silicon sector is enabled and Simultaneous Read/Write operation is disabled once the command is entered. See Common Flash Interface (CFI) Command on page 50 for the specific CFI command codes. Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Depending upon the state of the WORD# pin, multiple Password Program Commands are required. For a x32 bit data bus, 2 Password Program commands are required. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Read/Write operation is disabled. Read operations to any memory location returns the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a 0. The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the Secured Silicon sector is enabled. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device always drives all F’s onto the DQ data bus. The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, Simultaneous Read/Write operation is disabled when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. 50 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Password Protection Mode Locking Bit Program command is permitted if the Secured Silicon sector is enabled. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Persistent Sector Protection Mode Locking Bit Program command is permitted if the Secured Silicon sector is enabled. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the Secured Silicon sector is enabled. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A19–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command. The DYB Write command is permitted if the Secured Silicon sector is enabled. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command is ignored. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 51 Preliminary The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data bus. A0 is used to determine whether the 32 bit data quantity is used to match the upper 32 bits or lower 32 bits. Writing the Password Unlock command is address order specific. In other words, for the x32 data bus configuration, the lower 32 bits of the password are written first and then the upper 32 bits of the password are written. Writing out of sequence results in the Password Unlock not returning a match with the password and the PPB Lock Bit remains set. Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the device is busy. Also, reading the small bank (25% bank) results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the large bank (75% bank) returns actual array data. Approximately 1uSec is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. The second Password Unlock command is the final command before the PPB Lock Bit is cleared (assuming a valid password). As with the first Password Unlock command, the RY/BY# signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands (2 for x32 bus), the order, and when to read the PPB Lock bit to confirm successful password unlock The Password Unlock command is permitted if the Secured Silicon sector is enabled. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A19–A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command does not execute and the command times-out without programming the PPB. The host system must determine whether a PPB is fully programmed by noting the status of DQ0 in the sixth cycle of the PPB Program command. If DQ0 = 0, the entire six-cycle PPB Program command sequence must be reissued until DQ0 = 1. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command does not execute and the command timesout without erasing the PPBs. The host system must determine whether all PPB was fully erased by noting the status of DQ0 in the sixth cycle of the All PPB Erase command. If DQ0 = 1, the entire six-cycle All PPB Erase command sequence must be reissued until DQ0 = 1. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the Secured Silicon sector is enabled. DYB Write The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. 52 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank address is latched when the command is written. The DYB Write command is permitted if the Secured Silicon sector is enabled. PPB Lock Bit Set The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank address is latched when the command is written. The PPB Lock command is permitted if the Secured Silicon sector is enabled. DYB Status The programming of the DYB for a given sector can be verified by writing a DYB status verify command to the device. PPB Status The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. Non-volatile Protection Bit Program And Erase Flow The device uses a standard command sequence for programming or erasing the Secured Silicon Sector Protection, Password Locking, Persistent Sector Protection Mode Locking, or Persistent Protection Bits. Unlike devices that have the Single High Voltage Sector Unprotect/Protect feature, the device has the standard two-cycle unlock followed by 60h, which places the device into nonvolatile bit program or erase mode. Once the mode is entered, the specific non-volatile bit status is read on DQ0. Figure 4 on page 45 shows a typical flow for programming the non-volatile bit and Figure 5 on page 48 shows a typical flow for erasing the non-volatile bits. The Secured Silicon Sector Protection, Password Locking, Persistent Sector Protection Mode Locking bits are not erasable after they are programmed. However, the PPBs are both erasable and programmable (depending upon device security). Unlike Single High Voltage Sector Protect/Unprotect, the A6 pin no longer functions as the program/erase selector nor the program/erase margin enable. Instead, this function is accomplished by issuing the specific command for either program (68h) or erase (60h). In asynchronous mode, the DQ6 toggle bit indicates whether the program or erase sequence is active. (In synchronous mode, ADV# indicates the status.) If the DQ6 toggle bit toggles with either OE# or CE#, the non-volatile bit program or erase operation is in progress. When DQ6 stops toggling, the value of the non-volatile bit is available on DQ0. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 53 Preliminary Table 41. Command (Notes) Cycles First Addr RA XXX 555 Data RD F0 AA Memory Array Command Definitions Bus Cycles (Notes 1–4) Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Read (5) Reset (6) Manufacturer ID Autoselect (7) 1 1 4 2AA 55 555 90 BA+X00 01 09 for 32 Mb 36 or 08 for 16 Mb Device ID (11) 6 555 AA 2AA 55 555 90 BA+X01 7E BA+X0E BA+X0F 00/01 Program Chip Erase Sector Erase Program/Erase Suspend (12) Program/Erase Resume (13) CFI Query (14, 15) Accelerated Program (16) Configuration Register Verify (15) Configuration Register Write (17) Unlock Bypass Entry (18) Unlock Bypass Program (18) Unlock Bypass Erase (18) Unlock Bypass CFI (14, 18) Unlock Bypass Reset (18) 4 6 6 1 1 1 2 3 4 3 2 2 1 2 555 555 555 BA BA 55 XX 555 555 555 XX XX XX XX AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 2AA 2AA 2AA 55 55 55 555 555 555 A0 80 80 PA 555 555 PD AA AA 2AA 2AA 55 55 555 SA 10 30 PA 2AA 2AA 2AA PA XX PD 55 55 55 PD 10 BA+555 555 555 C6 D0 20 BA+XX XX RD WD XX 00 RA = Read Address (Amax–A0). RD = Read Data. Data DQmax–DQ0 at address location RA. SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command. WD = Write Data. See Configuration Register on page 31 definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Legend: BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command. PA = Program Address (Amax–A0). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. 2. 3. 4. See Table 27 on page 23 for description of bus operations. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or device ID information. See Autoselect Command on page 43 for more information. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock Bypass Reset command must be executed to return to normal operation. This command is ignored during any embedded program, erase or suspended operation. 10. Valid read operations include asynchronous and burst read mode operations. 11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Program/Erase Suspend mode. The Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. Asynchronous read operations. 16. ACC must be at VID during the entire operation of this command. 17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. 5. 6. 7. 8. 9. 54 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Table 42. Command (Notes) Cycles First Addr XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 Data F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA Sector Protection Command Definitions Bus Cycles (Notes 1 – 4) Second Addr Data Third Addr Data Addr Fourth Data Fifth Addr Data Sixth Addr Data Reset Secured Silicon Sector Entry Secured Silicon Sector Exit Secured Silicon Protection Bit Status Password Program (5, 7, 8) Password Verify Password Unlock (7, 8) PPB Program (5, 6) All PPB Erase (5, 9, 10) PPB Status (11, 12) PPB Lock Bit Set PPB Lock Bit Status DYB Write (7) DYB Erase (7) DYB Status (12) PPMLB Program (5, 6) PPMLB Status (5) SPMLB Program (5, 6) SPMLB Status (5) 1 3 4 6 4 4 5 6 6 4 3 4 4 4 4 6 6 6 6 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 BA+555 555 BA+555 555 555 BA+555 555 555 555 555 88 90 60 38 C8 28 60 60 90 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 SL RD(0) PL 48 PL RD(0) XX OW PWA[0-1] PWA[0-1] PWA[0-1] SG+WP WP SA+X02 00 RD(0) PWD[0-1] PWD[0-1] PWD[0-1] 68 60 00/01 SG+WP WP 48 40 SG+WP WP RD(0) RD(0) Legend: DYB = Dynamic Protection Bit OW = Address (A5–A0) is (011X10). PPB = Persistent Protection Bit PWA = Password Address. A0 selects between the low and high 32-bit portions of the 64-bit Password PWD = Password Data. Must be written over two cycles. PL = Password Protection Mode Lock Address (A5–A0) is (001X10) RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if unprotected, DQ0 = 0. RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command. SG = Sector Group Address BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command. SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10) WP = PPB Address (A5–A0) is (111010) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit Notes: 1. 2. 3. 4. See Table 27 on page 23 for description of bus operations. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. The reset command returns the device to reading the array. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit is fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. Data is latched on the rising edge of WE#. 8. The entire four bus-cycle sequence must be entered for each portion of the password. 9. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits were fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. 5. 6. 7. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 55 Preliminary Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 43 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. DQ7: Data# Polling The device features a Data# polling flag as a method to indicate to the host system whether the embedded algorithms are in progress or are complete. During the Embedded Program Algorithm, an attempt to read the bank in which programming was initiated produces the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device produces the true last data written to DQ7. Note that DATA# polling returns invalid data for the address being programmed or erased. For example, the data read for an address programmed as 0000 0000 1000 0000b, returns XXXX XXXX 0XXX XXXXb during an Embedded Program operation. Once the Embedded Program Algorithm is complete, the true data is read back on DQ7. Note that at the instant when DQ7 switches to true data, the other bits may not yet be true. However, they are all true data on the next read from the device. Please note that Data# polling may give misleading status when an attempt is made to write to a protected sector. For chip erase, the Data# polling flag is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Data# polling is valid after the last rising edge of the sector erase WE# pulse. Data# polling must be performed at sector addresses within any of the sectors being erased and not a sector that is a protected sector. Otherwise, the status may not be valid. DQ7 = 0 during an Embedded Erase Algorithm (chip erase or sector erase operation), but returns a 1 after the operation completes because it drops back into read mode. In asynchronous mode, just prior to the completion of the Embedded Algorithm operations, DQ7 may change asynchronously while OE# is asserted low. (In synchronous mode, ADV# exhibits this behavior.) The status information may be invalid during the instance of transition from status information to array (memory) data. An extra validity check is therefore specified in the data polling algorithm. The valid array data on DQ31–DQ0 is available for reading on the next successive read attempt. The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, Erase Suspend-Program mode, or sector erase time-out. If the user attempts to write to a protected sector, Data# polling is activated for about 1 µs: the device then returns to read mode, with the data from the protected sector unchanged. If the user attempts to erase a protected sector, Toggle Bit (DQ6) is activated for about 150 µs; the device then returns to read mode, without having erased the protected sector. Table 43 shows the outputs for Data# Polling on DQ7. Figure 6 on page 57 shows the Data# Polling algorithm. Figure 23 shows the timing diagram for synchronous status DQ7 data polling. RY/BY#: Ready/Busy# The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or completed. If the output is low, the device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device does not accept any additional program or erase commands with the exception of the Erase suspend command. If the device enters Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse 56 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE# pulse. START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL Notes: 1. 2. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5 PASS Figure 6. Data# Polling Algorithm If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is completed in a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is an open drain. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 57 Preliminary Table 43 shows the outputs for RY/BY#. Figures 15, 19, and 21 show RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, two immediately consecutive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (See DQ7: Data# Polling on page 56). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 43 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 59 explains the algorithm. Figure 24 shows the toggle bit timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. Also see DQ2: Toggle Bit II on page 58. Figure 24 shows the timing diagram for synchronous toggle bit status. DQ2: Toggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system performs two immediately consecutive reads at addresses within those sectors that were selected for erasure. (For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, ADV# is used.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 43 to compare outputs for DQ2 and DQ6. Toggle bit algorithm in is shown in Figure 7 in flowchart form, and the algorithm is explained in Reading Toggle Bits DQ6/DQ2 on page 59. Also see DQ6: Toggle Bit I on page 58. Figure 24 shows the toggle bit timing diagram. Figure 25 shows the differences between DQ2 and DQ6 in graphical form. Figure 26 shows the timing diagram for synchronous DQ2 toggle bit status. 58 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Reading Toggle Bits DQ6/DQ2 Refer to Figure 24 for the following discussion. Whenever the system initially begins reading toggle bit status, it must perform two immediately consecutive reads of DQ7–DQ0 to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two immediately consecutive read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (See DQ5: Exceeded Timing Limits on page 60). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7). November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 59 Preliminary START Read Byte (DQ0-DQ7) Address = VA Read Byte (Note 1)(DQ0-DQ7) Address = VA DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ 0-DQ7) Adrdess = VA (Notes 1, 2) DQ6 = Toggle? No Yes FAIL Notes: 1. 2. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. PASS Figure 7. Toggle Bit Algorithm DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation exceeds the timing limits, DQ5 produces a 1. Under both these conditions, the system must issue the reset command to return the device to reading array data. 60 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands is always less than 50 µs. Also see Sector Erase Command on page 46. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 43 shows the outputs for DQ3. Table 43. Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Erase Suspend Mode Notes: 1. 2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits for more information. DQ7 and DQ2 require a valid address when reading status information. See DQ7: Data# Polling and DQ2: Toggle Bit II for further details. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 61 Preliminary Absolute Maximum Ratings Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +145°C VCC, VIO (Note 1, Note 5) . . . . . . . . . . . . . -0.5 V to + 3.0V (16Mb), -0.5V to + 2.75V (32Mb) ACC, A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V Address, Data, Control Signals Except CLK (Note 1, Note 6) . . . . . . . . . . . . -0.5V to 3.6V (16 Mb), –0.5 V to 2.75 V (32 Mb) All other pins (Note 1, Note 6). . . . . . . . . . . . -0.5V to 3.6V (16 Mb),–0.5 V to 2.75 V (32 Mb) Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on output and I/O pins is 3.6V (16Mb), 2.75V (32Mb). During voltage transitions output pins may overshoot to VCC + 2.0V for periods up to 20 ns. See Figure 9. Minimum DC input voltage on pins ACC, A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9 and OE# is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Parameter describes VIO power supply. Parameter describes I/O pin voltage tolerances. 2. 3. 4. 5. 6. 20 ns +0.8 V –0.5 V –2.0 V 20 ns 20 ns Figure 8. Maximum Negative Overshoot Waveform 20 ns V CC +2.0 V V CC +0.5 V 2.0 V 20 ns 20 ns Figure 9. Maximum Positive Overshoot Waveform 62 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Operating Ranges Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C VCC Supply Voltages VCC for 2.6 V regulated voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.50 V to 2.75 V VIO Supply Voltages VIO . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 V to 3.6 V (16 Mb), 1.65 V to 2.75 V (32 Mb) Note: Operating ranges define those limits between which the functionality of the device is guaranteed. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 63 Preliminary DC Characteristics CMOS Compatible Parameter ILI ILIWP ILIT ILO ICCB ICC1 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 IACC VIL VIH VILCLK VIHCLK VID VOL IOLRB VHH VOH VLKO Description Input Load Current WP# Input Load Current A9, ACC Input Load Current Output Leakage Current VCC Active Burst Read Current (1) VCC Active Asynchronous Read Current (1) VCC Active Program Current (2, 4) VCC Active Erase Current (2, 4) VCC Standby Current (CMOS) VCC Active Current (Read While Write) VCC Reset Current () Automatic Sleep Mode Current VACC Acceleration Current Input Low Voltage Input High Voltage CLK Input Low Voltage CLK Input High Voltage Voltage for Autoselect Output Low Voltage RY/BY#, Output Low Current VCC = 2.5 V IOL = 4.0 mA, VCC = VCC min VOL = 0.4 V IOH = –100 µA, VCC = VCC min 8 0.85 x VCC VIO –0.1 1.6 2.0 V Test Conditions VIN = VSS to VIO, VIO = VIO max VIN = VSS to VIO, VIO = VIO max VCC = VCCmax; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIL 56 MHz 8 Double 66, 75 MHz Word 1 MHz 40 20 70 Min Typ Max ±1.0 –25 35 ±1.0 90 10 50 50 60 30 90 60 60 20 –0.5 0.7 x VIO –0.2 0.7 x VCC 11.5 0.3 x VIO VCC 0.3 x VIO 2.75 12.5 0.45 mA V µA mA µA µA mA mA µA Unit CE# = VIL, OE# = VIL CE# = VIL, OE# = VIH, ACC = VIH CE# = VIL, OE# = VIH, ACC = VIH VCC= VCC max, CE# = VCC ± 0.3 V CE# = VIL, OE# = VIL RESET# = VIL VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V ACC = VHH Accelerated (ACC pin) High Voltage IOH = –2.0 mA, VCC = VCC min Output High Voltage Low VCC Lock-Out Voltage (3) Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Not 100% tested. 4. Maximum ICC specifications are tested with VCC = VCCmax. 64 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary DC Characteristics Zero Power Flash Supply Current in mA 4 3 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Time in ns Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 5 Supply Current in mA 2.7 V 4 3 2 1 0 1 2 3 4 5 Frequency in MHz Figure 11. Typical ICC1 vs. Frequency November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 65 Preliminary Test Conditions Device Under Test CL Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Test Specifications Table 44. Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0 V – VIO VIO/2 VIO/2 V Test Specifications 40 MHz, 56 MHz 66 MHz, 75MHz 1 TTL gate 100 pF ns Unit Key to Switching Waveforms Waveform Inputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs Switching Waveforms VIO VSS Input VIO/2 V Measurement Level VIO/2 V Output Figure 13. Input Waveforms and Measurement Levels 66 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics VCC and VIO Power-up Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Min 50 µs Test Setup Speed Unit tVCS VCC tVIOS VIOP tRSTH RESET# Figure 14. VCC and VIO Power-up Diagram November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 67 Preliminary AC Characteristics Asynchronous Read Operations Parameter JEDEC Std. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tRC Description Read Cycle Time (Note 1) Test Setup Min CE# = VIL Max OE# = VIL OE# = VIL Max Max Max Min Max Min Min Min Speed Options 75 MHz, 66 MHz, 56 MHz, 40 MHz, Unit 0R 0P 0M OJ 48 48 52 54 54 58 20 10 2 10 0 10 2 64 64 69 67 67 71 28 ns tACC Address to Output Delay tCE tOE tDF tDF Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z Note 1 Output Enable to Output High Z Note 1 Read Toggle and Data# Polling tOEH Output Enable Hold Time Note 1 tAXQX Output Hold Time From Addresses, CE# or OE#, Whichever tOH Occurs First Note 1 Notes: 1. 2. Not 100% tested. See Figure 12 and Table 44 for test specifications tRC Addresses CE# tOE tOEH WE# High Z Outputs RESET# RY/BY# Output Valid tCE tOH High Z tDF Addresses Stable tACC OE# 0V Figure 15. Conventional Read Operations Timings 68 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics Burst Mode Read for 32 Mb & 16 Mb Parameter JEDE C Std. tBACC Description 75 MHz, 0R 32 MHz Max Min Min Min Min Max Min Max Min Max Max Max Min Min Min Min Min Min Max Min Max Max Min Min 2 7.5 7.5 20 2 10 10 0 5 3 15 15 2 2 48 13. 7.5 FBGA 2 54 15 60 3 3 2.5 2.5 6 16 Mb =3 32 Mb = 8 6 5 28 3 17 17 3 3 ns 64 18 7.5 FBGA 5.75 1.5 12 2 9 FBGA 9.5 PQFP 10 FBGA 10 PQFP 3 67 25 13 Speed Options 66 MHz, 0P 9 FBGA 9.5 PQFP 56 MHz, 0M 10 FBGA 10 PQFP 6 2 15 3 17 22 40 MHz, OJ 17 Unit Burst Access Time Valid Clock to Output Delay tADVCS ADV# Setup Time to Rising Edge of CLK tADVCH ADV# Hold Time from Rising Edge of CLK tADVP tDVCH tDIND tINDH tIACC tCLK tCLKR tCLKF tCKL tCLKH tCES tCH tACS tACH tOE tDF tEHQZ tOEZ tCEZ tWCKS ADV# Pulse Width (32Mb, 75MHz) Valid Data Hold from CLK (Note Note:) CLK to Valid IND/WAIT# IND/WAIT# Hold from CLK CLK to Valid Data Out, Initial Burst Access CLK Period CLK Rise Time CLK Fall Time CLK Low Time CLK to High Time CE# Setup Time to Clock CE# Hold Time Address Setup Time to CLK Address Hold Time from ADV# Rising Edge of CLK while ADV# is Low Output Enable to Output Valid Output Enable to Output High Z (Note Note:) Chip Enable to Output High Z (Note Note:) tWADVH WE hold time after ADV falling edge WE rising edge setup time to clock rising edge Note: Not 100% tested. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 69 Preliminary AC Characteristics tCES CE# CLK tADVCS ADV# tADVCH tACS Addresses Aa tCEZ tACH Data tIACC OE#* tDVCH tBACC Da Da + 1 Da + 2 Da + 3 Da + 31 tOE tOEZ IND# Figure 16. Burst Mode Read CLK ADV# CE# tCS tCH Addresses Data Stable Address tWC Valid Data tAS tAH tDS tDH WE# OE# tOEH tWPH IND/WAIT# Figure 17. Asynchronous Command Write Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/ RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. 70 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics CE# tCES CLK tADVCS tADVP ADV# ttACS AS tACH tACS tWC tACH Valid Address tADVCH tEHQZ Data Out tWCKS tDH tDF tOE Addresses Valid Address Data Data In tWADVH OE# WE# IND/WAIT# tDS tWP 10 ns Figure 18. Synchronous Command Write/Read Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/ RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. Hardware Reset (RESET#) Parameter JEDEC Std. tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 11 500 500 50 20 0 Unit µs ns ns ns µs ns Note: Not 100% tested. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 71 Preliminary AC Characteristics RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timing to Bank NOT Executing Embedded Algorithm Reset Timing to Bank Executing Embedded Algorithm tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 19. RESET# Timings Data Program/Erase Command tDS tDH WE# tWPWS tWP WP# RY/BY# Valid WP# tCH tWPRH Figure 20. WP# Timing 72 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup to WE# Rising Edge Data Hold from WE# Rising Edge Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time WE# Width Write Pulse Width High Double-Word Description Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Max Min Min All Speed Options Unit 60 0 25 18 2 0 0 2 25 30 18 1.0 50 0 90 20 2 ns µs sec. µs ns tWHWH1 Programming Operation (Note 2) tWHWH2 Sector Erase Operation (Note 2) tVCS tRB tBUSY tWPWS tWPRH VCC Setup Time (Note 1) Recovery Time from RY/BY# RY/BY# Delay After WE# Rising Edge WP# Setup to WE# Rising Edge with Command WP# Hold after RY/BY# Rising Edge Notes: 1. 2. Not 100% tested. See Command Definitions for more information. Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tWPH Read Status Data (last two cycles) PA PA tCH tWHWH1 A0h Statu DOUT tRB VCC tVCS Note: PA = program address, PD = program data, DOUT is the true data at the program address. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 73 Preliminary AC Characteristics Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# tCH tWP WE# tCS tDS tDH Data 55h 30h 10 for Chip Erase In Progress Complete OE# tWPH tWHWH2 tBUSY RY/BY# tVCS VCC tRB Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status). Figure 21. tWC Addresses Valid PA Chip/Sector Erase Operation Timings tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE# tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tCPH tCP tGHWL tWPH tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Figure 22. Back-to-Back Cycle Timings 74 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 Complement Complement True Valid Data High Z tWC VA VA tOE tDF Data tBUSY RY/BY# Status Data Status Data True Valid Data High Z Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 23. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 24. Toggle Bit Timings (During Embedded Algorithms) November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 75 Preliminary AC Characteristics WE# Enter Embedded Erasing Erase Erase Suspend Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 25. DQ2 vs. DQ6 for Erase/Erase Suspend Operations CE# CLK AVD# Addresses VA VA OE# tOE tOE Status Data Status Data Data RDY Notes: 1. 2. 3. 4. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data. Data polling requires burst access time delay. Figure 26. Synchronous Data Polling Timing/Toggle Bit Timings 76 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary AC Characteristics VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h/48h*** Sector Protect: 150 µs Sector Unprotect: 15 ms Valid* Data 1 µs CE# 60h 60h/68h** Status WE# OE# * Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah. ** Command for sector protect is 68h. Command for sector unprotect is 60h. *** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h. Figure 27. Sector Protect/Unprotect Timing Diagram Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWsH1 tWHWH2 Std. tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tWP tCP tCPH tWHWH1 tWHWH2 Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time WE# Width CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Double-Word Description Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ 32 16 30 18 1 µs sec. 0 All Speed Options 65 0 45 35 2 ns Unit Notes: 1. 2. Not 100% tested. See Command Definitions for more information. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 77 Preliminary AC Characteristics 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWPH tWP tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. 2. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. Figure indicates the last two bus cycles of the command sequence. Figure 28. Alternate CE# Controlled Write Operation Timings 78 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Double Word Program Time Accelerated Double Word Program Time Accelerated Chip Program Time Chip Program Time (Note 3) x32 Typ (Note 1) 1.0 16 Mb = 46 32 Mb = 78 18 8 16 Mb = 5 32 Mb = 10 16 Mb = 12 32 Mb = 24 Max (Note 2) 5 16 Mb = 230 32 Mb = 460 250 130 16 Mb = 50 32 Mb = 100 16 Mb = 120 32 Mb = 240 Unit s s µs µs s s Excludes system level overhead (Note 5) Excludes 00h programming prior to erasure (Note 4) Comments Notes: 1. 2. 3. 4. 5. 6. Typical program and erase times assume the following conditions: 25°C, 2.5 V VCC, 100K cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions of 145°C, VCC = 2.5 V, 1M cycles. The typical chip programming time is considerably less than the maximum chip programming time listed. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 41 and Table 42 for further information on command definitions. PPBs have a program/erase cycle endurance of 100 cycles. Latchup Characteristics Description Input voltage with respect to VSS on all pins except I/O pins (including A9, ACC, and WP#) Input voltage with respect to VSS on all I/O pins VCC Current Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PQFP and Fortified BGA Pin Capacitance Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. 2. Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 79 Preliminary Revision Summary S29CD016G Revision History Revision A1 (March 22, 2004) Performance Characteristics Burst Mode Read: changed to 66-MHz. Ordering Information Changed device number/description call out to show the two 16-Mbit configurations. Table 12 and Table 13 Corrected which sectors report to which bank. Asynchronous Read Operations Table Removed the OR Speed option. Revision A2 (May 24, 2004) “Spansion” logo Replaces AMD in bullet seven, first column. Fujitsu MBM29LV and MBM129F Added to bullet ten, first column. Ultra Low Power Consumption Bullet “capable of...” deleted from first bullet, second column. Block diagram Reset# moved, RY/BY added. Simultaneous Read/Write Circuit Block Diagram RY/BY added; Bank 1 added; Bank 0 added. Pin Configuration “A pull-up resistor of 10k...” added to RY/BY#. Ordering Information Additional ordering options updated to “protects sectors 44 and 45”. Device Number/Description Bit description altered. Simultaneous Read/Write Operation With Zero Latency Table 3 and 4 Bank # change. Auto Select Mode Table 5: Manufacturer ID Row updated (A3, A2). Table 5: DQ7 to DQ0 Column updated. 80 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Linear Burst Read Operations Table 6: “(x16)” removed from header row. IND/Wait# Operation in Linear Mode Figure 2 - “Address 2” removed. Initial Burst Access Delay Control Figure 3 - Valid Address line changed. Notes - Clock cycles updated. Configuration Register Table 9: CR14 reserve bit assigned ASD. Table 9: Speed options changed. Table 10: CR14 reserve changed to ASD. Table12. Sector Addresses for Ordering Option 00 Bank changed to 0. Bank changed to 1. Table 13. Sector Addresses for Ordering Option 01 Bank changed to 0. Bank changed to 1. Table 16. Device Geometry Definition 0005 = supports x16 and x32 via WORD#...” Removed. Unlock Bypass Command Sequence Table “18” replaced with “19” in text. Table 19. Memory Array Command Definitions (x32 Mode) Autoselect (7) - Device ID (11); Fifth/Data changed to “36”. Table 20. Sector Protection Command Definitions (x32 Mode) PBB Status (11,12) Third/Addr changed to “SG”. PPB Lock Bit Status; Third/Addr “BA” removed. DYB Status; Third/Addr changed to “SA”. Absolute Maximum Ratings Address, Data... changed to 3.6v. Table 22 CMOS Compatible Input High Voltage Max changed to 3.6. RY/BY#, OUtput Low Current Min removed, Max added (8). Table 23. Test Specifications Test conditions changed to OJ,OM,OP. AC Characteristics Figure 14 updated RESET#. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 81 Preliminary Table number 24. Asynchronous Read Operations OM speed options; Output Enable to Output Delay “20” added. Table 26. Hardware Reset Last row deleted. Erase/Program Operations TWADVH row added. TWCKS row added. Table 27. Alternate CE# Controlled Erase/Program Operations TWPH row added, TWADVH row added, TWCKS row added. Physical Dimensions Latchup characteristics deleted. Pin Description “WAIT# Provides data valid feedback only when the burst length is set to continuous.” Removed from document. Revision A3 (May 26, 2004) Block Diagram on page 6 Moved RESET# to point to the State Control/Command Register. Figure 2, on page 22 Updated note added “Double-Word” to figure title. Table 9, “Configuration Register Definitions,” on page 24 Added “CR14 = Automatic Sleep Mode...” configurations. Table 1, “Sector Addresses for Ordering Option 00,” on page 33 Re-inserted previously missing data. Removed “Note 1” from Sector SA1. Added “Note 3” to Sector SA44 and SA45. Moved Sectors SA15 - SA30 to Bank 1. Table on page 35 Added “Note 3” to Sector SA45. Revision A4 (November 5, 2004) Global Added reference links Added Colophon Updated Trademark Product Selector Guide Removed note from Product Selector Guide table 82 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Block Diagram Changed text on Input/Output buffers to show DQ0 to DQ31 Pin Configuration Changed text in ACC description Accelerated Program and Erase Operations Changed text in this paragraph Table 5 Change Address text column. SecSi Sector Entry Command Changed address text in this paragraph Figure 18 t Changed time spec call out from 10 ns to WADVH2 Table 27 t Added new row for WADVH2 Rev History Family Data sheet Rev A (July 18, 2005) Global Merged S29CD016G and S29CD032G datasheets into one family CD-G datasheet Changed datasheet status to "Preliminary Information" Added in 75MHz parameters Ordering Information Model numbers (character 15th & 16th) changed to reflect mask revision, autoselect code and top/bottom boot Added GT Grade under Temperature Range and Quality Grade Added note to "Refer to the KGD Datasheet supplement for die/wafer sales" Product Selector Guide Changed Min. Initial clock Delay values Memory Map and Sector Protect Groups Modified Notes 1 & 3 Add in Note 4 Simultaneous Read/Write Operation Removed Table 2: Bank Assignment for Boot Bank Sector Deivice Removed Table 3: Ordering Option 00 Removed Table 4: Ordering Option 01 Secured Silicon Sector Added in Electronic Marking November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 83 Preliminary Common Flash Memory Interface Updated website to reflect Spansion.com Changed address 28h from 0003h to 0005h Command Definitions Remove Secured Silicon Protection Bit Program command Absolute Maximum Ratings Changed Overshoot/Undershoot to be ± 0.7V from ± 2.0V Changed Address, Data, Control Signals to -0.5V to 3V for 16Mb Operating Ranges Changed VIO to 1.65V to 3.6V Burst Mode Read for 32Mb & 16 Mb Changed tADVCS = 5.75ns for 75MHz Changed tADVCH to be 2ns for 66MHz, 56MHz, 40 MHz Changed tIACC values Rounded tCLK values Changed tCR to tCLKR Changed tCF to tCLKF Changed tCL to tCLKL Changed tCH to tCLKH and changed values Removed tDS, tDH, tAS, tAH, tCS Added tWADVH, tWCKS Erase/Program Operations Removed tWCKS Alternative CE# Controlled Erase/Program Operations Added tWADVH Added tWCKS Rev History Family Datasheet Rev B0 (November 14, 2005) Absolute Maximum Ratings Changed under/overshoot to ± 2.0V Changed Vcc, VIO values Changed Address, Data, Control Signal values Note 5 & 6 Revision History Added in previous revision histories. Erase/Program Operations Added Note 1 to tWC and tVCS 84 S29CD-G Flash Family S29CD-G_00_B0 November 14, 2005 Preliminary Global Changed SecSi to Secured Silicon. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 85