S29CD032J1MQAI103

S29CD-J & S29CL-J Flash Family S29CD032J, S29CD016J, S29CL032J, S29CL016J 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O™ S29CD-J & S29CL-J Flash Family Cover Sheet Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Publication Number S29CD-J_CL-J_00 Revision B Amendment 1 Issue Date September 27, 2006 Data Sheet (Preliminary) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. ii S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 S29CD-J & S29CL-J Flash Family S29CD032J, S29CD016J, S29CL032J, S29CL016J 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O™ Data Sheet (Preliminary) General Description The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks, using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single VCC of 2.5 V to 2.75 V (S29CD-J) or 3.0 V to 3.6 V (S29CL-J) that make them ideal for today’s demanding automotive applications. Distinctive Characteristics Single 2.6 V (S29CD-J) or 3.3 V (S29CL-J) for read/program/ erase 110 nm Floating Gate Technology Simultaneous Read/Write operation with zero latency x32 Data Bus Dual Boot Sector Configuration (top and bottom) Flexible Sector Architecture – CD016J & CL016J: Eight 2K Double word, Thirty-two 16K Double word, and Eight 2K Double Word sectors – CD032J & CL032J: Eight 2K Double word, Sixty-two 16K Double Word, and Eight 2K Double Word sectors Supports Common Flash Interface (CFI) Extended Temperature range Persistent and Password methods of Advanced Sector Protection Unlock Bypass program command to reduce programming time ACC input pin to reduce factory programming time Data Polling bits indicate program and erase operation completion Hardware (WP#) protection of two outermost sectors in the large bank Ready/Busy (RY/BY#) output indicates data available to system Suspend and Resume commands for Program and Erase Operation Offered Packages – – – – 80-pin PQFP 80-ball Fortified BGA Pb-free package option available Known Good Die VersatileI/O™ control (1.65 V to 3.6 V) Programmable Burst Interface – Linear for 2, 4, and 8 double word burst with or without wrap around Secured Silicon Sector that can be either factory or customer locked 20 year data retention (typical) Cycling Endurance: 1 million write cycles per sector (typical) Command set compatible with JEDEC (JC42.4) standard Performance Characteristics Read Access Times Speed Option (MHz) Max Asynch. Access Time, ns (tACC) Max Synch. Burst Access, ns (tBACC) Min Initial Clock Delay (clock cycles) Max CE# Access Time, ns (tCE) Max OE# Access time, ns (tOE) 75 (32 Mb only) 48 7.5 (FBGA) 5 52 20 66 54 8 4 54 20 56 54 8 4 54 20 40 54 8 3 54 20 Typical Program and Erase Times Double Word Programming Sector Erase 18 µs 1.0 s Current Consumption (Max values) Continuous Burst Read @ 75 MHz Program Erase Standby Mode 90 mA 50 mA 50 mA 60 µA Publication Number S29CD-J_CL-J_00 Revision B Amendment 1 Issue Date September 27, 2006 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Data Sheet (Preliminary) Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2. 3. 4. 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input/Output Descriptions and Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram of Simultaneous Read/Write Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 80-Pin PQFP Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 PRQ080–80-Lead Plastic Quad Flat Package Physical Dimensions . . . . . . . . . . . . . . . . . . 10 5.3 80-Ball Fortified BGA Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions. . . . . . . . . . . . 12 Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Specification Bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Hardware and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 13 13 6. 7. 8. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Synchronous (Burst) Read Mode & Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 VersatileI/O™ (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 21 25 26 26 31 37 37 38 39 41 41 42 42 9. 10. Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 Secured Silicon Sector Protection Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 Secured Silicon Sector Entry and Exit Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Electronic Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 46 46 46 11. 12. 2 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 13. 14. 15. 16. 17. 18. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 15.1 Zero Power Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.1 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 VCC and VIO Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Asynchronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Synchronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7 Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.10 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 52 54 56 57 57 63 65 65 65 19. 20. 21. Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 19.1 Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Appendix 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20.1 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figures Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 9.1 Figure 9.2 Figure 9.3 Figure 13.1 Figure 13.2 Figure 15.1 Figure 15.2 Figure 16.1 Figure 17.1 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Asynchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Synchronous/Asynchronous State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation . . . . . . . . . . 23 Initial Burst Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PBB Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PPB Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) . . . . . . . . . . . . . . . . 49 Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VCC and VIO Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Conventional Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous Command Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Burst Mode Read (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Synchronous Command Write/Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 WP# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 S29CD-J & S29CL-J Flash Family 3 September 27, 2006 S29CD-J_CL-J_00_B1 Data Sheet (Preliminary) Figure 18.9 Figure 18.10 Figure 18.11 Figure 18.12 Figure 18.13 Figure 18.14 Figure 18.15 Figure 18.16 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Back-to-back Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 DQ2 vs. DQ6 for Erase/Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Synchronous Data Polling Timing/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Tables Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 9.1 Table 10.1 Table 13.1 Table 14.1 Table 15.1 Table 17.1 Table 17.2 Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 18.5 Table 18.6 Table 18.7 Table 18.8 Table 18.9 Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 20.1 Table 20.2 S29CD016J/CL016J (Top Boot)Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . .15 S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . .16 S29CD032J/CL032J (Top Boot) Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . .17 S29CD032J/CL032J (Bottom Boot) Sector & Memory Address Map . . . . . . . . . . . . . . . . . . .18 Device Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 32- Bit Linear and Burst Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Valid Configuration Register Bit Definition for IND/WAIT# . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Burst Initial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Configuration Register After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method) . . . . . . . . . . . .26 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 DC Characteristic, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 VCC and VIO Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Asynchronous Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Burst Mode Read for 32 Mb and 16 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Memory Array Command Definitions (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Sector Protection Command Definitions (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 1. Ordering Information The order number (Valid Combination) is formed by the following: S29CD032J 0 J F A I 0 0 0 Packing Type 0 = Tray, FBGA: 180 per tray, min. 10 trays per box Tray, PQFP: 66 per tray, min. 10 trays per box 2 = 7” Tape and Reel, FBGA: 400 per reel 3 = 13” Tape and Reel, FBGA: 1600 per reel 13” Tape and Reel, PQFP: 500 per reel Boot Sector Option (16th Character) 0 = Top Boot with Simultaneous Operation 1 = Bottom Boot with Simultaneous Operation 3 = Top Boot without Simultaneous Operation 4 = Bottom Boot without Simultaneous Operation Autoselect ID Option (15th Character) 0 = 7E, 08, 01/00 Autoselect ID 1 = 7E, 36, 01/00 Autoselect ID 0 = 7E, 46, 01/00 Autoselect ID 0 0 = = 7E, 09, 01/00 Autoselect ID 7E, 49, 01/00 Autoselect ID S29CD016J only S29CL016J only S29CD032J only S29CL032J only Temperature Range I = Industrial (–40°C to +85°C) M = Extended (–40°C to +125°C) Material Set A = Standard F = Pb-free Option Package Type Q = Plastic Quad Flat Package (PQFP) F = Fortified Ball Grid Array, 1.0 mm pitch package Clock Frequency (10th Character) J = 40 MHz M = 56 MHz P = 66 MHz R = 75 MHz (contact factory) Initial Burst Access Delay (9th Character) 0 = 5-1-1-1, 6-1-1-1, and above 1 = 4-1-1-1 Device Number/Description S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 volt-only) 32 or 16 Megabit (1 M or 512 K x 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory Manufactured on 110 nm floating gate technology 1.1 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29CD-J/S29CL-J Valid Combinations S29CD016J S29CL016J S29CD032J S29CL032J 0J, 0M, 0P, 1J 1M 0J, 0M, 0P, 0R, 1J 1M QAI, QFI, QAM, QFM FAI, FFI, FAM, FFM QAI, QFI, QAN, QFN FAI, FFI, FAN, FFN 00, 01, 02, 03, 10, 11, 12, 13 02, 03, 12, 13 00, 01, 02, 03, 10, 11, 12, 13 02, 03, 12, 13 Note on BGA Package Markings The ordering part number that appears on BGA packages omits the leading “S29”. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 5 Data Sheet (Preliminary) 2. Input/Output Descriptions and Logic Symbols Table identifies the input and output package connections provided on the device. Symbol A19-A0 DQ31-DQ0 CE# OE# WE# VCC VIO VSS NC Type Input I/O Input Input Input Supply Input I/O No Connect Description Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb). A9 supports 12V autoselect input. Data input/output Chip Enable. This signal is asynchronous relative to CLK for the burst mode. Output Enable. This signal is asynchronous relative to CLK for the burst mode. Write Enable Device Power Supply. This signal is asynchronous relative to CLK for the burst mode. VersatileI/OTM Input. Ground Not connected internally Ready/Busy output and open drain which require a external pull up resistor. RY/BY# Output When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. Load Burst Address input. Indicates that the valid address is present on the address inputs. End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs. Provides data valid feedback only when the burst length is set to continuous. Write Protect Input. At VIL, disables program and erase functions in two outermost sectors of the large bank. Acceleration input. At VHH, accelerates erasing and programming. When not used for acceleration, ACC = VSS to VCC. Hardware Reset. CLK AVD # IND# WAIT# WP# ACC RESET# Input Input Output Output Input Input Input 6 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 3. Block Diagram VCC VSS DQmax–DQ0 Amax–A0 Erase Voltage Generator WE# RESET# ACC WP# WORD# State Control Command Register VIO Input/Output Buffers PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE#‘ OE# Y-Decoder VCC Detector Y-Gating Address Latch Timer X-Decoder Cell Matrix ADV# CLK Burst State Control IND/ WAIT# Burst Address Counter Amax–A0 DQmax–DQ0 Amax–A0 Note Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 7 Data Sheet (Preliminary) 4. Block Diagram of Simultaneous Read/Write Circuit VCC VSS OE# Y-Decoder Amax–A0 Upper Bank Address Upper Bank Latches and Control Logic Amax–A0 Amax–A0 RESET# WE# CE# ADV# DQmax–DQ0 Amax–A0 STATE CONTROL & COMMAND REGISTER Status X-Decoder DQmax–DQ0 DQmax–DQ0 Control X-Decoder DQmax–DQ0 Lower Bank Amax–A0 Lower Bank Address 8 S29CD-J & S29CL-J Flash Family Latches and Control Logic Y-Decoder S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 5. 5.1 Physical Dimensions/Connection Diagrams 80-Pin PQFP Connection Diagram IND/WAIT# RESET# RY/BY# ADV# WP# WE# OE# CE# DQ16 DQ17 DQ18 DQ19 VCCQ VSS DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VCCQ VSS DQ28 DQ29 DQ30 DQ31 NC A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 ?65 64 63 62 61 60 59 58 57 56 55 54 53 80-Pin PQFP 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK VCC VSS NC NC NC NC VCCQ DQ15 DQ14 DQ13 DQ12 VSS VCCQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSS VCCQ DQ3 DQ2 DQ1 DQ0 A19 A18 A17 A16 VCC VSS ACC A13 A10 A11 A12 Notes 1. On 16 Mb device, pin 44 (A19) is NC. 2. Pin 69 (RY/BY#) is Open Drain and requires an external pull-up resistor. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family A14 A15 A3 A4 A5 A6 A7 A8 A9 9 Data Sheet (Preliminary) 5.2 PRQ080–80-Lead Plastic Quad Flat Package Physical Dimensions 6 3 PIN S D D1 D3 PIN R 0˚MIN. PIN ONE I.D. 0.30 ± 0.05 R GAGE 0.25 PLANE E3 -A-BE1 E 3 6 L 0˚-7˚ 7˚ TYP. b 4 ccc C A 0.20 MIN. FLAT SHOULDER 7˚ TYP. aa a M C A B S D S DETAIL X SEE NOTE 3 PIN P -DSEE DETAIL X e BASIC A2 A1 S S A 2 -A-CSEATING PLANE PIN Q b c SECTION S-S PACKAGE JEDEC SYMBOL A A1 A2 b c D D1 D3 e E E1 E3 aaa ccc L P Q R S 0.73 MIN -0.25 2.70 0.30 0.15 17.00 13.90 --23.00 19.90 ---- PQR 080 MO-108(B)CB-1 NOM --2.80 --17.20 14.00 12.0 0.80 23.20 20.00 18.40 0.20 0.10 0.88 24 40 64 80 1.03 MAX 3.35 -2.90 0.45 0.23 17.40 14.10 --23.40 20.10 ---SEE NOTE 3 REFERENCE SEE NOTE 3 REFERENCE BASIC, SEE NOTE 7 SEE NOTE 4 NOTES NOTES: 1. 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -ADIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION. CONTROLLING DIMENSIONS: MILLIMETER. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH INNERMOST AND OUTERMOST POINTS. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN ±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR PITCH < 0.5 mm. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500) 1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm 2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm. COPLANARITY IS MEASURED PER SPECIFICATION 06-500. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE WITHIN ±0.0085". 3. 4. 5. 6. 7. 8. 9. 3213\38.4C 10 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 5.3 80-Ball Fortified BGA Connection Diagrams A8 A2 A7 A3 A6 A6 A5 VSS A4 ACC A3 VCC A2 A14 A1 A15 B8 A1 B7 A4 B6 A5 B5 A8 B4 A9 B3 A12 B2 A13 B1 A16 C8 A0 C7 NC C6 A7 C5 NC C4 A10 C3 A11 C2 A18 C1 A17 D8 DQ29 D7 DQ30 D6 DQ31 D5 NC D4 NC D3 A19 D2 DQ0 D1 DQ3 E8 VCCQ E7 DQ26 E6 DQ28 E5 DQ27 E4 DQ1 E3 DQ2 E2 DQ4 E1 VCCQ F8 VSS F7 DQ24 F6 DQ25 F5 RY/BY# F4 DQ5 F3 DQ6 F2 DQ7 F1 VSS G8 VCCQ G7 DQ23 G6 DQ21 G5 DQ22 G4 DQ9 G3 DQ10 G2 DQ8 G1 VCCQ H8 DQ20 H7 DQ18 H6 DQ19 H5 DQ17 H4 WP# H3 DQ11 H2 DQ12 H1 DQ13 J8 DQ16 J7 IND/WAIT# J6 OE# J5 CE# J4 NC J3 ADV# J2 DQ14 J1 DQ15 K8 NC K7 NC K6 WE# K5 VCC K4 VSS K3 CLK K2 RESET# K1 VCCQ? Notes 1. On 16 Mb device, ball D3 (A19) is NC. 2. Ball F5 (RY/BY#) is Open Drain and requires an external pull-up resistor. 5.4 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 11 Data Sheet (Preliminary) 5.5 LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions 0.20 C 2X D A D1 eD K J H G F E D C B A 8 7 6 7 SE eE 5 E 4 3 E1 φ0 .50 2 1 1.00±0.5 A1 CORNER ID. (INK OR LASER) B 1.00±0.5 A1 CORNER TOP VIEW 0.20 C 2X 6 NXφb φ0.25 M C A B φ0.10 M C SD 7 A1 CORNER BOTTOM VIEW A A2 A1 SEATING PLANE C 0.25 C 0.15 C SIDE VIEW PACKAGE JEDEC LAA 080 N/A 13.00 x 11.00 mm PACKAGE NOTE NOTES: 1. 2. MAX 1.40 --PROFILE HEIGHT STANDOFF BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.70 BALL DIAMETER BALL PITCH - D DIRECTION BALL PITCH - E DIRECTION SOLDER BALL PLACEMENT 8. 9. 7 6 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW , SD OR SE = e/2 N/A "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 3214\38.12C SYMBOL A A1 A2 D E D1 E1 MD ME N φb eD eE SD/SE MIN -0.40 0.60 NOM ---13.00 BSC. 11.00 BSC. 9.00 BSC. 7.00 BSC. 10 8 80 0.50 0.60 1.00 BSC. 1.00 BSC. 0.50 BSC 12 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 6. Additional Resources Visit www.spansion.com to obtain the following related documents: 6.1 Application Notes The following is a list of application notes related to this product. All Spansion application notes are available at http://www.spansion.com/support/technical_documents/application_notes.html Using the Operation Status Bits in AMD Devices Understanding Page Mode Flash Memory Devices MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Common Flash Interface Version 1.4 Vendor Specific Extensions 6.2 Specification Bulletins Contact your local sales office for details. 6.3 Hardware and Software Support Downloads and related information on Flash device support is available at www.spansion.com/support/index.html Spansion low-level drivers Enhanced Flash drivers Flash file system Downloads and related information on simulation modeling and CAD modeling support is available at http:// www.spansion.com/support/simulation_models.html VHDL and Verilog IBIS ORCAD An FAQ (Frequently Asked Questions) list is available at www.spansion.com/support/ses/index.html 6.4 Contacting Spansion Obtain the latest list of company locations and contact information on our web site at www.spansion.com/about/location.html September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 13 Data Sheet (Preliminary) 7. Product Overview The S29CD-J and S29CL-J families consist of 32 Mb and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/write, dual boot burst mode Flash devices optimized for today's automotive designs. These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst read (2, 4, or 8 double words) with or without wraparound. (Note that 1 double word = 32 bits.) These products also offer single word programming with program/erase suspend and resume functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required. 256 bytes of Secured Silicon area for storing customer or factory secured information. The Secured Silicon Sector is One-Time Programmable. Electronic marking. 7.1 Memory Map The S29CD-J and S29CL-J devices consist of two banks organized as shown in Table 7.1, Table 7.2, Table 7.3 and Table 7.4. 14 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Table 7.1 S29CD016J/CL016J (Top Boot)Sector and Memory Address Map Sector SA0 (Note 1) SA1 SA2 SA3 SA4 Bank 0 (Note 2) SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SG9 SG8 Sector Group SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 x32 Address Range (A18:A0) 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh 18000h–1BFFFh 1C000h–1FFFFh Sector Size (KDwords) 2 2 2 2 2 2 2 2 16 16 16 16 16 Bank 1 (Note 2) 16 16 Sector SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 (Note 3) SA45 (Note 3) Notes 1. Secured Silicon Sector overlays this sector when enabled. 2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2. 3. This sector has the additional WP# pin sector protection feature. Sector Group x32 Address Range (A18:A0) 20000h–23FFFh Sector Size (KDwords) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 SG10 24000h–27FFFh 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh SG11 34000h–37FFFh 38000h–3BFFFh 3C000h–3FFFFh 40000h–43FFFh SG12 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh SG13 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh SG14 64000h–67FFFh 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh SG15 74000h–77FFFh 78000h–7BFFFh SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 7C000h–7C7FFh 7C800h–7CFFFh 7D000h–7D7FFh 7D800h–7DFFFh 7E000h–7E7FFh 7E800h–7EFFFh 7F000h–7F7FFh 7F800h–7FFFFh September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 15 Data Sheet (Preliminary) Table 7.2 S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map Sector Group SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 x32 Address Range (A18:A0) 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh SG8 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh SG9 18000h–1BFFFh 1C000h–1FFFFh 20000h–23FFFh SG10 24000h–27FFFh 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh SG11 34000h–37FFFh 38000h–3BFFFh 3C000h–3FFFFh 40000h–43FFFh SG12 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh SG13 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh Sector Size (KDwords) 2 2 2 2 2 Bank 1 (Note 2) 2 2 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Sector Group x32 Address Range (A18:A0) 60000h–63FFFh SG14 64000h–67FFFh 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh SG15 74000h–77FFFh 78000h–7BFFFh SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 7C000h–7C7FFh 7C800h–7CFFFh 7D000h–7D7FFh 7D800h–7DFFFh 7E000h–7E7FFh 7E800h–7EFFFh 7F000h–7F7FFh 7F800h–7FFFFh Sector Size (KDwords) 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 Sector SA0 (Note 1) SA1 (Note 1) SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 Bank 0 (Note 2) SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 Sector SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 (Note 3) Notes 1. This sector has the additional WP# pin sector protection feature. 2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1. 3. Secured Silicon Sector overlays this sector when enabled. 16 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Table 7.3 S29CD032J/CL032J (Top Boot) Sector & Memory Address Map Sector Sector Group x32 Address Range (A19:A0) Bank 0 (Note 2) SA0 (Note 1) SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SG9 SA13 SA14 SA15 SA16 SG10 SA17 SA18 SA19 SA20 SG11 SA21 SA22 38000h–3BFFFh 3C000h–3FFFFh Bank 1 (Note 2) SA23 SA24 SG12 SA25 SA26 SA27 SA28 SG13 SA29 SA30 SA31 SA32 SG14 SA33 SA34 SA35 SA36 SG15 SA37 SA38 78000h–7BFFFh 7C000h–7FFFFh 16 16 SA77 (Note 3) SG31 FF800h–FFFFFh 2 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh 74000h–77FFFh 16 16 16 16 SA73 SA74 SA75 SA76 (Note 3) SG27 SG28 SG29 SG30 FD800h–FDFFFh FE000h–FE7FFh FE800h–FEFFFh FF000h–FF7FFh 2 2 2 2 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh 64000h–67FFFh 16 16 16 16 SA69 SA70 SA71 SA72 SG24 SG25 SG26 F8000h–FBFFFh FC000h–FC7FFh FC800h–FCFFFh FD000h–FD7FFh 16 2 2 2 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh 54000h–57FFFh 16 16 16 16 SA65 SA66 SA67 SA68 SG23 40000h–43FFFh 44000h–47FFFh 16 16 16 16 SA60 SG21 SA61 SA62 SA63 SA64 SG22 E8000h–EBFFFh EC000h–EFFFFh F0000h–F3FFFh F4000h–F7FFFh 16 16 16 16 D8000h–DBFFFh DC000h–DFFFFh E0000h–E3FFFh E4000h–E7FFFh 16 16 16 16 D4000h–D7FFFh 16 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh 34000h–37FFFh 16 16 16 16 SA56 SG20 SA57 SA58 SA59 C8000h–CBFFFh CC000h–CFFFFh D0000h–D3FFFh 16 16 16 C4000h–C7FFFh 16 18000h–1BFFFh 1C000h–1FFFFh 20000h–23FFFh 24000h–27FFFh 16 16 16 16 SA52 SG19 SA53 SA54 SA55 B8000h–BBFFFh BC000h–BFFFFh C0000h–C3FFFh 16 16 16 B4000h–B7FFFh 16 SG8 SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh 2 2 2 2 2 2 2 2 16 16 16 16 16 SA39 SA40 SG16 SA41 SA42 SA43 SA44 SG17 SA45 SA46 SA47 SA48 SG18 SA49 SA50 SA51 A8000h–ABFFFh AC000h–AFFFFh B0000h–B3FFFh 16 16 16 98000h–9BFFFh 9C000h–9FFFFh A0000h–A3FFFh A4000h–A7FFFh 16 16 16 16 88000h–8BFFFh 8C000h–8FFFFh 90000h–93FFFh 94000h–97FFFh 16 16 16 16 Sector Size (KDwords) Sector Sector Group x32 Address Range (A19:A0) Sector Size (KDwords) Bank 1 continued (Note 2) 80000h–83FFFh 84000h–87FFFh 16 16 Notes 1. Secured Silicon Sector overlays this sector when enabled. 2. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1. 3. This sector has the additional WP# pin sector protection feature. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 17 Data Sheet (Preliminary) Table 7.4 S29CD032J/CL032J (Bottom Boot) Sector & Memory Address Map Sector Sector Group x32 Address Range (A19:A0) Bank 0 (Note 2) SA0 (Note 3) SA1 (Note 3) SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SG15 SG14 SG13 SG12 SG11 SG10 SG9 SG8 SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 00000h–007FFh 00800h–00FFFh 01000h–017FFh 01800h–01FFFh 02000h–027FFh 02800h–02FFFh 03000h–037FFh 03800h–03FFFh 04000h–07FFFh 08000h–0BFFFh 0C000h–0FFFFh 10000h–13FFFh 14000h–17FFFh 18000h–1BFFFh 1C000h–1FFFFh 20000h–23FFFh 24000h–27FFFh 28000h–2BFFFh 2C000h–2FFFFh 30000h–33FFFh 34000h–37FFFh 38000h–3BFFFh 3C000h–3FFFFh 40000h–43FFFh 44000h–47FFFh 48000h–4BFFFh 4C000h–4FFFFh 50000h–53FFFh 54000h–57FFFh 58000h–5BFFFh 5C000h–5FFFFh 60000h–63FFFh 64000h–67FFFh 68000h–6BFFFh 6C000h–6FFFFh 70000h–73FFFh 74000h–77FFFh 78000h–7BFFFh 7C000h–7FFFFh 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 (Note 1) Notes 1. This sector has the additional WP# pin sector protection feature. 2. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1. 3. The Secured Silicon Sector overlays this sector when enabled. Sector Size (KDwords) Sector Sector Group x32 Address Range (A19:A0) Sector Size (KDwords) Bank 0 continued (Note 2) SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SG19 SG18 SG17 SG16 80000h–83FFFh 84000h–87FFFh 88000h–8BFFFh 8C000h–8FFFFh 90000h–93FFFh 94000h–97FFFh 98000h–9BFFFh 9C000h–9FFFFh A0000h–A3FFFh A4000h–A7FFFh A8000h–ABFFFh AC000h–AFFFFh B0000h–B3FFFh B4000h–B7FFFh B8000h–BBFFFh BC000h–BFFFFh Bank 1 (Note 2) C0000h–C3FFFh SG20 C4000h–C7FFFh C8000h–CBFFFh CC000h–CFFFFh D0000h–D3FFFh SG21 D4000h–D7FFFh D8000h–DBFFFh DC000h–DFFFFh E0000h–E3FFFh SG22 E4000h–E7FFFh E8000h–EBFFFh EC000h–EFFFFh F0000h–F3FFFh SG23 F4000h–F7FFFh F8000h–FBFFFh SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 FC000h–FC7FFh FC800h–FCFFFh FD000h–FD7FFh FD800h–FDFFFh FE000h–FE7FFh FE800h–FEFFFh FF000h–FF7FFh FF800h–FFFFFh 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 18 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 8. Device Operations This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command register (see Table 8.1). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine; the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command in order to return the device to the reading array data mode. 8.1 Device Operation Table The device must be set up appropriately for each operation. Table 8.1 describes the required state of each control pin for any particular operation. Table 8.1 Device Bus Operation Operation CE# L L L H L X OE# L H H X H X WE# H L L X H X RESET# H H H H H L X X X X X X CLK X X ADV# X X Addresses AIN AIN AIN X HIGH Z X Sector Address, A9 = VID, A7 – A0 = 02h Data (DQ0–DQ31) DOUT DIN DIN HIGH Z HIGH Z HIGH Z 00000001h, (protected) A6 = H 00000000h (unprotect) A6 = L Read Asynchronous Write Synchronous Write Standby (CE#) Output Disable Reset PPB Protection Status (Note 2) L L H H X X Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data bus Terminate Current Burst Read Cycle Terminate Current Burst Read Cycle with RESET# Terminate Current Burst Read Cycle; Start New Burst Read Cycle L L X L H H H H H AIN X X Burst Data Out H X L X X H H H H H L H X X X X X AIN HIGH Z HIGH Z X Legend L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care. Notes 1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block. 2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 19 Data Sheet (Preliminary) 8.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The internal state machine is set for asynchronously reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection (CE# must be set to VIL to read data). OE# is the output control and should be used to gate data to the output pins if the device is selected (OE# must be set to VIL in order to read data). WE# should remain at VIH (when reading data). Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least a period of tACC-tOE and CE# has been asserted for at least tCE-tOE time). Figure 8.1 shows the timing diagram of an asynchronous read operation. Figure 8.1 Asynchronous Read Operation CE# CLK ADV# Addresses Data OE# WE# IND/WAIT# VIH Float Float VOH Address 0 Address 1 Address 2 Address 3 D0 D1 D2 D3 D3 Note Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required. Refer to Section 18.2, Asynchronous Operations on page 52 for timing specifications and to Figure 18.2, Conventional Read Operations Timings on page 52 for another timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. 8.3 Hardware Reset (RESET#) The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0” on this input forces the device out of any mode that is currently executing back to the reset state. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation. If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a period of tREADY2, if the bank was in the read/reset mode at the time RESET# was asserted. If one of the 20 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) banks was in the middle of either a program or erase operation when RESET# was asserted, the user must wait a period of tREADY before accessing that bank. Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset. These locations need updating after the reset operation is complete. See Section 18.4 for timing specifications. Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device initialization until VCC and VIO have reached their steady state voltages. See Section 18.1. 8.4 Synchronous (Burst) Read Mode & Configuration Register When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. The device offers a linear method of burst read operation which is discussed in Section 8.4.1, 2-, 4-, 8Double Word Linear Burst Operation on page 22. Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set in order to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (tIACC) of each burst access and when RDY indicates that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration register settings (and read the current register settings if desired via the Read Configuration Register command sequence), then write the configuration register command sequence. See Section 8.4.3, Configuration Register on page 24, and Table 20.1, Memory Array Command Definitions (x32 Mode) on page 69 for further details. Once the configuration register is written to enable burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. Figure 8.2 Synchronous/Asynchronous State Diagram Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1)? Synchronous Read Mode Only The device outputs the initial word subject to the following operational conditions: tIACC specification: The time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that tIACC is lengthened. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 21 Data Sheet (Preliminary) Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchronous timing as defined in the Configuration Register. However, the user must recognize burst operations past the 256 byte Secured Silicon boundary returns invalid data. Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations results in the data remaining valid while OE# is at VIL, regardless of the number of CLK cycles applied to the device. 8.4.1 2-, 4-, 8- Double Word Linear Burst Operation In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive addresses that are determined by the group within which the starting address falls. Note that 1 double word = 32 bits. See Table 8.2 for all valid burst output sequences. The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (VIL) during the last transfer of data in a linear burst read before a wrap around. This transition indicates that the system should initiate another ADV# to start the next burst access. If the system continues to clock the device, the next access wraps around to the starting address of the previous burst access. The IND/WAIT# signal is floating when not active. Table 8.2 32- Bit Linear and Burst Data Order Data Transfer Sequence (Independent of the WORD# pin) Two Linear Data Transfers Output Data Sequence (Initial Access Address, x16) 0-1 (A0 = 0) 1-0 (A0 = 1) 0-1-2-3 (A0:A-1/A1-A0 = 00) Four Linear Data Transfers 1-2-3-0 (A0:A-1/A1-A0 = 01) 2-3-0-1 (A:A-1/A1-A0 = 10) 3-0-1-2 (A0:A-1/A1-A0 = 11) 0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000) 1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001) 2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010) Eight Linear Data Transfers 3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011) 4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100) 5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101) 6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110) 7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111) Notes 1. The default configuration in the Control Register for Bit 6 is “1,” indicating that the device delivers data on the rising edge of the CLK signal. 2. The device is capable of holding data for one CLK cycle. 3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register contents are reset to their default conditions. 4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal. 5. Restarting a burst cycle is accomplished by taking CE# and ADV# to VIL. 6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions back to VIH before a clock edge. 7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to VIH during a burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst is complete. The OE# pin does not halt the burst sequence, The DQ bus remains in the float state until OE# is taken to VIL. 8. Halting the burst sequence is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse. The IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/WAIT# signal floats and is not driven. If OE# is at VIL, the IND/ WAIT# signal is driven at VIH until it transitions to VIL, indicating the end of the burst sequence. Table 8.3 lists the valid combinations of the Configuration Register bits that impact the IND/WAIT# timing. See Figure 8.3 for the IND/WAIT# timing diagram. 22 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT# CR9 (DOC) 0 0 CR8 (WC) 0 1 CR6 (CC) 1 1 Definition IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation VIH CE# VIL CLK 3 Clock Delay ADV# Addresses Data Address 1 Address 1 Latched Address 2 Invalid D1 D2 D3 D0 OE# IND/WAIT# Note Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around. 8.4.2 Initial Burst Access Delay Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid. Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration Register (CR13-CR10). Refer to Table 8.5 for the initial access delay configurations under CR13-CR10. See Figure 8.4 for the Initial Burst Delay Control timing diagram. Note that the Initial Access Delay for a burst access has no effect on asynchronous read operations. Table 8.4 Burst Initial Access Delay CR13 0 0 0 0 0 0 0 CR12 0 0 0 1 1 1 1 CR11 0 1 1 0 0 1 1 CR10 1 0 1 0 1 0 1 Initial Burst Access (CLK cycles) 3 4 5 6 7 8 9 September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 23 Data Sheet (Preliminary) Figure 8.4 Initial Burst Delay Control 1st CLK 2nd CLK 3rd CLK 4th CLK 5th CLK CLK ADV# Addresses DQ31-DQ03 DQ31-DQ04 DQ31-DQ05 Valid Address Address 1 Latched Three CLK Delay D0 Four CLK Delay D0 Five CLK Delay D0 D1 D2 D1 D2 D3 D1 D2 D3 D4 Notes 1. Burst access starts with a rising CLK edge and when ADV# is active. 2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge. 3. CR [13-10] = 1 or three clock cycles 4. CR [13-10] = 2 or four clock cycles 5. CR [13-10] = 3 or five clock cycles 8.4.3 Configuration Register The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode and the configuration register settings are in their default state. (See Table 8.6 for the default Configuration Register settings.) The host system determines the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the Configuration Register commands. The Configuration Register is readable at any time, however, writing the Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If the user attempts to write the Configuration Register while the Embedded Algorithm™ is active, the write operation is ignored and the contents of the Configuration Register remain unchanged. The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation, DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the same as the Autoselect command reads. When the command is issued, the bank address is latched along with the command. Read operations to the bank that was specified during the Configuration Register read command return Configuration Register contents. Read operations to the other bank return flash memory data. Either bank address is permitted when writing the Configuration Register read command. The configuration register can be read with a four-cycle command sequence. See Section 20.1, Command Definitions on page 69 for sequence details. Table 8.5 describes the Configuration Register settings. 24 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Table 8.5 Configuration Register Configuration Register CR15 = Read Mode (RM) 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) CR14 = Reserved for Future Enhancements These bits are reserved for future use. Set these bits to 0. CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0) 0000 = 2 CLK cycle initial burst access delay 0001 = 3 CLK cycle initial burst access delay 0010 = 4 CLK cycle initial burst access delay 0011 = 5 CLK cycle initial burst access delay CR9 = Data Output Configuration (DOC) 0 = Hold Data for 1-CLK cycle—Default 1 = Reserved CR8 = IND/WAIT# Configuration (WC) 0 = IND/WAIT# Asserted During Delay—Default 1 = IND/WAIT# Asserted One Data Cycle Before Delay CR7 = Burst Sequence (BS) 0 = Reserved 1 = Linear Burst Order—Default CR6 = Clock Configuration (CC) 0 = Reserved 1 = Burst Starts and Data Output on Rising Clock Edge—Default CR5–CR3 = Reserved For Future Enhancements (R) These bits are reserved for future use. Set these bits to 0. CR2–CR0 = Burst Length (BL2–BL0) 000 = Reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear 010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear 011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default) 100 = Reserved, burst accesses disabled (asynchronous reads only) 101 = Reserved, burst accesses disabled (asynchronous reads only) 110 = Reserved, burst accesses disabled (asynchronous reads only) 0100 = 6 CLK cycle initial burst access delay 0101 = 7 CLK cycle initial burst access delay 0110 = 8 CLK cycle initial burst access delay 0111 = 9 CLK cycle initial burst access delay—Default Table 8.6 Configuration Register After Device Reset CR15 RM 1 CR14 Reserve 0 CR13 IAD3 0 CR12 IAD2 1 CR11 IAD1 1 CR10 IAD0 1 CR9 DOC 0 CR8 Reserve 0 CR7 BS 1 CR6 CC 1 CR5 Reserve 0 CR4 Reserve 0 CR3 Reserve 0 CR2 BL2 1 CR1 BL1 0 CR0 BL0 0 8.5 Autoselect The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-dress pins A6, A1, and A0 must be as shown in Table 8.7. In addition, when verifying sector protection, the sector September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 25 Data Sheet (Preliminary) address must appear on the appropriate highest order address bits. Table 8.7 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command. This method does not require VID. See Section 20.1, Command Definitions on page 69 for details on using the autoselect mode. Autoselect mode can be used in either synchronous (Burst) mode or asynchronous (Non Burst) mode. The system must write the reset command to exit the autoselect mode and return to reading the array data. See Table 8.7 for command sequence details. Table 8.7 S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method) A19 to A11 X X A5 to A8 A7 A6 A4 A3 A2 A1 A0 X X X L L L X X X L X L L L L H DQ7 to DQ0 0001h 007Eh 08h or 36h for CD016J Read Cycle 2 L L H X X VID X L L L H H H L 46h for CL016J 09h for CD032J 49h for CL032J 0000h Read Cycle 3 L L H X X VID X L L L H H H H Top Boot Option 0001h Bottom Boot Option 0000h (unprotected) PPB Protection Status L L H SA X VID X L L L L L H L 0001h (protected) Description Manufacturer ID: Spansion Read Cycle 1 Autoselect Device Code CE# L L OE# L L WE# H H A10 X X A9 VID VID Legend L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note The autoselect codes can also be accessed in-system via command sequences. See Table 20.2. 8.6 VersatileI/O™ (VIO) Control The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The output voltage generated on the device is determined based on the VIO (VCCQ) level. For the 2.6 V (CD-J), a VIO of 1.65 V–3.6 V (CD032J has a VIO of 1.65 V to 2.75 V) allows the device to interface with I/Os lower than 2.5 V. For a 3.3 V VCC (CL-J), a VIO of 1.65 V–3.60 V allows the device to interface with I/Os lower than 3.0 V. 8.7 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be set up appropriately as outlined in the configuration register (Table 8.5 on page 25). During a synchronous write operation, to write a command or command sequence (including programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. 8.7.1 Programming Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell 26 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) margin. Section 20.1, Command Definitions on page 69 shows the address and data requirements for the program command sequence. Note the following: When the Embedded Program algorithm is complete, the device returns to the read mode and address are no longer latched. An address change is required to begin reading valid array data. The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. Refer to Section 8.8, Write Operation Status on page 31 for information on these status bits. A “0” cannot be programmed back to a “1.” Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. . A succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. A hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the device has returned to the read mode, to ensure data integrity. Figure 8.5 Program Operation START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note See Table 19.1 and Table 20.2 for program command sequence. 8.7.2 Sector Erase The sector erase function erases one or more sectors in the memory array. (See Table 20.1, Memory Array Command Definitions (x32 Mode), on page 69 and Figure 8.6, Erase Operation, on page 29.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 27 Data Sheet (Preliminary) successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 80 µs occurs. During the timeout period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs. Any sector erase address and command following the exceeded time-out (80 µs) may or may not be accepted. A time-out of 80 µs from the rising edge of the last WE# (or CE#) initiates the execution of the Sector Erase com-mand(s). If another falling edge of the WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See Section 8.8.6, DQ3: Sector Erase Timer on page 35.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data; addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Section 8.8, Write Operation Status on page 31 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be re-initiated once that bank has returned to reading array data, in order to ensure data integrity. Figure 8.6 on page 29 illustrates the algorithm for the erase operation. Refer to Section 8.7, Program/Erase Operations on page 26 for parameters and timing diagrams. 8.7.3 Chip Erase Chip erase is a six-bus cycle operation as indicated by Section 20.1, Command Definitions on page 69. The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single command. However, chip erase does not erase protected sectors. This command invokes the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. Section 20.1 in the appendix shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6 or the RY/ BY#. Refer to Section 8.8, Write Operation Status on page 31 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 28 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 8.6 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes 1. See Section 20.1, Command Definitions on page 69 for erase command sequence. 2. See Section 8.8.6, DQ3: Sector Erase Timer on page 35 for more information. 8.7.4 Erase Suspend / Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 80-µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the 80-µs time-out period has expired and during the sector erase operation, the device takes 20 µs maximum to suspend the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector that is not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Note that when the device is in the Erase Suspend mode, the Reset command is not required for read operations and is ignored. Further nesting of erase operation is not permitted. Reading at any address within erase suspended sectors produces status information on DQ7-DQ0. The system can use DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 8.8 on page 34 for information on these status bits. A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase suspend command is issued; read operations thereafter return array data. Read operations from the other bank return array data with no latency. After an erase-suspended program operation is complete, the bank returns to the erase-suspend read mode. The system can determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status bits, just as in the standard program operation. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 29 Data Sheet (Preliminary) The following are the allowable operations when Erase Suspend is issued under certain conditions: For the Busy Sectors, the host system may Read status Write the Erase Resume command For the Non Busy Sectors, the system may Read data Program data or write the Suspend/Resume Erase command 8.7.5 Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation and updates the status bits. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The Sector Erase and Program Resume Command is ignored if the Secured Silicon sector is enabled. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status bits, just as in the standard program operation. See Section 8.8, Write Operation Status on page 31 for more information. The system must write the Program Resume command in order to exit the Program Suspend mode, and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. The following are the allowable operations when Program Suspend is issued under certain conditions: For the Busy Sectors, the host system may write the Program Resume command For the Non Busy Sectors, the system may read data 8.7.6 Accelerated Program and Erase Operations Accelerated programming and erasing is enabled through the ACC function. This method is faster than the standard program command sequences. The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH (12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses the higher voltage on the ACC pin to accelerate the operation. Any sector that is being protected with the WP# pin is still protected during accelerated program or Erase. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Notes In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1. The ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result. The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. The Accelerated Program command is not permitted if the Secured Silicon sector is enabled. 8.7.7 Unlock Bypass The device features an Unlock Bypass mode to facilitate faster programming, erasing (Sector and Chip Erase), as well as CFI commands. Once the device enters the Unlock Bypass mode, only two write cycles are required to program or erase data, instead of the normal four cycles. This results in faster total programming/ erasing time. Section 20.1, Command Definitions on page 69 shows the requirements for the unlock bypass command sequences. 30 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) During the unlock bypass mode only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence, which returns the device to read mode. Notes 1. The Unlock Bypass Command is ignored if the Secured Silicon sector is enabled. 2. Unlike the standard program or erase commands, there is no Unlock Bypass Program/Erase Suspend or Program/Erase Resume command. 8.7.8 Simultaneous Read/Write The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing in another bank of memory. The Simultaneous Read/Write feature can be used to perform the following: Programming in one bank, while reading in the other bank Erasing in one bank, while reading in the other bank Programming a PPB, while reading data from the large bank or status from the small bank Erasing a PBB, while reading data from the large bank or status from the small bank Any of the above situations while in the Secured Silicon Sector Mode The Simultaneous R/W feature can not be performed during the following modes: CFI Mode Password Program operation Password Verify operation As an alternative to using the Simultaneous Read/Write feature, the user may also suspend an erase or program operation to read in another location within the same bank (except for the sector being erased). 8.8 Write Operation Status The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ7, DQ6, DQ2, DQ5, DQ3, and RY/BY#. 8.8.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that Data# Polling returns invalid data for the address being programmed or erased. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode without programming the sector. If an erase address falls within a protected sector, Toggle BIT (DQ6) is active for 150 s, then the device returns to the read mode without erasing the sector. Please note that Data# polling (DQ7) may give misleading status when an attempt is made to program or erase a protected sector. During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. In asynchronous mode, just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 31 Data Sheet (Preliminary) operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles. See the following for more information: Table 8.9, Write Operation Status on page 36 shows the outputs for Data# Polling on DQ7. Figure 8.7, Data# Polling Algorithm, on page 32 shows the Data# Polling timing diagram. Figure 8.7 Data# Polling Algorithm START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5 8.8.2 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase timeout. 32 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) During an Embedded Program or Erase algorithm operation, two immediate consecutive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See Figure 18.12, Toggle Bit Timings (During Embedded Algorithms), on page 60 for additional information. 8.8.3 DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system performs two consecutive reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 8.8 to compare outputs for DQ2 and DQ6. See Section 8.8.2, DQ6: Toggle Bit I on page 32 for additional information. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 33 Data Sheet (Preliminary) 8.8.4 Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must perform two consecutive reads of DQ7DQ0 in a row in order to determine whether a toggle bit is toggling. Typically, the system notes and stores the value of the toggle bit after the first read. After the second read, the system compares the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completes the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also notes whether the value of DQ5 is high (see the section on DQ5). If it is, the system then determines again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device had not completed the operation successfully, and the system writes the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 8.8 for more on the Toggle Bit Algorithm. Table 8.8 DQ6 and DQ2 Indications If device is programming, and the system reads at any address, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within sectors selected for erasure, erase suspended, at an address within secotrs not selected for erasure, at any address, then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable. actively erasing, programming in erase suspend, 34 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 8.8 Toggle Bit Algorithm START Read Byte (DQ0-DQ7) Address = VA (Note 1) Read Byte (DQ0-DQ7) Address = VA DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ?0-DQ7) Adrdess = VA (Notes 1, 2) DQ6 = Toggle? No Yes FAIL PASS Notes 1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. 8.8.5 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Under both these conditions, the system issues the reset command to return the device to reading array data. 8.8.6 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 35 Data Sheet (Preliminary) are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See Section 8.7.2, Sector Erase on page 27 for more details. After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 8.9 shows the status of DQ3 relative to the other status bits. 8.8.7 RY/BY#: Ready/Busy# The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output of RY/BY# is low, the device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any additional program or erase commands with the exception of the Erase suspend command. If the device has entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/ BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE# pulse. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is completed in a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pullup resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is an open drain. Table 8.9 shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2. Figure 18.2, Figure 18.6, Figure 18.8 and Figure 18.9 show RY/BY# for read, reset, program, and erase operations, respectively. Table 8.9 Write Operation Status Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Erase Suspend Mode Notes 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See Section 8.8.5, DQ5: Exceeded Timing Limits on page 35 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. See Section 8.8.1, DQ7: Data# Polling on page 31 and Section 8.8.3, DQ2: Toggle Bit II on page 33 for further details. 36 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 8.9 Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the cycles in an erase command sequence before erasing begins. This resets the device to the read mode. However, once erasure begins, the device ignores the reset commands until the operation is complete. The reset command may be written between the cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erasesuspend-read mode. However, once programming begins, the device ignores the reset commands until the operation is complete. The reset command may be written between the cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to exit the autoselect mode and return to the read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode or erase-suspend-read-mode if the device was in Erase Suspend. When the reset command is written, before the embedded operation starts, the device requires tRR before it returns to the read or erasesuspend-read mode. Table 8.10 Reset Command Timing Parameter tRR Description Reset Command to Read Mode or Erase-Suspend-Read Mode Max. 250 Unit ns 9. Advanced Sector Protection/Unprotection The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 9.1. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 37 Data Sheet (Preliminary) Figure 9.1 Advanced Sector Protection/Unprotection Hardware Methods Software Methods WP# = VIL (Two outermost sectors locked in large bank) Password Method (DQ2) Persistent Method (DQ1) 64-bit Password (One Time Protect) PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked 1. Bit is volatile, and defaults to “1” on reset. 2. Programming to “0” locks all PPBs to their current state. 3. Once programmed to “0”, requires hardware reset to unlock. Memory Array Sector 0 Sector 1 Sector 2 Persistent Protection Bit (PPB)4,5 PPB 0 PPB 1 PPB 2 Dynamic Protection Bit (DYB)6,7,8 DYB 0 DYB 1 DYB 2 Sector N-2 Sector N-1 Sector N 3 PPB N-2 PPB N-1 PPB N 4. PPBs programmed individually, but cleared collectively DYB N-2 DYB N-1 DYB N 5. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is “0” (unprotected). 6. Volatile Bits. 3. N = Highest Address Sector. 9.1 Advanced Sector Protection Overview As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected. The device programmer or host system must then choose which sector protection method to use. Programming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks the device permanently in that mode: Persistent Protection Mode Lock Bit Password Protection Mode Lock Bit After selecting a sector protection method, each sector can operate in any of the following three states: 38 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 1. Persistently Locked. A sector is protected and cannot be changed. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described between page 39 and page 42. Notes 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. The user must be sure that the password is correct when the Password Mode Locking Bit is set, as there is no means to verify the password afterwards. 2. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 3. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. 4. It is important that the mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is impossible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. 5. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without modifying the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs, after which the device returns to read mode without having erased the protected sector. 6. For the command sequence required for programming the lock register bits, refer to Section 20.1, Command Definitions on page 69. 9.2 Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile. A single Persistent Protection Bit is assigned to a maximum for four sectors (see the sector address tables for specific sector protection groupings). All eightKbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Notes 1. Each PPB is individually programmed and all are erased in parallel. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 2. If a PPB requires erasure, all of the sector PPBs must first be programmed prior to PPB erasing. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPB has the potential of being over-erased. There is no hardware mechanism to prevent sector PPB over-erasure. 3. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. 9.2.1 Programming PPB The PPB Program Command is used to program, or set, a given PPB. The first three cycles in the PPB Program Command are standard unlock cycles. The fourth cycle in the PPB Program Command executes the pulse which programs the specified PPB. The user must wait either 100 µs or until DQ6 stops toggling before executing the fifth cycle, which is the read verify portion of the PPB Program Command. The sixth cycle outputs the status of the PPB Program operation. In the event that the program PPB operation was not successful, the user can loop directly to the fourth cycle of the PPB Program Command to perform the program pulse and read verification again. After four unsuccessful loops through the program pulse and read verification cycles the PPB programming operation should be considered a failure. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 39 Data Sheet (Preliminary) Figure 9.2 PBB Program Operation Write 0xAA to 0x555 Write 0x55 to 0x2AA Write 0x60 to 0x555 Write 0x68 to SG+WP Either poll DQ6 in the small bank and wait for it to stop toggling OR wait 100 μs Note: Reads from the small bank at this point return the status of the operation, not read array data. Write 0x48 to SG+WP Read from SG+WP NO NO 5th attempt? YES DQ0 = 1? YES Error Done 9.2.2 Erasing PPB The All PPB Erase command is used to erase all the PPBs in bulk. There are no means for individually erasing a specific PPB. The first three cycles of the PPB Erase command are standard unlock cycles. The fourth cycle executes the erase pulse to all the PBBs. The user must wait either 20ms or until DQ6 stops toggling before executing the fifth cycle, which is the read verify portion of the PPB Erase Command. The sixth cycle outputs the status of the PPB Erase operation. In the event that the erase PPB operation was not successful, the user can loop directly to the fourth cycle of the All PPB Erase Command to perform the erase pulse and read verification again. After four unsuccessful loops through the erase pulse and read verification cycles, the PPB erasing operation should be considered a failure. Note All PPB must be preprogrammed prior to issuing the All PPB Erase Command. 40 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 9.3 PPB Erase Operation Write 0xAA to 0x555 Write 0x55 to 0x2AA Write 0x60 to 0x555 Write 0x60 to WP Either poll DQ6 in the small bank and wait for it to stop toggling OR wait 20 ms Note: Reads from the small bank at this point return the status of the operation, not read array data. Write 0x40 to WP Read from WP NO NO 5th attempt? YES DQ0 = 0? YES Error Done 9.3 Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set to “1”, it locks all PPBs; when set to “0”, it allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2. The PPB Lock Bit must be set only after all PPBs are configured to the desired settings. 9.4 Dynamic Protection Bits A Dynamic Protection Bit (DYB) is volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs set to “0”. By issuing the DYB Set or Clear command sequences, the DYBS are set or cleared, thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. Notes 1. The DYBs can be set or cleared as often as needed with the DYB Write Command. 2. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. The DYB are also always cleared after a power-up or reset. 3. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 4. The DYB Set or Clear commands for the dynamic sectors signify the protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 41 Data Sheet (Preliminary) locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. Table 9.1 Sector Protection Schemes DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable 9.5 Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power-up and reset, the PPB Lock Bit is set “1” in order to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes 1. There is no special addressing order required for programming the password. Once the password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. 2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”. (This is an OTP area). 3. The password is all “1”s when shipped from the factory. 4. When the password is undergoing programming, Simultaneous Read/Write operation is disabled. Read operations to any memory location returns the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. 5. All 64-bit password combinations are valid as a password. 6. There is no means to read, program or erase the password is after it is set. 7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 8. The Password Mode Lock Bit is not erasable. 9. The exact password must be entered in order for the unlocking function to occur. 10. There is a built-in 2-µs delay for each password check. This delay is intended to stop any efforts to run a program that tries all possible combinations in order to crack the password. 9.6 Hardware Data Protection Methods The device offers several methods of data protection by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describe these methods. 9.6.1 WP# Method The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large bank. 42 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) If the system asserts VIL on the WP# pin, the device disables program and erase functions in the two “outermost” boot sectors (8-Kbyte sectors) in the large bank. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution 9.6.2 Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. 9.6.3 Write Pulse “Glitch Protection” Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 9.6.4 Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power-up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. 9.6.5 VCC and VIO Power-up And Power-down Sequencing The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach the operating voltages. Once, VCC and VIO attain the operating voltages, deassertion of RESET# to VIH is permitted. 9.6.6 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH). September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 43 Data Sheet (Preliminary) 10. Secured Silicon Sector Flash Memory Region The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is a 256-byte flash memory area that is either programmable at the customer, or by Spansion at the request of the customer. See Table 10.1 for the Secured Silicon Sector address ranges. All Secured Silicon reads outside of the 256-byte address range return invalid data. Table 10.1 Secured Silicon Sector Addresses Ordering Option Top Boot Bottom Boot Sector Size (Bytes) 256 256 Address Range 00000h-0003Fh (16 Mb & 32 Mb) FFFC0h–FFFFFh (32 Mb) 7FFC0h–7FFFFh (16 Mb) The device allows Simultaneous Read/Write operation while the Secured Silicon Sector is enabled. However, several restrictions are associated with Simultaneous Read/Write operation and device operation when the Secured Silicon Sector is enabled: 1. The Secured Silicon Sector is not available for reading while the Password Unlock, any PPB program/erase operation, or Password programming are in progress. Reading to any location in the small bank will return the status of these operations until these operations have completed execution. 2. Programming the DYB associated with the overlaid boot-block sector results in the DYB NOT being updated. This occurs only when the Secured Silicon sector is not enabled. 3. Reading the DYB associated with the overlaid boot-block sector when the PPB Lock/DYB Verify command is issued, causes the read command to return invalid data. This function occurs only when the Secured Silicon Sector is not enabled. 4. All commands are available for execution when the Secured Silicon Sector is enabled, except the following: a. Any Unlock Bypass command b. CFI c. Accelerated Program d. Program and Sector Erase Suspend e. Program and Sector Erase Resume Issuing the above commands while the Secured Silicon Sector is enabled results in the command being ignored. 5. It is valid to execute the Sector Erase command on any sector other than the Secured Silicon Sector when the Secured Silicon Sector is enabled. However, it is not possible to erase the Secured Silicon Sector using the Sector Erase Command, as it is a one-time programmable (OTP) area that can not be erased. 6. Executing the Chip Erase command is permitted when the Secured Silicon Sector is enabled. The Chip Erase command erases all sectors in the memory array, except for sector 0 in top-boot block configuration, or sector 45 in bottom-boot block configuration. The Secured Silicon Sector is a onetime programmable memory area that cannot be erased. 7. Executing the Secured Silicon Sector Entry command during program or erase suspend mode is allowed. The Sector Erase/Program Resume command is disabled when the Secured Silicon sector is enabled; the user cannot resume programming of the memory array until the Exit Secured Silicon Sector command is written. 8. Address range 00040h–007FFh for the top bootblock, and FF00h–FFF7Fh return invalid data when addressed with the Secured Silicon sector enabled. 9. The Secured Silicon Sector Entry command is allowed when the device is in either program or erase suspend modes. If the Secured Silicon sector is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erasure on the Secured 44 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Silicon sector if the overlayed sector was undergoing programming or erasure. The host system must ensure that the device resume any suspended program or erase operation after exiting the Secured Silicon sector. 10.1 Secured Silicon Sector Protection Bit The Secured Silicon Sector can be shipped unprotected, allowing customers to utilize that sector in any manner they choose. Please note the following: The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Secured Silicon Sector Protection Bit must be used with caution as once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return the device to the memory array. 10.2 Secured Silicon Sector Entry and Exit Commands The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See the Table 20.1, Memory Array Command Definitions (x32 Mode), on page 69 and Table 20.2, Sector Protection Command Definitions (x32 Mode), on page 70 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read Secured Silicon areas Program Secured Silicon Sector (only once) After the system has written the Enter Secured Silicon Sector command sequence, it can read the Secured Silicon Sector by using the addresses listed in Table 10.1, Secured Silicon Sector Addresses on page 44. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. 11. Electronic Marking Electronic marking has been programmed into the device, prior to shipment from Spansion, to ensure traceability of individual products. The electronic marking is stored and locked within a one-time programmable region. Detailed information on Electronic Marking will be provided in a datasheet supplement. 12. Power Conservation Modes 12.1 Standby Mode When the system is not reading or writing to the device, it can place the device in standby mode. In this mode, current consumption is greatly reduced, and outputs are placed in a high impedance state, independent of OE# input. The device enters CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 in Section 15.1, DC Characteristic, CMOS Compatible on page 48 represents the standby current specification. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 45 Data Sheet (Preliminary) Caution Entering standby mode via the RESET# pin also resets the device to read mode and floats the data I/O pins. Furthermore, entering ICC7 during a program or erase operation leaves erroneous data in the address locations being operated on at the time of the RESET# pulse. These locations require updating after the device resumes standard operations. See Hardware RESET# Input Operation for further discussion of the RESET# pin and its functions. 12.2 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. While in sleep mode, output data is latched and always available to the system. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. Standard address access timings provide new data when addresses are changed. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than tACC or the CLK runs slower than 5 MHz. A new burst operation is required to provide new data. ICC8 in Section 15.1, DC Characteristic, CMOS Compatible on page 48 represents the automatic sleep mode current specification. 12.3 Hardware RESET# Input Operation The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. Any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity. When RESET# is held at VSS ±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ±0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry, thus a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset operation is internally complete. This action requires between 1 µs and 7 µs for either Chip Erase or Sector Erase. The RY/BY# pin can be used to determine whether the reset operation is complete. Otherwise, allow for the maximum reset time of 11 µs. If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank after 500 ns if the bank is in the read/reset mode at the time RESET# is asserted. If one of the banks is in the middle of either a program or erase operation when RESET# is asserted, the user must wait 11 µs before accessing that bank. Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization until VCC and VIO have reached steady state voltages. 12.4 Output Disable (OE#) When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. 46 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 13. Electrical Specifications 13.1 Absolute Maximum Ratings Table 13.1 Absolute Maximum Ratings Parameter Storage Temperature, Plastic Packages Ambient Temperature with Power Applied VCC, VIO (Note 1) for 2.6 V devices (S29CD-J) VCC, VIO (Note 1) for 3.3 V devices (S29CL-J) ACC, A9, and RESET# (Note 2) (with the exception of CLK) Address, Data, Control Signals (Note 1) All other pins (Note 1) –0.5 V to +2.75 V (32 Mb) Rating –65 °C to +150 °C –65 °C to +145 °C –0.5 V to +3.6 V –0.5 V to +3.6 V –0.5 V to +13.0 V –0.5 V to +3.6 V (16 Mb) –0.5V to +2.75 V (32 Mb) –0.5 V to +3.6 V (16 Mb) Output Short Circuit Current (Note 3) 200 mA Notes 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 13.2. Maximum DC voltage on output and I/O pins is 3.6 V. During voltage transitions output pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 13.2. 2. Minimum DC input voltage on pins ACC, A9, and RESET# is -0.5 V. During voltage transitions, A9 and RESET# may overshoot VSS to – 2.0 V for periods of up to 20 ns. See Figure 13.1. Maximum DC input voltage on pin A9 is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 13.1 Maximum Negative Overshoot Waveform 20 ns +0.8 V –0.5 V –2 V 20 ns 20 ns Figure 13.2 Maximum Positive Overshoot Waveform 20 ns V CC +2.0 V V CC +0.5 V 2.0 V 20 ns 20 ns September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 47 Data Sheet (Preliminary) 14. Operating Ranges Table 14.1 Operating Ranges Parameter Ambient Temperature (TA) VCC Supply Voltages VIO Supply Voltages Industrial Devices Extended Devices VCC for 2.6 V regulated voltage range (S29CD-J devices) VCC for 3.3 V regulated voltage range (S29CL-J devices) VIO (S29CD-J devices) VIO (S29CL-J devices) Range –40°C to +85°C –40°C to +125°C 2.50 V to 2.75 V 3.00 V to 3.60 V 1.65V to 2.75V 1.65V to 3.6V Note Operating ranges define those limits between which the functionality of the device is guaranteed. 15. DC Characteristics Table 15.1 DC Characteristic, CMOS Compatible Parameter ILI ILIWP ILIT ILO ICCB ICC1 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 IACC VIL VIH VILCLK VIHCLK VID VOL IOLRB VHH VOH VLKO Description Input Load Current WP# Input Load Current A9, ACC Input Load Current Output Leakage Current VCC Active Burst Read Current (1) VCC Active Asynchronous Read Current (1) VCC Active Program Current (2, 3, 4) VCC Active Erase Current (2, 3, 4) VCC Standby Current (CMOS) VCC Active Current (Read While Write) (3) VCC Reset Current Automatic Sleep Mode Current VACC Acceleration Current Input Low Voltage Input High Voltage CLK Input Low Voltage CLK Input High Voltage Voltage for Autoselect Output Low Voltage RY/BY#, Output Low Current Accelerated (ACC pin) High Voltage Output High Voltage Low VCC Lock-Out Voltage (3) VCC = 2.5 V IOL = 4.0 mA, VCC = VCC min VOL = 0.4 V IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min 8 0.85 x VCC VIO –0.1 1.6 2.0 Test Conditions VIN = VSS to VIO, VIO = VIO max VIN = VSS to VIO, VIO = VIO max VCC = VCCmax; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIL 56 MHz 66, 75 MHz 8 Double Word 1 MHz 40 20 45 Min Typ Max ±1.0 –25 35 ±1.0 55 4 50 50 60 30 90 60 60 20 –0.5 0.7 x VIO –0.2 0.7 x VCC 11.5 0.3 x VIO VCC 0.3 x VIO 2.75 12.5 0.45 Unit µA µA µA µA mA mA mA mA µA mA µA µA mA V V V V V V mA V V V CE# = VIL, OE# = VIL CE# = VIL, OE# = VIH, ACC = VIH CE# = VIL, OE# = VIH, ACC = VIH VCC= VCC max, CE# = VCC ± 0.3 V CE# = VIL, OE# = VIL RESET# = VIL VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V ACC = VHH Notes 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Not 100% tested. 4. Maximum ICC specifications are tested with VCC = VCCmax. 48 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 15.1 Zero Power Flash Figure 15.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 4 Supply Current in mA 3 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note Addresses are switching at 1 MHz Figure 15.2 Typical ICC1 vs. Frequency 5 2.7 V 4 Supply Current in mA 3 2 1 0 1 2 3 4 5 Frequency in MHz September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 49 Data Sheet (Preliminary) 16. Test Conditions Figure 16.1 Test Setup Device Under Test CL Note Diodes are IN3064 or equivalent 17. Test Specifications Table 17.1 Test Specifications Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0 V – VIO VIO/2 VIO/2 54D, 64C 65A, 75E 1 TTL gate 100 pF ns V V V Unit Table 17.2 Key to Switching Waveforms Waveform Inputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs 17.1 Switching Waveforms Figure 17.1 Input Waveforms and Measurement Levels VIO VSS Input VIO/2 V Measurement Level VIO/2 V Output 50 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 18. AC Characteristics 18.1 VCC and VIO Power-up Table 18.1 VCC and VIO Power-up Parameter tVCS tVIOS tRSTH Description VCC Setup Time VIO Setup Time RESET# Low Hold Time Test Setup Min Min Min Speed 50 50 50 Unit µs µs µs Figure 18.1 VCC and VIO Power-up Diagram tVCS VCC tVIOS VIOP tRSTH RESET# September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 51 Data Sheet (Preliminary) 18.2 Asynchronous Operations Table 18.2 Asynchronous Read Operations Speed Options Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Min Max Min Min Min 75MHz 0R 48 48 52 66MHz 0P 54 54 54 20 10 2 10 0 10 2 56MHz 0M 54 54 54 40MHz 0J 54 54 54 20 Unit ns ns ns ns ns ns ns ns ns ns Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std. tRC tACC tCE tOE tDF tDF tOEH Output Enable Hold Time (Note 1) tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes 1. Not 100% tested. 2. See Figure 16.1 and Table 17.1 for test specifications. 3. TOE during Read Array. Figure 18.2 Conventional Read Operations Timings tRC Addresses tACC CE# tOE tOEH WE# High Z Outputs RESET# RY/BY# Output Valid tCE tOH High Z tDF Addresses Stable OE# 0V 52 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 18.3 Asynchronous Command Write Timing CLK ADV# CE# tCS tCH Addresses Data Stable Address tWC Valid Data tAS tAH tDS tDH WE# OE# tWEH tOEP IND/WAIT# Note All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 53 Data Sheet (Preliminary) 18.3 Synchronous Operations Table 18.3 Burst Mode Read for 32 Mb and 16 Mb Description 75MHz, OR Burst Access Time Valid Clock to Output Delay ADV# Setup Time to Rising Edge of CLK ADV# Hold Time from Rising Edge of CLK ADV# Pulse Width Valid Data Hold from CLK (Note 2) CLK to Valid IND/WAIT# (Note 2) IND/WAIT# Hold from CLK (Note 2) ADV or ADD Valid (Whichever Occurs Last) to Valid Data Out, Initial Burst Access CLK Period CLK Rise Time (Note 2) CLK Fall Time (Note 2) CLK High Time (Note 3) CLK Low Time (Note 3) Output Enable to Output Valid Output Enable to Output High Z (Note 2) Chip Enable to Output High Z (Note 2) CE# Setup Time to Clock ADV# Falling Edge to Address Valid (Note 1) Address Hold Time from Rising Edge of AVD# RESET# Low to Output High Z (Note 2) ADV# Falling Edge to WE# Falling Edge ADV# Rising Edge to WE# Rising Edge Max Min Min Min Min Max Min Max Min Max Max Max Min Min Max Min Max Max Min Max Min Max Min Min 2 7.5 7.5 4 6.5 15 7.5 5 10 6.65 6.65 6.8 27 20 2 10 10 4 6.5 15 10 5 10 3 15 15 5 6.5 15 15 5 10 7.5 2 7.5 FBGA 2 48 13.3 8.5 2 9 FBGA 9.5 PQFP 2 54 15.15 60 3 3 8.0 27 11.25 27 20 3 17 17 6 6.5 15 17 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns 7.5 FBGA 6 Speed Options 66MHz, OP 8 6 1.5 9.5 3 10 FBGA 10 PQFP 3 54 17.85 10.5 3 17 3 54 25 56MHz, OM 8 6 40MHz, OJ 8 6 Unit ns ns ns ns ns ns ns ns ns Parameter JEDEC Std. tBACC tADVCS tADVCH tADVP tBDH tINDS tINDH tIACC tCLK tCR tCF tCLKH tCLKL tOE tDF tEHQZ tOEZ tCEZ tCES tAAVS tAAVH tRSTZ tWADVH1 tWADVH2 Notes 1. Using the max tAAVS and min tADVCS specs together will result in incorrect data output. 2. Not 100% tested 3. Recommended 50% Duty Cycle 54 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 18.4 Burst Mode Read (x32 Mode) tCES CE# CLK tADVCS ADV# tCEZ Addresses Aa tBDH tAAVH Data tAAVS tIACC OE# Da tBACC Da+1 Da+2 Da + 3 Da + 31 tOE tOEZ IND# tINDS tINDH Figure 18.5 Synchronous Command Write/Read Timing CE# tCES CLK tADVCS tADVP ADV# Valid Address tAS Valid Address tADVCH Valid Address tWC tEHQZ Data Out tWAVDH2 tDH tDF tOE Addresses Data Data In tWAVDH1 OE# WE# IND/WAIT# tDS tWP 10 ns Note All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 55 Data Sheet (Preliminary) 18.4 Hardware Reset (RESET#) Table 18.4 Hardware Reset (RESET#) Parameter Test Setup Max Max Max Min Min Min Max All Speed Options 11 500 500 50 20 0 500 JEDEC Std. tREADY tREADY2 tRP tRH tRPD tRB tREADY3 Description RESET# Pin Low (During embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (Not during embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High time Before Read (See Note) RESET# Low to Standby Mode RY/BY # Recovery Time RESET # Active for Bank NOT Executing Algorithm Unit µs ns ns ns µs ns ns Note Not 100% tested. Figure 18.6 RESET# Timings RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timing to Bank NOT Executing Embedded Algorithm Reset Timing to Bank Executing Embedded Algorithm tReady RY/BY# tRB CE#, OE# RESET# tRP 56 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 18.5 Write Protect (WP#) Figure 18.7 WP# Timing Data Program/Erase Command tDS tDH WE# tWPWS tWP WP# RY/BY# Valid WP# tBUSY tWPRH 18.6 Erase/Program Operations Table 18.5 Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY tWPWS tWPRH Notes 1. Not 100% tested. 2. See Section 20.1, Command Definitions on page 69 for more information. 3. Program Erase Parameters are the same, regardless of Synchronous or Asynchronous mode. Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup to WE# Rising Edge Data Hold from WE# Rising Edge Read Recovery Time Before Write (OE# High to WE# Low) (Note 1) CE# Setup Time CE# Hold Time WE# Width Write Pulse Width High Programming Operation (Note 2), Double-Word Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# (Note 1) RY/BY# Delay After WE# Rising Edge (Note 1) WP# Setup to WE# Rising Edge with Command (Note 1) WP# Hold after RY/BY# Rising Edge (Note 1) Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Max Min Max All Speed Options 60 0 25 18 2 0 0 0 25 30 9 0.5 50 0 90 20 2 Unit ns ns ns ns ns ns ns ns ns ns µs sec. µs ns ns ns ns September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 57 Data Sheet (Preliminary) Figure 18.8 Program Operation Timings Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tWPH Read Status Data (last two cycles) PA PA tCH tWHWH1 A0h Status DOUT tRB VCC tVCS Note PA = program address, PD = program data, DOUT is the true data at the program address. 58 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 18.9 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC Note SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” ). tRB Figure 18.10 Back-to-back Cycle Timings tWC Addresses Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE# tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tCPH tCP tGHWL tWPH tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 59 Data Sheet (Preliminary) Figure 18.11 Data# Polling Timings (During Embedded Algorithms) ‘ tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 tDF tOE VA tWC VA High Z Complement Complement True Valid Data High Z Data tBUSY RY/BY# Status Data Status Data True Valid Data Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18.12 Toggle Bit Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data 60 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations WE# Enter Embedded Erasing Erase Erase Suspend Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings CE# CLK AVD# Addresses VA VA OE# tOE tOE Status Data Status Data Data RDY Notes 1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data. 4. Data polling requires burst access time delay. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 61 Data Sheet (Preliminary) Figure 18.15 Sector Protect/Unprotect Timing Diagram VIH RESET# SA, A6, A1, A0 Valid* Sector Protect/Unprotect Valid* Verify 40h/48h*** Sector Protect: 150 µs Sector Unprotect: 15 ms Valid* Data 1 µs CE# 60h 60h/68h** Status WE# OE# Notes * Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah. ** Command for sector protect is 68h. Command for sector unprotect is 60h. *** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h. 62 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 18.7 Alternate CE# Controlled Erase/Program Operations Table 18.6 Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tWP tCP tCPH tWHWH1 tWHWH2 tWADVS tWCKS Notes 1. Not 100% tested. 2. See Section 20.1 on page 69 for more information. Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write(OE# High to WE# Low) WE# Setup Time WE# Hold Time WE# Width CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) WE# Rising Edge Setup to ADV# Falling Edge WE# Rising Edge Setup to CLK Rising Edge Double-Word Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min All Speed Options 65 0 45 35 2 0 0 0 25 20 30 9 0.5 11.75 5 Unit ns ns ns ns ns ns ns ns ns ns ns µs sec ns ns September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 63 Data Sheet (Preliminary) Figure 18.16 Alternate CE# Controlled Write Operation Timings 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tW S tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWPH tWP tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 64 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 18.8 Erase and Programming Performance Table 18.7 Erase and Programming Performance Parameter Typ (Note 1) 0.5 16 Mb = 46 32 Mb = 78 8 8 16 Mb = 5 32 Mb = 10 16 Mb = 12 32 Mb = 24 Max (Note 2) 5 16 Mb = 230 32 Mb = 460 130 130 16 Mb = 50 32 Mb = 100 16 Mb = 120 32 Mb = 240 Unit s s µs µs s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Sector Erase Time Chip Erase Time Double Word Program Time Accelerated Double Word Program Time Accelerated Chip Program Time Chip Program Time, x32 (Note 3) Notes 1. Typical program and erase times assume the following conditions: 25°C, 2.5 V VCC, 100K cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 145°C, VCC = 2.5 V, 1M cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20.1 and Table 20.2 for further information on command definitions. 6. PPBs have a program/erase cycle endurance of 100 cycles. 7. Guaranteed cycles per sector is 100K minimum. 18.9 Latchup Characteristics Table 18.8 Latchup Characteristics Description Input voltage with respect to VSS on all pins except I/O pins (including A9, ACC, and WP#) Input voltage with respect to VSS on all I/O pins VCC Current Note Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA 18.10 PQFP and Fortified BGA Pin Capacitance Table 18.9 PQFP and Fortified BGA Pin Capacitance Parameter Symbol CIN COUT CIN2 Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 65 Data Sheet (Preliminary) 19. Appendix 1 19.1 Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 19.1-Table 19.3. In order to terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 19.1-Table 19.3. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100. Contact a Spansion representative for copies of these documents. Table 19.1 CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 19.2 CFI System Interface String Addresses Data Description VCC Min. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt 0023h = S29CD-J devices 0030h = S29CL-J devices VCC Max. (write/erase) DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt 0027h = S29CD-J devices 0036h = S29CL-J devices VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single word/doubleword program 2N µs Typical timeout for Min. size buffer program 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for word/doubleword program 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) 1Bh (see description) 1Ch (see description) 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 0000h 0000h 0004h 0000h 0009h 0000h 0005h 0000h 0007h 0000h 66 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Table 19.3 Device Geometry Definition Addresses 27h Data Device Size = 2N byte (see description) 0015h = 16 Mb device 0016h = 32 Mb device Flash Device Interface description (for complete description, please refer to CFI publication 100) 0000 = x8-only asynchronous interface 28h 29h 0003h 0000h 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via BYTE# with asynchronous interface 0003 = x 32-only asynchronous interface 0005 = supports x16 and x32 via WORD# with asynchronous interface 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 0000h 0000h 0003h 0007h 0000h 0020h 0000h (See description) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Max. number of byte in multi-byte program = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Address 31h data: 001Dh = 16 Mb device 003Dh = 32 Mb device Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Description Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Table 19.4 CFI Primary Vendor-Specific Extended Query (Sheet 1 of 2) Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0033h Query-unique ASCII string PRI Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (DQ1, DQ0) 00 = Required, 01 = Not Required 45h 0004h Silicon Revision Number (DQ5–DQ2) 0000 = CS49 0001 = CS59 0010 = CS99 0011 = CS69 0100 = CS119 Erase Suspend (1 byte) 00 = Not Supported 01 = To Read Only 02 = To Read and Write Sector Protect (1 byte) 00 = Not Supported, X = Number of sectors in per group Temporary Sector Unprotect 00h = Not Supported, 01h = Supported Description 46h 0002h 47h 48h 0001h 0000h September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 67 Data Sheet (Preliminary) Table 19.4 CFI Primary Vendor-Specific Extended Query (Continued) (Sheet 2 of 2) Addresses Data Description Sector Protect/Unprotect scheme (1 byte) 01 =29F040 mode, 02 = 29F016 mode 03 = 29F400 mode, 04 = 29LV800 mode 05 = 29BDS640 mode (Software Command Locking) 06 = BDD160 mode (New Sector Protect) 07 = 29LV800 + PDL128 (New Sector Protect) mode Simultaneous Read/Write (1 byte) 00h = Not Supported, X = Number of sectors in all banks except Bank 1 Burst Mode Type 00h = Not Supported, 01h = Supported Page Mode Type 00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) ACC (Acceleration) Supply Maximum 00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD) Top/Bottom Boot Sector Flag (1 byte) 00h = Uniform device, no WP# control, 01h = 8 x 8 Kb sectors at top and bottom with WP# control 02h = Bottom boot device 03h = Top boot device 04h = Uniform, Bottom WP# Protect 05h = Uniform, Top WP# Protect If the number of erase block regions = 1, then ignore this field Program Suspend 00 = Not Supported 01 = Supported Write Buffer Size 2(N+1) word(s) Bank Organization (1 byte) 00 = If data at 4Ah is zero XX = Number of banks Bank 1 Region Information (1 byte) XX = Number of Sectors in Bank 1 Bank 2 Region Information (1 byte) XX = Number of Sectors in Bank 2 Bank 3 Region Information (1 byte) XX = Number of Sectors in Bank 3 Bank 4 Region Information (1 byte) XX = Number of Sectors in Bank 4 49h 0006h 4Ah 4Bh 4Ch 4Dh 4Eh 0037h 0001h 0000h 00B5h 00C5h 4Fh 0001h 50h 0001h 51h 0000h 57h 0002h 58h 59h 5Ah 5Bh 0017h 0037h 0000h 0000h 68 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 20. Appendix 2 20.1 Command Definitions Table 20.1 Memory Array Command Definitions (x32 Mode) Cycles Bus Cycles (Notes 1–4) First Addr RA XXX 555 555 555 555 555 BA BA 55 XX 555 555 555 XX XX XX XX Data RD F0 AA AA AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 XX 00 PA 2AA 2AA 2AA PA XX PD 55 55 55 PD 10 BA+555 555 555 C6 D0 20 BA+XX XX RD WD 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 555 555 555 555 555 90 90 A0 80 80 BA+X00 BA+X01 PA 555 555 01 7E PD AA AA 2AA 2AA 55 55 555 SA 10 30 BA+X0E 09 BA+X0F 00/01 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Command (Notes) Read (5) Reset (6) Autoselect (7) Program Chip Erase Sector Erase Program/Erase Suspend (12) Program/Erase Resume (13) CFI Query (14, 15) Accelerated Program (16) Configuration Register Verify (15) Configuration Register Write (17) Unlock Bypass Entry (18) Unlock Bypass Program (18) Unlock Bypass Erase (18) Unlock Bypass CFI (14, 18) Unlock Bypass Reset (18) Legend Manufacturer ID Device ID (11) 1 1 4 6 4 6 6 1 1 1 2 3 4 3 2 2 1 2 BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command. PA = Program Address (Amax–A0). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (Amax–A0). RD = Read Data. Data DQmax–DQ0 at address location RA. SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes 1. See Table 8.1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to the read mode (or to the erasesuspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 7. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or device ID information. See “Autoselect” for more information. 8. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock Bypass Reset command must be executed to return to normal operation. 9. This command is ignored during any embedded program, erase or suspended operation. 10. Valid read operations include asynchronous and burst read mode operations. 11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01. 12. The system may read and program in non-erasing sectors when in the Program/Erase Suspend mode. The Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 14. Command is valid when device is ready to read array data. 15. Asynchronous read operations. 16. ACC must be at VID during the entire operation of this command. 17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 69 Data Sheet (Preliminary) Table 20.2 Sector Protection Command Definitions (x32 Mode) Cycles Bus Cycles (Notes 1–4) First Addr XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 Data F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 555 BA+555 555 BA+555 555 555 BA+555 555 555 555 555 88 90 60 60 38 C8 28 60 60 90 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 SL RD(0) PL 48 PL RD(0) XX OW OW PWA[0-1] PWA[0-1] PWA[0-1] SG+WP WP SA+X02 00 68 RD(0) PWD[0-1] PWD[0-1] PWD[0-1] 68 60 00/01 SG+WP WP 48 40 SG+WP WP RD(0) RD(0) OW 48 OW RD(0) Second Addr Data Third Addr Data Addr Fourth Data Fifth Addr Data Sixth Addr Data Command (Notes) Reset Secured Silicon Sector Entry Secured Silicon Sector Exit Secured Silicon Protection Bit Program (5, 6) Secured Silicon Protection Bit Status Password Program (5, 7, 8) Password Verify Password Unlock (7, 8) PPB Program (5, 6) All PPB Erase (5, 9, 10) PPB Status (11, 12) PPB Lock Bit Set PPB Lock Bit Status DYB Write (7) DYB Erase (7) DYB Status (12) PPMLB Program (5, 6) PPMLB Status (5) SPMLB Program (5, 6) SPMLB Status (5) Legend 1 3 4 6 6 4 4 5 6 6 4 3 4 4 4 4 6 6 6 6 DYB = Dynamic Protection Bit OW = Address (A5–A0) is (011X10). PPB = Persistent Protection Bit PWA = Password Address. A0 selects between the low and high 32-bit portions of the 64-bit Password PWD = Password Data. Must be written over two cycles. PL = Password Protection Mode Lock Address (A5–A0) is (001X10) RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if unprotected, DQ0 = 0. RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. Notes 1. See Table 8.1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns the device to reading the array. 6. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command. SG = Sector Group Address BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command. SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10) WP = PPB Address (A5–A0) is (111010) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 8. The entire four bus-cycle sequence must be entered for each portion of the password. 9. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. 70 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) 21. Revision History Section Revision A0 (March 1, 2005) Initial release. Description Revision A1 (April 15, 2005) Ordering Information and Valid Combinations tables Revision A2 (January 20, 2006) Ordering Information Input/Output Descriptions Additional Resources Memory Address Map Simultaneous Read/Write Operation Advanced Sector Protection/ Unprotection Electronic Marking Absolute Maximum Ratings AC Characteristics Asynchronous Read Operation Conventional Read Operation Timings Added “Contact factory” for 75 MHz. Modified Ordering Options for Characters 15 & 16 to reflect autoselect ID & top/bottom boot. Changed “N” for Extended Temperature Range to “M”. Removed Logic Symbol Diagrams. Added section. Changed “Bank 2” to “Bank 1”. Removed Ordering Options Table (Tables 3 & 4). Added Advanced Sector Protection/Unprotection figure. Added figures for PPB Erase & Program Algorithm. Added in Electronic Marking section. Modified VCC Ratings to reflect 2.6 V and 3.6 V devices. Modified VCC Ratings to reflect 16 Mb & 32 Mb devices. Added Note “tOE during Read Array”. Changed values of tAVAV, tAVQV, tELQV, tGLQV in table. Moved tDF line to 90% on the high-Z output in figure. Added tAAVS and tAAVH timing parameters to table. Changed tCH to tCLKH. Changed tCL to tCLKL. Removed the following timing parameters: • tDS (Data Setup to WE# Rising Edge) • tDH (Data Hold from WE# Rising Edge) • tAS (Address Setup to Falling Edge of WE#) • tAH (Address Hold from Falling Edge of WE#) • tCS (CE# Setup Time) • tCH (CE# Hold Time) • tACS (Address Setup Time to CLK) • tACH (Address Hold Time from ADV# Rising Edge of CLK while ADV# is Low) Added the following timing parameters: Burst Mode Read (x32 Mode) • tAAVS • tDVCH • tINDS • tINDH In figure, changed tOEH to tWEH; changed tWPH to tOEP. Removed tWADVH and tWCKS from figure. In figure, changed tCH to tBUSY In table, added Note 3: Program/Erase parameters are the same regardless of synchronous or asynchronous mode. Added tOEP (OE# High Pulse) Removed tOES from table. Added tWADVS and tWCKS Removed “or when device is in autoselect mode” from Note 14. Updated to include lead Pb-free options. Burst Mode Read for 32 Mb & 16 Mb Asynchronous Command Write Timing Synchronous Command Write/Read Timing WP# Timing Erase/Program Operations Alternative CE# Controlled Erase/ Program Operations Appendix 2: Command Definitions Revision B0 (June 12, 2006) Global Distinctive Characteristics Performance Characteristics Ordering Information Changed document status to Preliminary. Changed cycling endurance from typical to guaranteed. Updated Max Asynch. Access Time, Max CE# Access Time, and Max OE# Access time in table. Updated additional ordering options in designator breakout table. Updated valid combination tables. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 71 Data Sheet (Preliminary) Section Input/Output Descriptions and Logic Symbols Physical Dimensions/Connection Diagrams Additional Resources Hardware Reset (RESET#) Autoselect Erase Suspend / Erase Resume Commands Program Suspend / Program Resume Commands Reset Command Secured Silicon Sector Flash Memory Region Absolute Maximum Ratings Operating Ranges DC Characteristics, CMOS Compatible table Burst Mode Read for 32 Mb and 16 Mb table Synchronous Command Write/Read Timing figure Hardware Reset (RESET#) Erase/Program Operations table Erase and Programming Performance Common Flash Memory Interface (CFI) Revision B1 (September 27, 2006) Distinctive Characteristics Performance Characteristics Ordering Information S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method) DQ6 and DQ2 Indications Section 8.9, Reset Command Section 13.1, Absolute Maximum Ratings Table 18.3, Burst Mode Read for 32 Mb and 16 Mb Burst Mode Read (x32 Mode) Changed RY/BY# description. Changed note on connection diagrams. Updated contact information. Added section. Description Updated third and fourth paragraphs in section. Updated Autoselect Codes table. Modified second paragraph. Replaced allowable operations table with bulleted list. Replaced allowable operations table with bulleted list. Added section. Modified Secured Silicon Sector Addresses table. Modified VCC and VIO ratings. Modified Note 1. Modified specification titles and descriptions (no specification value changes). Modified ICCB specification. Deleted Note 5. Added Note 3 references to table. Modified tADVCS, tCLKH, tCLKL, tAAVS specifications. Added tRSTZ, tWAVDH1, and tWAVDH2 specifications. Added Notes 2 and 3, and note references to table. Added tWAVDH1 and tWAVDH2 to figure. Deleted tACS and tACH from figure. Added table to section. Added note references. Deleted tOEP specification. Changed Double Word Program Time specification. CFI System Interface String table: Changed description and data for addresses 1Bh and 1Ch. Device Geometry Definition table: Changed description and data for address 27h. Changed cycling endurance specification to typical. Changed tBACC specifications for 66 MHz, 56 MHz, 40 MHz speed options. Added quantities to packing type descriptions, restructured table for easier reference. In table, modified description of read cycle 3 DQ7–DQ0. In table, corrected third column heading Added table. Deleted OE# from section. In table, changed tADVCS, tBDH specifications. Modified description for tIACC. Deleted minimum specifications for tAAVH. In figure, modified period for tIACC in drawing. 72 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006 Data Sheet (Preliminary) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2005–2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. September 27, 2006 S29CD-J_CL-J_00_B1 S29CD-J & S29CL-J Flash Family 73 Data Sheet (Preliminary) 74 S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B1 September 27, 2006