S29GL-P MirrorBit® Flash Family
S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
S29GL-P MirrorBit® Flash Family Cover Sheet
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication Number S29GL-P_00
Revision A
Amendment 7
Issue Date November 8, 2007
Data
Sheet
(Preliminary)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
S29GL-P MirrorBit® Flash Family
S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
Data Sheet (Preliminary)
General Description
The Spansion S29GL01G/512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These devices offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher density, better performance and lower power consumption.
Distinctive Characteristics
Single 3V read/program/erase (2.7-3.6 V) Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC
Offered Packages
– 56-pin TSOP – 64-ball Fortified BGA
90 nm MirrorBit process technology 8-word/16-byte page read buffer 32-word/64-byte write buffer reduces overall programming time for multiple-word updates Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number – Can be programmed and locked at the factory or by the customer
Suspend and Resume commands for Program and Erase operations Write operation status bits indicate program and erase operation completion Unlock Bypass Program command to reduce programming time Support for CFI (Common Flash Interface) Persistent and Password methods of Advanced Sector Protection WP#/ACC input
– Accelerates programming time (when VHH is applied) for greater throughput during system production – Protects first or last sector regardless of sector protection settings
Uniform 64Kword/128KByte Sector Architecture
– – – – S29GL01GP: One thousand twenty-four sectors S29GL512P: Five hundred twelve sectors S29GL256P: Two hundred fifty-six sectors S29GL128P: One hundred twenty-eight sectors
Hardware reset input (RESET#) resets device Ready/Busy# output (RY/BY#) detects program or erase cycle completion
100,000 erase cycles per sector typical 20-year data retention typical
Publication Number S29GL-P_00
Revision A
Amendment 7
Issue Date November 8, 2007
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Data
Sheet
(Preliminary)
Performance Characteristics
Maximum Read Access Times (ns) Density Voltage Range (1) Regulated VCC 128 & 256 Mb Full VCC VersatileIO VIO Regulated VCC 512 Mb Full VCC VersatileIO VIO Regulated VCC 1 Gb Full VCC VersatileIO VIO Random Access Time (tACC) 90 100/110 110 100 100 (2)/110 110 (2)/120 110 120 130 25 25 25 Page Access Time (tPACC) CE# Access Time (tCE) 90 100/110 110 100 100 (2)/110 110 (2)/120 110 120 130 25 25 25 OE# Access Time (tOE)
Notes 1. Access times are dependent on VCC and VIO operating ranges. See Ordering Information page for further details. Regulated VCC: VCC = 3.0–3.6 V. Full VCC: VCC = VIO = 2.7–3.6 V. VersatileIO VIO: VIO = 1.65–VCC, VCC = 3 V. 2. Contact a sales representative for availability.
Current Consumption (typical values) Random Access Read (f = 5 MHz) 8-Word Page Read (f = 10 MHz) Program/Erase Standby 30 mA 1 mA 50 mA 1 µA
Program & Erase Times (typical values) Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VHH) Per Word Sector Erase Time (64 Kword Sector) 60 µs 15 µs 13.5 µs 0.5 s
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S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2. 3. 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Special Handling Instructions for BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 TS056—56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Specification Bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Hardware and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 14 16 17 17 17 17 17
5.
6. 7.
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 VersatileIOTM (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Factory Locked Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Customer Lockable Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 20 20 21 24 36 40 42 43 43 45 45 48 48 49 49 49 49 49 50 50 50 51 52 52 53 53 54 54 55 56
8.
9.
10.
11.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
5
Data
Sheet
(Preliminary)
12.
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.2 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Advance Information on S29GL-R 65 nm MirrorBit Hardware Reset (RESET#) and Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13. 14.
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S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
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(Preliminary)
Figures
Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 8.1 Figure 8.2 Figure 8.3 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12 Figure 11.13 Figure 11.14 Figure 11.15 Figure 13.1 Figure 13.2 S29GL-P Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 64-ball Fortified Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LAA064—64ball Fortified Ball Grid Array (FBGA), 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . .14 56-pin Standard TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write Buffer Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PPB Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-up Sequence Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 65 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Power-On Reset Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
November 8, 2007 S29GL-P_00_A7
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7
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(Preliminary)
Tables
Table 2.1 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Table 7.13 Table 7.14 Table 7.15 Table 7.16 Table 7.17 Table 7.18 Table 8.1 Table 8.2 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 Table 11.7 Table 11.8 Table 11.9 Table 12.1 Table 12.2 Table 12.3 Table 12.4 Table 12.5 Table 12.6 Table 12.7 Table 12.8 Table 13.1 Table 13.2 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 S29GL01GP Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 S29GL512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 S29GL256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 S29GL128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Autoselect Addresses in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Autoselect Entry in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Single Word/Byte Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations . . . . . . . . . . . . . . .48 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 S29GL-P DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 S29GL-P Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Power-up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 S29GL-P Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 S29GL-P Alternate CE# Controlled Erase and Program Operations . . . . . . . . . . . . . . . . . . .64 Erase And Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 S29GL-P Memory Array Command Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 S29GL-P Sector Protection Command Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 S29GL-P Memory Array Command Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 S29GL-P Sector Protection Command Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Power-Up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
12 F F I 01 0 PACKING TYPE 0 = Tray (standard; see (Note 4) 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER (VIO range, protection when WP# =VIL) 01 = VIO = VCC = 2.7 to 3.6 V, highest address sector protected 02 = VIO = VCC = 2.7 to 3.6 V, lowest address sector protected V1 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, highest address sector protected V2 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, lowest address sector protected R1 = VIO = VCC = 3.0 to 3.6 V, highest address sector protected R2 = VIO = VCC = 3.0 to 3.6 V, lowest address sector protected TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE MATERIALS SET A = Pb (Note 1) F = Pb-free PACKAGE TYPE T = 56-pin Thin Small Outline Package (TSOP) Standard Pinout(TSO56) F = 64-ball Fortified Ball Grid Array, 1.0 mm pitch package (LAA064) SPEED OPTION 90 = 90 ns 10 = 100 ns 11 = 110 ns 12 = 120 ns 13 = 130 ns DEVICE NUMBER/DESCRIPTION S29GL01GP, S29GL512P, S29GL256P, S29GL128P 3.0 Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured on 90 nm MirrorBit® process technology
S29GL01GP
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
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Data
Sheet
(Preliminary)
Recommended Combinations
Recommended Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific recommended combinations and to check on newly released combinations.
S29GL-P Valid Combinations Speed 11 12 13 S29GL01GP 11 12 13 10 10 (1), 11 S29GL512P 11(1), 12 10 10 (1), 11 11(1), 12 90 10, 11 S29GL256P, S29GL128P 11 90 10, 11 11 Notes 1. Contact a local sales representative for availability. 2. TSOP package marking omits packing type designator from ordering part number. 3. BGA package marking omits leading “S29” and packing type designator from ordering part number. 4. Type 0 is standard. Specify other options as required. FAI (1)(3) FFI (3) TAI (1)(2) TFI (2) FAI (1)(3) FFI (3) TAI (1)(2) TFI (2) FAI (1)(3) FFI (3) R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 R1, R2 01, 02 V1, V2 0, 2, 3 (4) 0, 3 (4) 0, 2, 3 (4) 0, 3 (4) 0, 2, 3 (4) TAI (1)(2) TFI (2) Package & Temperature Model Number R1, R2 01, 02 V1, V2 0, 3 (4) Packing Type
10
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
2. Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions
Symbol Type Address lines for GL01GP A24–A0 for GL512P A23–A0 for GL256P, A22–A0 for GL128P. Data input/output. DQ15: Data input/output in word mode. A-1: LSB address input in byte mode. Chip Enable. Output Enable. Write Enable. Device Power Supply. Versatile IO Input. Ground. Not connected internally. Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the device is actively erasing or programming. At High Z, the device is in ready. Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active. Hardware Reset. Low = device resets and returns to reading array data. Write Protect/Acceleration Input. At VIL, disables program and erase functions in the outermost sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pullup; when unconnected, WP# is at VIH. Reserved for future use. Description
A25–A0
Input
DQ14–DQ0 DQ15/A-1 CE# OE# WE# VCC VIO VSS NC RY/BY#
I/O I/O Input Input Input Supply Supply Supply No Connect Output
BYTE# RESET#
Input Input
WP#/ACC
Input
RFU
Reserved
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Data
Sheet
(Preliminary)
3. Block Diagram
Figure 3.1 S29GL-P Block Diagram
RY/BY#
DQ15–DQ0
Sector Switches
VCC VSS VIO RESET#
Erase Voltage Generator
Input/Output Buffers
WE# WP#/ACC BYTE#
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
Y-Decoder STB
Y-Gating
VCC Detector
Timer
Address Latch
X-Decoder
Cell Matrix
AMax**–A0 (A-1)
** AMax GL01GP=A25, AMax GL512P = A24, AMax GL256P = A23, AMax GL128P = A22
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29GL-P family.
4.1
Related Documents
The following documents contain information relating to the S29GL-P devices. Click on the title or go to www.spansion.com download the PDF file, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
12
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
Figure 4.1 64-ball Fortified Ball Grid Array
Top View, Balls Facing Down
RFU on S29GL128P RFU on S29GL256P RFU on S29GL512P
A8 RFU A7 A13 A6 A9 A5 WE# A4
B8 A22 B7 A12 B6 A8 B5 RESET# B4
C8 A23 C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 RFU
D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 RFU
E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 RFU
F8 A24 F7 BYTE# F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO
G8 A25 G7 DQ15/A-1 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 RFU
H8 RFU H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 RFU
RY/BY# WP#/ACC A3 A7 A2 A3 A1 RFU B3 A17 B2 A4 B1 RFU
Do not connect to VIL or VSS
Note RFU = No Connect (NC)
November 8, 2007 S29GL-P_00_A7
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13
Data
Sheet
(Preliminary)
4.3
LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm
Figure 4.2 LAA064—64ball Fortified Ball Grid Array (FBGA), 11 x 13 mm
14
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
Figure 4.3 56-pin Standard TSOP (Top View)
NC on S29GL128P NC on S29GL256P NC on S29GL512P
A23 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
A24 A25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Do not connect to VIL or VSS RFU VIO
Note RFU = No Connect (NC)
November 8, 2007 S29GL-P_00_A7
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Data
Sheet
(Preliminary)
4.4
TS056—56-Pin Standard Thin Small Outline Package (TSOP)
Figure 4.4 56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm
PACKAGE JEDEC SYMBOL A A1 A2 b1 b c1 c D D1 E e L
O
TS 56 MO-142 (B) EC MIN. --0.05 0.95 0.17 0.17 0.10 0.10 19.80 18.30 13.90 0.50 0˚ 0.08 NOM. ----1.00 0.20 0.22 ----20.00 18.40 14.00 0.50 BASIC 0.60 --56 0.70 8˚ 0.20 MAX. 1.20 0.15 1.05 0.23 0.27 0.16 0.21 20.20 18.50 14.10
NOTES: 1 2 3 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm. THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
4 5
6 7 8
R N
3160\38.10A
16
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
5.
Additional Resources
Visit www.spansion.com to obtain the following related documents:
5.1
Application Notes
The following is a list of application notes related to this product. All Spansion application notes are available at http://www.spansion.com/support/technical_documents/application_notes.html Using the Operation Status Bits in AMD Devices Understanding Page Mode Flash Memory Devices MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read Common Flash Interface Version 1.4 Vendor Specific Extensions MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read Taking Advantage of Page Mode Read on the MCF5407 Coldfire Migration to S29GL128N and S29GL256N based on 110nm MirrorBit® Technology Optimizing Program/Erase Times Practical Guide to Endurance and Data Retention Configuring FPGAs using Spansion S29GL-N Flash Connecting Spansion™ Flash Memory to a System Address Bus Connecting Unused Data Lines of MirrorBit® Flash Reset Voltage and Timing Requirements for MirrorBit® Flash Versatile IO: DQ and Enhanced
5.2
Specification Bulletins
Contact your local sales office for details.
5.3
Hardware and Software Support
Downloads and related information on Flash device support is available at www.spansion.com/support/index.html Spansion low-level drivers Enhanced Flash drivers Flash file system Downloads and related information on simulation modeling and CAD modeling support is available at http:// www.spansion.com/support/simulation_models.html VHDL and Verilog IBIS ORCAD An FAQ (Frequently Asked Questions) list is available at www.spansion.com/support/ses/index.html
5.4
Contacting Spansion
Obtain the latest list of company locations and contact information on our web site at www.spansion.com/about/location.html
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
17
Data
Sheet
(Preliminary)
6.
Product Overview
The S29GL-P family consists of 1 Gb, 512 Mb, 256 Mb and 128 Mb, 3.0-volt-only, page mode Flash devices optimized for today’s embedded designs that demand a large storage array and rich functionality. These devices are manufactured using 90 nm MirrorBit technology. These products offer uniform 64 Kword (128 Kb) uniform sectors and feature VersatileIO control, allowing control and I/O signals to operate from 1.65 V to VCC. Additional features include: Single word programming or a 32-word buffer for an increased programming speed Program Suspend/Resume and Erase Suspend/Resume Advanced Sector Protection methods for protecting sectors as required 128 words/256 bytes of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable.
6.1
Memory Map
The S29GL-P devices consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 6.1– Table 6.4. Table 6.1 S29GL01GP Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range SA00 64 Kword/128 Kb 1024 : SA1023 Address Range (16-bit) 0000000h - 000FFFFh : 3FF0000H - 3FFFFFFh Sector Ending Address Notes Sector Starting Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA001-SA1022) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
Table 6.2 S29GL512P Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range SA00 64 Kword/128 Kb 512 : SA511 Address Range (16-bit) 0000000h - 000FFFFh : 1FF0000H - 1FFFFFFh Sector Ending Address Notes Sector Starting Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
Table 6.3 S29GL256P Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range SA00 64 Kword/128 Kb 256 : SA255 Address Range (16-bit) 0000000h - 000FFFFh : 0FF0000H - 0FFFFFFh Sector Ending Address Notes Sector Starting Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA001-SA254) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
18
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
Data
Sheet
(Preliminary)
Table 6.4 S29GL128P Sector & Memory Address Map
Uniform Sector Size Sector Count Sector Range SA00 64 Kword/128 Kb 128 : SA127 Address Range (16-bit) 0000000h - 000FFFFh : 07F0000 - 7FFFFF Sector Ending Address Notes Sector Starting Address
Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
7. Device Operations
This section describes the read, program, erase, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 12.1 through Table 12.4). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must pull the RESET# pin low or power cycle the device to return the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state of each control pin for any particular operation. Table 7.1 Device Operations
Addresses (Note 1) AIN AIN AIN X X X DQ8–DQ15 DQ0–DQ7 DOUT (Note 3) (Note 3) High-Z High-Z High-Z BYTE#= VIH DOUT (Note 3) (Note 3) High-Z High-Z High-Z BYTE#= VIL DQ8–DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset
CE# L L L VCC ± 0.3 V L X
OE# L H H X H X
WE# H L L X H X
RESET# H H H VCC ± 0.3 V H L
WP#/ACC X (Note 2) VHH H X X
Legend L = Logic Low = VIL, H = Logic High = VIH, VHH = 11.5–12.5V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes 1. Addresses are AMax:A0 in word mode; AMax:A-1 in byte mode. 2. If WP# = VIL, on the outermost sector remains protected. If WP# = VIH, the outermost sector is unprotected. WP# has an internal pull-up; when unconnected, WP# is at VIH. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.) 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm.
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Data
Sheet
(Preliminary)
7.2
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.3
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and DQ signals). VIO range is 1.65 to VCC. See Ordering Information on page 9 for VIO options on this device. For example, a VIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus.
7.4
Read
All memories require access time to output array data. In a read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. The device defaults to reading array data after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#, assuming the tACC access time has been meet.
7.5
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3. Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within a page. The microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
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7.6
Autoselect
The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register (separate from the memory array) on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm (see Table 7.3). The Autoselect codes can also be accessed in-system. There are two methods to access autoselect codes. One uses the autoselect command, the other applies VID on address pin A9. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins must be as shown in Table 7.2. To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously in Erase Suspend). It is recommended that A9 apply VID after power-up sequence is completed. In addition, it is recommended that A9 apply from VID to VIH/VIL before power-down the VCC/VIO. See Table 12.1 on page 68 for command sequence details. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 7.4 to Table 7.5). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register.
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Table 7.2 Autoselect Codes, (High Voltage Method)
Amax A14 to to CE# OE# WE# A16 A10 L L H X X A8 to A7 X A5 to A4 X A3 to A2 L L L L H X X VID X L X H H L L L H X X VID X L X H H L L L H X X VID X L X H H L L L H X X VID X L X H H L L H SA X VID X L X L DQ8 to DQ15 A1 L L H H L H H L H H L H H H A0 L H L H H L H H L H H L H L BYTE# BYTE# = VIL = VIH 00 22 22 22 22 22 22 22 22 22 22 22 22 X X X X X X X X X X X X X X X DQ7 to DQ0 01h 7Eh 28h 01h 7Eh 23h 01h 7Eh 22h 01h 7Eh 21h 01h 01h (protected), 00h (unprotected) 99h (factory locked), 19h (not factory locked) 89h (factory locked), 09h (not factory locked)
Description Manufacturer ID: Spansion Product S29GL128P S29GL256P S29GL512P S29GL01GP Device ID Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3
A9 VID
A6 L
Sector Group Protection Verification Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector
Device ID
Device ID
Device ID
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
Legend L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. VID = 11.5V to 12.5V
Table 7.3 Autoselect Addresses in System
Description Manufacturer ID Device ID, Word 1 Address (Base) + 00h (Base) + 01h xx01h/1h 227Eh/7Eh 2228h/28h (GL01GP) 2223h/23h (GL512P) 2222h/22h (GL256P) 2221h/21h (GL128P) 2201h/01h For S29GLxxxPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. For S29GLxxxPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked. xx01h/01h = Locked, xx00h/00h = Unlocked Read Data (word/byte mode)
Device ID, Word 2
(Base) + 0Eh
Device ID, Word 3 Secure Device Verify Sector Protect Verify
(Base) + 0Fh (Base) + 03h (SA) + 02h
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Table 7.4 Autoselect Entry in System
(LLD Function = lld_AutoselectEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Byte Address Base + AAAh Base + 555h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 0x00AAh 0x0055h 0x0090h
Software Functions and Sample Code
Table 7.5 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd) Cycle Unlock Cycle 1
Note 1. Any offset within the device works. 2. base = base address.
Operation Write
Byte Address base + XXXh
Word Address base + XXXh
Data 0x00F0h
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)base_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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7.7
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles within the command sequence. See Section 7.7.8 for details on the Unlock Bypass function. Note the following: When the Embedded Program algorithm is complete, the device returns to the read mode. The system can determine the status of the program operation by reading the DQ status bits. Refer to the Write Operation Status on page 36 for information on these status bits. An “0” cannot be programmed back to a “1.” A succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Any commands written to the device during the Embedded Program/Erase are ignored except the Suspend commands. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. Programming is allowed in any sequence and across sector boundaries for single word programming operation. See Write Buffer Programming on page 26 when using the write buffer. Programming to the same word address multiple times without intervening erases is permitted.
7.7.1
Single Word Programming
Single word programming mode is one method of programming the Flash. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8 or 16-bits wide. While the single word programming method is supported by most Spansion devices, in general Single Word Programming is not recommended for devices that support Write Buffer Programming. See Table 12.1 on page 68 for the required bus cycles and Figure 7.1 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by reading the DQ status bits. Refer to Write Operation Status on page 36 for information on these status bits. During programming, any command (except the Suspend Program command) is ignored. The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming to the same address multiple times continuously (for example, “walking” a bit within a word) is permitted.
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Figure 7.1 Single Word Program
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2
Write Program Command: Address 555h, Data A0h
Setup Command
Program Data to Address: PA, PD
Program Address (PA), Program Data (PD)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Busy? No Yes Polling Status = Done? No
Yes
Error condition (Exceeded Timing Limits)
PASS. Device is in read mode.
FAIL. Issue reset command to return to read array mode.
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Software Functions and Sample Code
Table 7.6 Single Word/Byte Program
(LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Note Base = Base Address.
Operation Write Write Write Write
Byte Address Base + AAAh Base + 555h Base + AAAh Byte Address
Word Address Base + 555h Base + 2AAh Base + 555h Word Address
Data 00AAh 0055h 00A0h Data
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */
7.7.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard “word” programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of “word locations minus 1” that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the “Program Buffer to Flash” confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The “write-buffer-page” is selected by using the addresses AMAX–A5. The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple “write-buffer-pages.” This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected “write-buffer-page”, the operation ABORTs.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter is decremented for every data load operation. Also, the last data loaded at a location before the “Program Buffer to Flash” confirm command is the data programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the “Program Buffer to Flash” command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The Write Operation Status bits should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then check the write operation status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming.
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The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the “Number of Locations to Program” step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address” during the “write buffer data loading” stage of the operation. Writing anything other than the Program to Buffer Flash Command after the specified number of “data load” cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A “Write-toBuffer-Abort reset” command sequence is required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed.
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Software Functions and Sample Code
Table 7.7 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Write Write Write Write Byte Address Base + AAAh Base + 555h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N–1)h
Sector Address Sector Address
Number of words (N) loaded into the write buffer can be from 1 to 32 words (1 to 64 bytes). 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h
Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */
for (i=0;i
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