S29NS128P0PBJW003

厂商：
SPANSION(飞索)
封装：
描述：
S29NS128P0PBJW003 - MirrorBit Flash Family - SPANSION

数据手册：

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数据手册
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S29NS128P0PBJW003 数据手册

S29NS-P MirrorBitTM Flash Family S29NS512P S29NS256P S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory Data Sheet (Advance Information) S29NS-P MirrorBitTM Flash Family Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S29NS-P_00 Revision A Amendment 1 Issue Date February 20, 2007 Data Sheet (Advance Information) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. 2 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 S29NS-P MirrorBitTM Flash Family S29NS512P S29NS256P S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory Data Sheet (Advance Information) Features Single 1.8 V read/program/erase (1.70–1.95 V) 90 nm MirrorBit Technology Multiplexed Data and Address for reduced I/O count Simultaneous Read/Write operation Full/Half drive output slew rate control 32-word Write Buffer Sixteen-bank architecture consisting of 64/32/16 MB for NS512/256/128P, respectively Four 32 KB sectors at the top of memory array (NS256/128P) 512 128KB sectors (NS512P), 255/127 128KB sectors (NS256/ 128P) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) RDY output indicates data available to system Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of highest two sectors Top Boot sector configuration (NS256/128P) Handshaking by monitoring RDY Offered Packages – NS512P: 64-ball FBGA (8 mm x 9.2 mm) – NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings VPP input pin to reduce factory programming time Support for Common Flash Interface (CFI) Performance Characteristics Read Access Times Speed Option (MHz) Max. Synch. Latency, ns (tIACC) Max. Synch. Burst Access, ns (tBACC) Max. Asynch. Access Time, ns (tACC) Max OE# Access Time, ns (tOE) 108 80 7.0 80 7.0 Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VPP) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 30 µs 6 µs 4 µs 350 ms 600 ms Current Consumption (typical values) Continuous Burst Read @ 108 MHz Simultaneous Operation 108 MHz Program Standby Mode 42 mA 60 mA 30 mA 20 µA General Description The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 108 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption. Publication Number S29NS-P_00 Revision A Amendment 1 Issue Date February 20, 2007 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Data Sheet (Advance Information) Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2. 3. 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Programmable Output Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Secured Silicon Sector Entry and Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 33 35 50 50 50 50 50 51 52 52 53 55 56 56 58 59 60 60 60 60 60 61 61 61 62 64 64 64 65 66 66 66 67 67 77 5. 6. 7. 8. 9. 10. 11. 12. 4 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figures Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 7.2 Figure 7.3 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P. . . . . . . . . . . . . . . . . . 12 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13 Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VCC Power-Up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 68 8-Word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . 69 Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 5 Data Sheet (Advance Information) Tables Table 2.1 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 6.9 Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table 6.14 Table 6.15 Table 6.16 Table 6.17 Table 6.18 Table 6.19 Table 6.20 Table 6.21 Table 6.22 Table 6.23 Table 6.24 Table 6.25 Table 6.26 Table 6.27 Table 6.28 Table 6.29 Table 7.1 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 6 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 S29NS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 S29NS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 S29NS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Address Latency for 2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Programmable Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Secured Silicon SectorSecure Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) . . . . . . . . . . . . . .62 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) . . . . . . . . . . . . . . . . . . .62 Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) . . . . . . . . . . . . . . . . .63 DC Characteristics—CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 VCC Power-Up with No Ramp Rate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 1. Ordering Information The ordering part number is formed by a valid combination of the following: S29NS 512 P xx BJ W 00 0 Packing Type 0 = Tray (standard; (Note 1)) 3 = 13-inch Tape and Reel Model Number 00 = Standard Temperature Range W = Wireless (–25°C to +85°C) Package Type & Material Set BJ = Very Thin Fine-Pitch BGA,Lead (Pb)-free LF35 Package Speed Option (Burst Frequency) 0P = 66 MHz 0S = 83 MHz AB = 108 MHz Process Technology P = 90 nm MirrorBit™ Technology Flash Density 512 =512 Mb 256 =256 Mb 128 =128 Mb Product Family S29NS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory Valid Combinations Base Ordering Part Number S29NS512P S29NS256P S29NS128P Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. 0P, 0S, AB BJW (Lead (Pb)-free, LF35) 0, 3 (1) 00 6.2 mm x 7.7 mm, 44-ball Speed Option Package Type Package Type, Material, & Temperature Range Packing Type Model Number 8.0 mm x 9.2 mm, 64-ball Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 7 Data Sheet (Advance Information) 2. Input/Output Descriptions & Logic Symbol Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Symbol A24 – A16 A23 – A16 A22 – A16 A/DQ15 – A/DQ0 CE# OE# WE# VCC VCCQ VSS VSSQ NC RDY CLK Type Input Input Input I/O Input Input Input Supply Supply I/O I/O No Connect Output Input Address inputs, S29NS512P Address inputs, S29NS256P Address inputs, S29NS128P Multiplexed Address/Data input/output Chip Enable. Asynchronous relative to CLK for the Burst mode. Output Enable. Asynchronous relative to CLK for the Burst mode Write Enable Device Power Supply Input/Output Power Supply (must be ramped simultaneously with VCC) Ground Input/Output Ground No Connected internally Ready. Indicates when valid burst data is ready to be read The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of CLK. VIH = device ignores address inputs Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL,disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use Description AVD# Input RESET# WP# Input Input VPP Input RFU Reserved 8 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 3. Block Diagrams Figure 3.1 Simultaneous Operation Circuit VCC Bank Address Y-Decoder VSS VCCQ VSSQ Latches and Control Logic DQ15–DQ0 Bank 0 Amax–A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder DQ15–DQ0 Bank 1 WP# VPP RESET# WE# CE# AVD# RDY A/DQ15–A/DQ0 ?Amax–A0 X-Decoder DQ15–DQ0 Status STATE CONTROL & COMMAND REGISTER ?Amax–A16 Control X-Decoder Latches and Control Logic Y-Decoder Bank Address Bank (n-1) DQ15–DQ0 ?Amax–A16 X-Decoder Bank Address Latches and Control Logic Y-Decoder Bank (n) DQ15–DQ0 Notes 1. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P. 2. Bank (n) = 15 for NS512P/ NS256P/ NS128P. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 9 Data Sheet (Advance Information) 4. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the OPN. 4.1 Related Documents The following documents contain information relating to the S29NS-P devices. Click on the title or go to www.spansion.com, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 64-Ball Fine-Pitch Grid Array, S29NS512P Figure 4.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down 1 A nc B nc 2 3 4 5 6 7 8 9 10 11 12 13 14 C DNU D F-RDY E F-VCCQ F F-VSS G A/DQ15 A/DQ14 H DNU J DNU DNU F-VCCQ F-VSSQ DPD F-VCCQ DNU DNU DNU Do Not Use F-VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 F-VCCQ A/DQ1 A/DQ0 A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 F-OE# Reserved for Future Use A16 A20 F-ADV# A23 F-RST# F-WP# A18 F-CE# F-VSSQ No Connect A21 F-VSS F-CLK F-VCC F-WE# F-ACC A19 A17 A22 Flash Only DNU F-VSS A24 F-VCC F-VSS F-VCC A25 DNU DNU Legend K nc nc Figure 2.1. 10 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 VSS D1 A2 A21 B2 A16 C2 A/DQ7 D2 A3 VSS B3 A20 C3 A/DQ6 D3 VSSQ A4 CLK B4 AVD# C4 A/DQ13 D4 A/DQ5 A5 VCC B5 A23 C5 A/DQ12 D5 A/DQ4 A6 WE# B6 RESET# C6 A/DQ3 D6 A7 VPP B7 WP# C7 A/DQ2 D7 A8 A19 B8 A18 C8 A/DQ9 D8 VCCQ A9 A17 B9 CE# C9 A/DQ8 D9 A/DQ1 A10 A22 B10 VSSQ C10 OE# D10 A/DQ0 A/DQ15 A/DQ14 A/DQ11 A/DQ10 NC NC 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Figure 4.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 VSS D1 A2 A21 B2 A16 C2 A/DQ7 D2 A3 VSS B3 A20 C3 A/DQ6 D3 VSSQ A4 CLK B4 AVD# C4 A/DQ13 D4 A/DQ5 A5 VCC B5 NC C5 A/DQ12 D5 A/DQ4 A6 WE# B6 RESET# C6 A/DQ3 D6 A7 VPP B7 WP# C7 A/DQ2 D7 A8 A19 B8 A18 C8 A/DQ9 D8 VCCQ A9 A17 B9 CE# C9 A/DQ8 D9 A/DQ1 A10 A22 B10 VSSQ C10 OE# D10 A/DQ0 A/DQ15 A/DQ14 A/DQ11 A/DQ10 NC NC February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 11 Data Sheet (Advance Information) VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array Figure 4.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P 10 D A D1 e A1 CORNER A1 CORNER INDEX MARK 10 9 8 7 6 5 4 3 2 NF2 1 NF1 e A B C D E 7 E 0.50 NF4 NF3 SE E1 F TOP VIEW A A1 A2 B 1.00 SD 7 Øb 0.10 C 6 Ø 0.05 M C Ø 0.15 M C A B SEATING PLANE C 0.08 C BOTTOM VIEW SIDE VIEW NOTES: PACKAGE JEDEC VDD 064 N/A 8.00 mm x 9.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N Øb 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT 0.35 BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 4. e REPRESENTS THE SOLDER BALL GRID PITCH. MIN 0.86 0.20 0.66 7.90 9.10 NOM ----0.71 8.00 9.20 4.50 2.50 10 6 64 MAX 1.00 --0.76 8.10 9.30 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3533 \ 16-038.27 \ 12.13.05 0.25 0.30 0.50 0.25 e SD / SE 12 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) VDE44-44-Ball Very Thin Fine-Pitch Ball Grid Array, 6.2mm x 7.7 mm Figure 4.5 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P A1 CORNER INDEX MARK 10 D A D1 A1 CORNER 10 9 8 7 6 5 4 3 2 1 NF2 NF1 e A E 1.00 NF4 NF3 B C D SE 7 E1 1.00 TOP VIEW B SD φb 7 6 φ 0.05 M C φ 0.15 M C A B A A1 A2 0.10 C BOTTOM VIEW SIDE VIEW SEATING PLANE C 0.08 C NOTES: PACKAGE JEDEC VDE 044 N/A 7.70 mm x 6.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE ? 0.25 MIN 0.86 0.20 0.66 7.6 6.1 NOM ----0.71 7.7 6.2 4.50 1.50 10 4 44 0.30 0.50 BSC. 0.25 BSC. 0.35 MAX 1.00 --0.76 7.8 6.3 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ? THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3308.2 \ 16-038.9L February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 13 Data Sheet (Advance Information) 5. Product Overview The S29NS-P family consists of 512, 256, and 128 Mb, 1.8 volts-only, simultaneous read/write burst mode, multiplexed Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-word, 16-word, or 32-word aligned group) with or without wrap around. These flash devices multiplex the data and addresses for reduced I/O count. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable. 5.1 Memory Map The S29NS512/256/128P Mb devices consist of 16 banks organized as shown in Tables 5.1 – 5.3. Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 1 of 8) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h–00FFFFh 010000h–01FFFFh 020000h–02FFFFh 030000h–03FFFFh 040000h–04FFFFh 050000h–05FFFFh 060000h–06FFFFh 070000h–07FFFFh 080000h–08FFFFh 090000h–09FFFFh 0A0000h–0AFFFFh 0B0000h–0BFFFFh 0C0000h–0CFFFFh 0D0000h–0DFFFFh 0E0000h–0EFFFFh 0F0000h–0FFFFFh 100000h–10FFFFh 110000h–11FFFFh 120000h–12FFFFh 130000h–13FFFFh 140000h–14FFFFh 150000h–15FFFFh 160000h–16FFFFh 170000h–17FFFFh 180000h–18FFFFh 190000h–19FFFFh 1A0000h–1AFFFFh 1B0000h–1BFFFFh 1C0000h–1CFFFFh 1D0000h–1DFFFFh 1E0000h–1EFFFFh 1F0000h–1FFFFFh Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 200000h–20FFFFh 210000h–21FFFFh 220000h–22FFFFh 230000h–23FFFFh 240000h–24FFFFh 250000h–25FFFFh 260000h–26FFFFh 270000h–27FFFFh 280000h–28FFFFh 290000h–29FFFFh 2A0000h–2AFFFFh 2B0000h–2BFFFFh 2C0000h–2CFFFFh 2D0000h–2DFFFFh 2E0000h–2EFFFFh 2F0000h–2FFFFFh 300000h–30FFFFh 310000h–31FFFFh 320000h–32FFFFh 330000h–33FFFFh 340000h–34FFFFh 350000h–35FFFFh 360000h–36FFFFh 370000h–37FFFFh 380000h–38FFFFh 390000h–39FFFFh 3A0000h–3AFFFFh 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh 3E0000h–3EFFFFh 3F0000h–3FFFFFh SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 Bank 1 Bank 0 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 14 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 2 of 8) Bank Sector SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 Bank 2 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 400000h–40FFFFh 410000h–41FFFFh 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh 4E0000h–4EFFFFh 4F0000h–4FFFFFh 500000h–50FFFFh 510000h–51FFFFh 520000h–52FFFFh 530000h–53FFFFh 540000h–54FFFFh 550000h–55FFFFh 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh 5A0000h–5AFFFFh 5B0000h–5BFFFFh 5C0000h–5CFFFFh 5D0000h–5DFFFFh 5E0000h–5EFFFFh 5F0000h–5FFFFFh Bank 3 Bank Sector SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 600000h–60FFFFh 610000h–61FFFFh 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh 6E0000h–6EFFFFh 6F0000h–6FFFFFh 700000h–70FFFFh 710000h–71FFFFh 720000h–72FFFFh 730000h–73FFFFh 740000h–74FFFFh 750000h–75FFFFh 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh 7A0000h–7AFFFFh 7B0000h–7BFFFFh 7C0000h–7CFFFFh 7D0000h–7DFFFFh 7E0000h–7EFFFFh 7F0000h–7FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 15 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 3 of 8) Bank Sector SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 Bank 4 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 800000h–80FFFFh 810000h–81FFFFh 820000h–82FFFFh 830000h–83FFFFh 840000h–84FFFFh 850000h–85FFFFh 860000h–86FFFFh 870000h–87FFFFh 880000h–88FFFFh 890000h–89FFFFh 8A0000h–8AFFFFh 8B0000h–8BFFFFh 8C0000h–8CFFFFh 8D0000h–8DFFFFh 8E0000h–8EFFFFh 8F0000h–8FFFFFh 900000h–90FFFFh 910000h–91FFFFh 920000h–92FFFFh 930000h–93FFFFh 940000h–94FFFFh 950000h–95FFFFh 960000h–96FFFFh 970000h–97FFFFh 980000h–98FFFFh 990000h–99FFFFh 9A0000h–9AFFFFh 9B0000h–9BFFFFh 9C0000h–9CFFFFh 9D0000h–9DFFFFh 9E0000h–9EFFFFh 9F0000h–9FFFFFh Bank 5 Bank Sector SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range A00000h–A0FFFFh A10000h–A1FFFFh A20000h–A2FFFFh A30000h–A3FFFFh A40000h–A4FFFFh A50000h–A5FFFFh A60000h–A6FFFFh A70000h–A7FFFFh A80000h–A8FFFFh A90000h–A9FFFFh AA0000h–AAFFFFh AB0000h–ABFFFFh AC0000h–ACFFFFh AD0000h–ADFFFFh AE0000h–AEFFFFh AF0000h–AFFFFFh B00000h–B0FFFFh B10000h–B1FFFFh B20000h–B2FFFFh B30000h–B3FFFFh B40000h–B4FFFFh B50000h–B5FFFFh B60000h–B6FFFFh B70000h–B7FFFFh B80000h–B8FFFFh B90000h–B9FFFFh BA0000h–BAFFFFh BB0000h–BBFFFFh BC0000h–BCFFFFh BD0000h–BDFFFFh BE0000h–BEFFFFh BF0000h–BFFFFFh 16 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 4 of 8) Bank Sector SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 Bank 6 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range C00000h–C0FFFFh C10000h–C1FFFFh C20000h–C2FFFFh C30000h–C3FFFFh C40000h–C4FFFFh C50000h–C5FFFFh C60000h–C6FFFFh C70000h–C7FFFFh C80000h–C8FFFFh C90000h–C9FFFFh CA0000h–CAFFFFh CB0000h–CBFFFFh CC0000h–CCFFFFh CD0000h–CDFFFFh CE0000h–CEFFFFh CF0000h–CFFFFFh D00000h–D0FFFFh D10000h–D1FFFFh D20000h–D2FFFFh D30000h–D3FFFFh D40000h–D4FFFFh D50000h–D5FFFFh D60000h–D6FFFFh D70000h–D7FFFFh D80000h–D8FFFFh D90000h–D9FFFFh DA0000h–DAFFFFh DB0000h–DBFFFFh DC0000h–DCFFFFh DD0000h–DDFFFFh DE0000h–DEFFFFh DF0000h–DFFFFFh Bank 7 Bank Sector SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range E00000h–E0FFFFh E10000h–E1FFFFh E20000h–E2FFFFh E30000h–E3FFFFh E40000h–E4FFFFh E50000h–E5FFFFh E60000h–E6FFFFh E70000h–E7FFFFh E80000h–E8FFFFh E90000h–E9FFFFh EA0000h–EAFFFFh EB0000h–EBFFFFh EC0000h–ECFFFFh ED0000h–EDFFFFh EE0000h–EEFFFFh EF0000h–EFFFFFh F00000h–F0FFFFh F10000h–F1FFFFh F20000h–F2FFFFh F30000h–F3FFFFh F40000h–F4FFFFh F50000h–F5FFFFh F60000h–F6FFFFh F70000h–F7FFFFh F80000h–F8FFFFh F90000h–F9FFFFh FA0000h–FAFFFFh FB0000h–FBFFFFh FC0000h–FCFFFFh FD0000h–FDFFFFh FE0000h–FEFFFFh FF0000h–FFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 17 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 5 of 8) Bank Sector SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 SA270 Bank 8 SA271 SA272 SA273 SA274 SA275 SA276 SA277 SA278 SA279 SA280 SA281 SA282 SA283 SA284 SA285 SA286 SA287 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1000000h-100FFFFh 1010000h-101FFFFh 1020000h-102FFFFh 1030000h-103FFFFh 1040000h-104FFFFh 1050000h-105FFFFh 1060000h-106FFFFh 1070000h-107FFFFh 1030000h-108FFFFh 1090000h-109FFFFh 10A0000h-10AFFFFh 10B0000h-10BFFFFh 10C0000h-10CFFFFh 10D0000h-10DFFFFh 10E0000h-10EFFFFh 10F0000h-10FFFFFh 1100000h-110FFFFh 1110000h-111FFFFh 1120000h-112FFFFh 1130000h-113FFFFh 1140000h-114FFFFh 1150000h-115FFFFh 1160000h-116FFFFh 1170000h-117FFFFh 1180000h-118FFFFh 1190000h-119FFFFh 11A0000h-11AFFFFh 11B0000h-11BFFFFh 11C0000h-11CFFFFh 11D0000h-11DFFFFh 11E0000h-11EFFFFh 11F0000h-11FFFFFh Bank 9 Bank Sector SA288 SA289 SA290 SA291 SA292 SA293 SA294 SA295 SA296 SA297 SA298 SA299 SA300 SA301 SA302 SA303 SA304 SA305 SA306 SA307 SA308 SA309 SA310 SA311 SA312 SA313 SA314 SA315 SA316 SA317 SA318 SA319 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1200000h-120FFFFh 1210000h-121FFFFh 1220000h-122FFFFh 1230000h-123FFFFh 1240000h-124FFFFh 1250000h-125FFFFh 1260000h-126FFFFh 1270000h-127FFFFh 1230000h-128FFFFh 1290000h-129FFFFh 12A0000h-12AFFFFh 12B0000h-12BFFFFh 12C0000h-12CFFFFh 12D0000h-12DFFFFh 12E0000h-12EFFFFh 12F0000h-12FFFFFh 1300000h-130FFFFh 1310000h-131FFFFh 1320000h-132FFFFh 1330000h-133FFFFh 1340000h-134FFFFh 1350000h-135FFFFh 1360000h-136FFFFh 1370000h-137FFFFh 1380000h-138FFFFh 1390000h-139FFFFh 13A0000h-13AFFFFh 13B0000h-13BFFFFh 13C0000h-13CFFFFh 13D0000h-13DFFFFh 13E0000h-13EFFFFh 13F0000h-13FFFFFh 18 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 6 of 8) Bank Sector SA320 SA321 SA322 SA323 SA324 SA325 SA326 SA327 SA328 SA329 SA330 SA331 SA332 SA333 SA334 Bank 10 SA335 SA336 SA337 SA338 SA339 SA340 SA341 SA342 SA343 SA344 SA345 SA346 SA347 SA348 SA349 SA350 SA351 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1400000h-140FFFFh 1410000h-141FFFFh 1420000h-142FFFFh 1430000h-143FFFFh 1440000h-144FFFFh 1450000h-145FFFFh 1460000h-146FFFFh 1470000h-147FFFFh 1430000h-148FFFFh 1490000h-149FFFFh 14A0000h-14AFFFFh 14B0000h-14BFFFFh 14C0000h-14CFFFFh 14D0000h-14DFFFFh 14E0000h-14EFFFFh 14F0000h-14FFFFFh 1500000h-150FFFFh 1510000h-151FFFFh 1520000h-152FFFFh 1530000h-153FFFFh 1540000h-154FFFFh 1550000h-155FFFFh 1560000h-156FFFFh 1570000h-157FFFFh 1580000h-158FFFFh 1590000h-159FFFFh 15A0000h-15AFFFFh 15B0000h-15BFFFFh 15C0000h-15CFFFFh 15D0000h-15DFFFFh 15E0000h-15EFFFFh 15F0000h-15FFFFFh Bank 11 Bank Sector SA352 SA353 SA354 SA355 SA356 SA357 SA358 SA359 SA360 SA361 SA362 SA363 SA364 SA365 SA366 SA367 SA368 SA369 SA370 SA371 SA372 SA373 SA374 SA375 SA376 SA377 SA378 SA379 SA380 SA381 SA382 SA383 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 1600000h-160FFFFh 1610000h-161FFFFh 1620000h-162FFFFh 1630000h-163FFFFh 1640000h-164FFFFh 1650000h-165FFFFh 1660000h-166FFFFh 1670000h-167FFFFh 1630000h-168FFFFh 1690000h-169FFFFh 16A0000h-16AFFFFh 16B0000h-16BFFFFh 16C0000h-16CFFFFh 16D0000h-16DFFFFh 16E0000h-16EFFFFh 16F0000h-16FFFFFh 1700000h-170FFFFh 1710000h-171FFFFh 1720000h-172FFFFh 1730000h-173FFFFh 1740000h-174FFFFh 1750000h-175FFFFh 1760000h-176FFFFh 1770000h-177FFFFh 1780000h-178FFFFh 1790000h-179FFFFh 17A0000h-17AFFFFh 17B0000h-17BFFFFh 15C0000h-17CFFFFh 17D0000h-17DFFFFh 17E0000h-17EFFFFh 17F0000h-17FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 19 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 7 of 8) Bank Sector SA384 SA385 SA386 SA387 SA388 SA389 SA390 SA391 SA392 SA393 SA394 SA395 SA396 SA397 SA398 Bank 12 SA399 SA400 SA401 SA402 SA403 SA404 SA405 SA406 SA407 SA408 SA409 SA410 SA411 SA412 SA413 SA414 SA415 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1800000h-180FFFFh 1810000h-181FFFFh 1820000h-182FFFFh 1830000h-183FFFFh 1840000h-184FFFFh 1850000h-185FFFFh 1860000h-186FFFFh 1870000h-187FFFFh 1830000h-188FFFFh 1890000h-189FFFFh 18A0000h-18AFFFFh 18B0000h-18BFFFFh 18C0000h-18CFFFFh 18D0000h-18DFFFFh 18E0000h-18EFFFFh 18F0000h-18FFFFFh 1900000h-190FFFFh 1910000h-191FFFFh 1920000h-192FFFFh 1930000h-193FFFFh 1940000h-194FFFFh 1950000h-195FFFFh 1960000h-196FFFFh 1970000h-197FFFFh 1980000h-198FFFFh 1990000h-199FFFFh 19A0000h-19AFFFFh 19B0000h-19BFFFFh 19C0000h-19CFFFFh 19D0000h-19DFFFFh 19E0000h-19EFFFFh 19F0000h-19FFFFFh Bank 13 Bank Sector SA416 SA417 SA418 SA419 SA420 SA421 SA422 SA423 SA424 SA425 SA426 SA427 SA428 SA429 SA430 SA431 SA432 SA433 SA434 SA435 SA436 SA437 SA438 SA439 SA440 SA441 SA442 SA443 SA444 SA445 SA446 SA447 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1A00000h-1A0FFFFh 1A10000h-1A1FFFFh 1A20000h-1A2FFFFh 1A30000h-1A3FFFFh 1A40000h-1A4FFFFh 1A50000h-1A5FFFFh 1A60000h-1A6FFFFh 1A70000h-1A7FFFFh 1A30000h-1A8FFFFh 1A90000h-1A9FFFFh 1AA0000h-1AAFFFFh 1AB0000h-1ABFFFFh 1AC0000h-1ACFFFFh 1AD0000h-1ADFFFFh 1AE0000h-1AEFFFFh 1AF0000h-1AFFFFFh 1B00000h-1B0FFFFh 1B10000h-1B1FFFFh 1B20000h-1B2FFFFh 1B30000h-1B3FFFFh 1B40000h-1B4FFFFh 1B50000h-1B5FFFFh 1B60000h-1B6FFFFh 1B70000h-1B7FFFFh 1B80000h-1B8FFFFh 1B90000h-1B9FFFFh 1BA0000h-1BAFFFFh 1BB0000h-1BBFFFFh 1BC0000h-1BCFFFFh 1BD0000h-1BDFFFFh 1BE0000h-1BEFFFFh 1BF0000h-1BFFFFFh 20 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 8 of 8) Bank Sector SA448 SA449 SA450 SA451 SA452 SA453 SA454 SA455 SA456 SA457 SA458 SA459 SA460 SA461 SA462 Bank 14 SA463 SA464 SA465 SA466 SA467 SA468 SA469 SA470 SA471 SA472 SA473 SA474 SA475 SA476 SA477 SA478 SA479 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1C00000h-1C0FFFFh 1C10000h-1C1FFFFh 1C20000h-1C2FFFFh 1C30000h-1C3FFFFh 1C40000h-1C4FFFFh 1C50000h-1C5FFFFh 1C60000h-1C6FFFFh 1C70000h-1C7FFFFh 1C30000h-1C8FFFFh 1C90000h-1C9FFFFh 1CA0000h-1CAFFFFh 1CB0000h-1CBFFFFh 1CC0000h-1CCFFFFh 1CD0000h-1CDFFFFh 1CE0000h-1CEFFFFh 1CF0000h-1CFFFFFh 1D00000h-1D0FFFFh 1D10000h-1D1FFFFh 1D20000h-1D2FFFFh 1D30000h-1D3FFFFh 1D40000h-1D4FFFFh 1D50000h-1D5FFFFh 1D60000h-1D6FFFFh 1D70000h-1D7FFFFh 1D80000h-1D8FFFFh 1D90000h-1D9FFFFh 1DA0000h-1DAFFFFh 1DB0000h-1DBFFFFh 1DC0000h-1DCFFFFh 1DD0000h-1DDFFFFh 1DE0000h-1DEFFFFh 1DF0000h-1DFFFFFh Bank 15 Bank Sector SA480 SA481 SA482 SA483 SA484 SA485 SA486 SA487 SA488 SA489 SA490 SA491 SA492 SA493 SA494 SA495 SA496 SA497 SA498 SA499 SA500 SA501 SA502 SA503 SA504 SA505 SA506 SA507 SA508 SA509 SA510 SA511 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 1E00000h-1E0FFFFh 1E10000h-1E1FFFFh 1E20000h-1E2FFFFh 1E30000h-1E3FFFFh 1E40000h-1E4FFFFh 1E50000h-1E5FFFFh 1E60000h-1E6FFFFh 1E70000h-1E7FFFFh 1E30000h-1E8FFFFh 1E90000h-1E9FFFFh 1EA0000h-1EAFFFFh 1EB0000h-1EBFFFFh 1EC0000h-1ECFFFFh 1ED0000h-1EDFFFFh 1EE0000h-1EEFFFFh 1EF0000h-1EFFFFFh 1F00000h-1F0FFFFh 1F10000h-1F1FFFFh 1F20000h-1F2FFFFh 1F30000h-1F3FFFFh 1F40000h-1F4FFFFh 1F50000h-1F5FFFFh 1F60000h-1F6FFFFh 1F70000h-1F7FFFFh 1F80000h-1F8FFFFh 1F90000h-1F9FFFFh 1FA0000h-1FAFFFFh 1FB0000h-1FBFFFFh 1FC0000h-1FCFFFFh 1FD0000h-1FDFFFFh 1FE0000h-1FEFFFFh 1FF0000h-1FFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 21 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 1 of 3) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank 0 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank 1 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Bank 4 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h–00FFFFh 010000h–01FFFFh 020000h–02FFFFh 030000h–03FFFFh 040000h–04FFFFh 050000h–05FFFFh 060000h–06FFFFh 070000h–07FFFFh 080000h–08FFFFh 090000h–09FFFFh 0A0000h–0AFFFFh 0B0000h–0BFFFFh 0C0000h–0CFFFFh 0D0000h–0DFFFFh 0E0000h–0EFFFFh 0F0000h–0FFFFFh 100000h–10FFFFh 110000h–11FFFFh 120000h–12FFFFh 130000h–13FFFFh 140000h–14FFFFh 150000h–15FFFFh 160000h–16FFFFh 170000h–17FFFFh 180000h–18FFFFh 190000h–19FFFFh 1A0000h–1AFFFFh 1B0000h–1BFFFFh 1C0000h–1CFFFFh 1D0000h–1DFFFFh 1E0000h–1EFFFFh 1F0000h–1FFFFFh 400000h–40FFFFh 410000h–41FFFFh 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh 4E0000h–4EFFFFh 4F0000h–4FFFFFh Bank 6 Bank 3 Bank 2 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h–20FFFFh 210000h–21FFFFh 220000h–22FFFFh 230000h–23FFFFh 240000h–24FFFFh 250000h–25FFFFh 260000h–26FFFFh 270000h–27FFFFh 280000h–28FFFFh 290000h–29FFFFh 2A0000h–2AFFFFh 2B0000h–2BFFFFh 2C0000h–2CFFFFh 2D0000h–2DFFFFh 2E0000h–2EFFFFh 2F0000h–2FFFFFh 300000h–30FFFFh 310000h–31FFFFh 320000h–32FFFFh 330000h–33FFFFh 340000h–34FFFFh 350000h–35FFFFh 360000h–36FFFFh 370000h–37FFFFh 380000h–38FFFFh 390000h–39FFFFh 3A0000h–3AFFFFh 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh 3E0000h–3EFFFFh 3F0000h–3FFFFFh 600000h–60FFFFh 610000h–61FFFFh 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh 6E0000h–6EFFFFh 6F0000h–6FFFFFh 22 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 2 of 3) Bank Sector SA80 SA81 SA82 SA83 SA84 SA85 SA86 Bank 5 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank 8 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 Bank 9 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h–50FFFFh 510000h–51FFFFh 520000h–52FFFFh 530000h–53FFFFh 540000h–54FFFFh 550000h–55FFFFh 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh 5A0000h–5AFFFFh 5B0000h–5BFFFFh 5C0000h–5CFFFFh 5D0000h–5DFFFFh 5E0000h–5EFFFFh 5F0000h–5FFFFFh 800000h–80FFFFh 810000h–81FFFFh 820000h–82FFFFh 830000h–83FFFFh 840000h–84FFFFh 850000h–85FFFFh 860000h–86FFFFh 870000h–87FFFFh 880000h–88FFFFh 890000h–89FFFFh 8A0000h–8AFFFFh 8B0000h–8BFFFFh 8C0000h–8CFFFFh 8D0000h–8DFFFFh 8E0000h–8EFFFFh 8F0000h–8FFFFFh 900000h–90FFFFh 910000h–91FFFFh 920000h–92FFFFh 930000h–93FFFFh 940000h–94FFFFh 950000h–95FFFFh 960000h–96FFFFh 970000h–97FFFFh 980000h–98FFFFh 990000h–99FFFFh 9A0000h–9AFFFFh 9B0000h–9BFFFFh 9C0000h–9CFFFFh 9D0000h–9DFFFFh 9E0000h–9EFFFFh 9F0000h–9FFFFFh Bank 11 Bank 10 Bank 7 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 700000h–70FFFFh 710000h–71FFFFh 720000h–72FFFFh 730000h–73FFFFh 740000h–74FFFFh 750000h–75FFFFh 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh 7A0000h–7AFFFFh 7B0000h–7BFFFFh 7C0000h–7CFFFFh 7D0000h–7DFFFFh 7E0000h–7EFFFFh 7F0000h–7FFFFFh A00000h–A0FFFFh A10000h–A1FFFFh A20000h–A2FFFFh A30000h–A3FFFFh A40000h–A4FFFFh A50000h–A5FFFFh A60000h–A6FFFFh A70000h–A7FFFFh A80000h–A8FFFFh A90000h–A9FFFFh AA0000h–AAFFFFh AB0000h–ABFFFFh AC0000h–ACFFFFh AD0000h–ADFFFFh AE0000h–AEFFFFh AF0000h–AFFFFFh B00000h–B0FFFFh B10000h–B1FFFFh B20000h–B2FFFFh B30000h–B3FFFFh B40000h–B4FFFFh B50000h–B5FFFFh B60000h–B6FFFFh B70000h–B7FFFFh B80000h–B8FFFFh B90000h–B9FFFFh BA0000h–BAFFFFh BB0000h–BBFFFFh BC0000h–BCFFFFh BD0000h–BDFFFFh BE0000h–BEFFFFh BF0000h–BFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 23 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 3 of 3) Bank Sector SA192 SA193 SA194 SA195 SA196 SA197 SA198 Bank 12 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 Bank 13 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range C00000h–C0FFFFh C10000h–C1FFFFh C20000h–C2FFFFh C30000h–C3FFFFh C40000h–C4FFFFh C50000h–C5FFFFh C60000h–C6FFFFh C70000h–C7FFFFh C80000h–C8FFFFh C90000h–C9FFFFh CA0000h–CAFFFFh CB0000h–CBFFFFh CC0000h–CCFFFFh CD0000h–CDFFFFh CE0000h–CEFFFFh CF0000h–CFFFFFh D00000h–D0FFFFh D10000h–D1FFFFh D20000h–D2FFFFh D30000h–D3FFFFh D40000h–D4FFFFh D50000h–D5FFFFh D60000h–D6FFFFh D70000h–D7FFFFh Bank 15 D80000h–D8FFFFh D90000h–D9FFFFh DA0000h–DAFFFFh DB0000h–DBFFFFh DC0000h–DCFFFFh DD0000h–DDFFFFh DE0000h–DEFFFFh DF0000h–DFFFFFh Bank 14 Bank Sector SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range E00000h–E0FFFFh E10000h–E1FFFFh E20000h–E2FFFFh E30000h–E3FFFFh E40000h–E4FFFFh E50000h–E5FFFFh E60000h–E6FFFFh E70000h–E7FFFFh E80000h–E8FFFFh E90000h–E9FFFFh EA0000h–EAFFFFh EB0000h–EBFFFFh EC0000h–ECFFFFh ED0000h–EDFFFFh EE0000h–EEFFFFh EF0000h–EFFFFFh F00000h–F0FFFFh F10000h–F1FFFFh F20000h–F2FFFFh F30000h–F3FFFFh F40000h–F4FFFFh F50000h–F5FFFFh F60000h–F6FFFFh F70000h–F7FFFFh F80000h–F8FFFFh F90000h–F9FFFFh FA0000h–FAFFFFh FB0000h–FBFFFFh FC0000h–FCFFFFh FD0000h–FDFFFFh FE0000h–FEFFFFh FF0000h–FF3FFFh FF4000h–FF7FFFh FF8000h–FFBFFFh FFC000h–FFFFFFh 24 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 1 of 2) Bank Sector SA0 SA1 SA2 Bank 0 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank 2 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 Bank 3 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 Bank 8 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 Bank 9 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h–00FFFFh 010000h–01FFFFh 020000h–02FFFFh 030000h–03FFFFh 040000h–04FFFFh 050000h–05FFFFh 060000h–06FFFFh 070000h–07FFFFh 080000h–08FFFFh 090000h–09FFFFh 0A0000h–0AFFFFh 0B0000h–0BFFFFh 0C0000h–0CFFFFh 0D0000h–0DFFFFh 0E0000h–0EFFFFh 0F0000h–0FFFFFh 100000h–10FFFFh 110000h–11FFFFh 120000h–12FFFFh 130000h–13FFFFh 140000h–14FFFFh 150000h–15FFFFh 160000h–16FFFFh 170000h–17FFFFh 180000h–18FFFFh 190000h–19FFFFh 1A0000h–1AFFFFh 1B0000h–1BFFFFh 1C0000h–1CFFFFh 1D0000h–1DFFFFh 1E0000h–1EFFFFh 1F0000h–1FFFFFh 400000h–40FFFFh 410000h–41FFFFh 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh 4E0000h–4EFFFFh 4F0000h–4FFFFFh Bank 13 Bank 12 Bank 7 Bank 6 Bank 5 Bank 4 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h–20FFFFh 210000h–21FFFFh 220000h–22FFFFh 230000h–23FFFFh 240000h–24FFFFh 250000h–25FFFFh 260000h–26FFFFh 270000h–27FFFFh 280000h–28FFFFh 290000h–29FFFFh 2A0000h–2AFFFFh 2B0000h–2BFFFFh 2C0000h–2CFFFFh 2D0000h–2DFFFFh 2E0000h–2EFFFFh 2F0000h–2FFFFFh 300000h–30FFFFh 310000h–31FFFFh 320000h–32FFFFh 330000h–33FFFFh 340000h–34FFFFh 350000h–35FFFFh 360000h–36FFFFh 370000h–37FFFFh 380000h–38FFFFh 390000h–39FFFFh 3A0000h–3AFFFFh 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh 3E0000h–3EFFFFh 3F0000h–3FFFFFh 600000h–60FFFFh 610000h–61FFFFh 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh 6E0000h–6EFFFFh 6F0000h–6FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 25 Data Sheet (Advance Information) Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 2 of 2) Bank Sector SA80 SA81 SA82 Bank 10 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 Bank 11 SA91 SA92 SA93 SA94 SA95 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h–50FFFFh 510000h–51FFFFh 520000h–52FFFFh 530000h–53FFFFh 540000h–54FFFFh 550000h–55FFFFh 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh 5A0000h–5AFFFFh 5B0000h–5BFFFFh Bank 15 5C0000h–5CFFFFh 5D0000h–5DFFFFh 5E0000h–5EFFFFh 5F0000h–5FFFFFh Bank 14 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range 700000h–70FFFFh 710000h–71FFFFh 720000h–72FFFFh 730000h–73FFFFh 740000h–74FFFFh 750000h–75FFFFh 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh 7A0000h–7AFFFFh 7B0000h–7BFFFFh 7C0000h–7CFFFFh 7D0000h–7DFFFFh 7E0000h–7EFFFFh 7F0000h–7F3FFFh 7F4000h–7F7FFFh 7F8000h–7FBFFFh 7FC000h–7FFFFFh 26 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 6. Device Operations This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Tables 11.1 and 11.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 6.1 Device Operation Table The device must be setup appropriately for each operation. Table 6.1 describes the required state of each control pin for any particular operation. Table 6.1 Device Operations Operation Asynchronous Read – Addresses Latched Asynchronous Write Standby (CE#) Hardware Reset Burst Read Operations Latch Starting Burst Address by CLK L H H L Addr In Addr In X H CE# OE# WE# CLK AVD# Amax– A16 Addr In A/DQ15– A/DQ0 I/O RDY RESET# L L H X H H L H X H X X X X X X X X X Addr In X X I/O HIGH Z HIGH Z H HIGH Z HIGH Z H H Advance Burst read to next address Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L H X L X X H H H X X H X X X X X I/O HIGH Z HIGH Z H HIGH Z HIGH Z H H L L X H Addr In Addr In X H Legend L = Logic 0, H = Logic 1, X = can be either VIL or VIH., Notes 1. Address is latched on the rising edge of clock. = rising edge, = high to low, = toggle. 2. CLK must stay low or high after CE# goes low when device in Asynchronous Read mode. 6.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. To read data from the memory array, the system must first assert a valid address while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. The data is output on A/DQ15 – A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 27 Data Sheet (Advance Information) 6.3 Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for Asynchronous read and can be automatically enabled for burst mode and the address is latched on the first rising edge of CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal transitions with valid data. The system would then write the configuration register command sequence. At startup the system writes the Set Configuration Register command sequence to optimize the system performance. The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge of the clock. RDY indicates the initial latency. Note that the device has a fixed internal address boundary that occurs every 128 words. No boundary crossing latency is required when the device operates with wait states set from 2 to 9. 6.3.1 Latency Tables for Variable Wait State Tables 6.2 – 6.9 show the latency for variable wait state in a normal Burst operation. Table 6.2 Address Latency for 9 Wait States Word 0 1 2 3 9 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 Table 6.3 Address Latency for 8 Wait States Word 0 1 2 3 8 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 28 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 6.4 Address Latency for 7 Wait States Word 0 1 2 3 7 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 Table 6.5 Address Latency for 6 Wait States Word 0 1 2 3 6 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.6 Address Latency for 5 Wait States Word 0 1 2 3 5 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.7 Address Latency for 4 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 D13 D13 D13 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 29 Data Sheet (Advance Information) Table 6.8 Address Latency for 3 Wait States Word 0 1 2 3 3 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 D9 D10 D11 D11 D10 D11 D12 D12 D11 D12 D13 D13 D12 D13 D14 D14 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.9 Address Latency for 2 Wait States Word 0 1 2 3 2 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 D9 D10 D11 D12 D10 D11 D12 D13 D11 D12 D13 D14 D12 D13 D14 D15 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 30 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 6.1 Synchronous Read Flow Chart Note: Setup Configuration Register parameters Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Set Configuration Registers Command and Settings: Address 555h, Data D0h Address X00h, Data CR0-CR1 Command Cycle CR = Configuration Registers Load Initial Address Address = RA RA = Read Address Wait tIACC + Programmable Wait State Setting CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles Read Initial Data RD = DQ[15:0] RD = Read Data Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing Refer to the Latency tables. Read Next Data RD = DQ[15:0] Delay X Clocks Crossing Boundary? No Yes End of Data? Yes Completed 6.3.2 Continuous Burst Read Mode In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary within the same bank, but not into a program or erase suspended sector, as mentioned above, additional latency cycles are required as reflected by the configuration register table (Table 6.11) and Tables 6.2 – 6.9 . If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 31 Data Sheet (Advance Information) 6.3.3 8-Word, 16-Word, and 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 6.10). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 38-3Fh, and the burst sequence is 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. Table 6.10 Burst Address Groups Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Group Address Ranges 0 – 7h, 8 – Fh, 10 – 17h,... 0 – Fh, 10 – 1Fh, 20 – 2Fh,... 00 – 1Fh, 20 – 3Fh, 40 – 5Fh,... 6.3.4 8-Word, 16-Word, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 3C-43h, and the burst sequence is 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which incurs the additional boundary crossing wait state. 6.3.5 Configuration Registers This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the device is capable of the asynchronous read mode and synchronous read, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 11.1). The following list describes the register settings. Table 6.11 Configuration Register CR Bit CR0.15 CR0.14 Function Reserved (Not used) Reserved (Not used) 0 = Reserved (Default) 1 = Reserved 0 = Reserved (Default) 1 = Reserved Settings (Binary) 32 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 6.11 Configuration Register CR Bit CR1.0 0001 0010 CR0.13 0011 0100 CR0.12 0101 Programmable Wait State (Note 1) 0110 = 0111 1000 = 1001 … CR0.11 initial data is valid on the 8th 9th rising CLK edge AVD# transition to VIH Reserved 7th = initial data is valid on the 3rd 4th 5th 6th rising CLK edge AVD# transition to VIH Function 0000 Settings (Binary) 2nd 1101 1110 = = initial data is valid on the 13th rising CLK edge Reserved AVD# transition to VIH (Default) 1111 CR0.10 CR0.9 CR0.8 CR0.7 CR0.6 CR0.5 CR1.4 CR0.4 CR0.3 RDY Polarity Reserved (Not used) RDY Reserved (Not used) Reserved (Not used) Reserved (Not used) Output Drive Strength RDY Function Burst Wrap Around 0 = RDY signal is active low 1 = RDY signal is active high (Default) 0 = Reserved 1 = Reserved (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved (Default) 1 = Reserved 0 = Full Drive= Current Driver Strength (Default) 1 = Half Drive 0 = RDY (Default) 1 = Reserved 0 = No Wrap Around Burst 1 = Wrap Around Burst (Default) 000 = Continuous (Default) CR0.2 010 = 8-Word Linear Burst CR0.1 CR0.0 Burst Length 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes 1. The addresses are latched by rising edge of CLK. 2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default). 3. A software reset command is required after read command. 4. CR0.3 is ignored if in continuous read mode (no wrap around). 6.4 Autoselect The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in the system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 6.12). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle select the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 33 Data Sheet (Advance Information) To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). See Table 11.1 for command sequence details. Table 6.12 Autoselect Addresses Description Manufacturer ID Byte 00 Device ID, Byte 01 Sector Lock/Unlock Byte 02 Address (BA) + 00h 0001h 307Eh(NS512P) 317Eh(NS256P) 327Eh(NS128P) 0001h = Locked, 0000h = Unlocked DQ15 – DQ8 = reserved DQ7 – Factory Lock Bit; 1 = Locked, 0 = Not Locked DQ6 – Customer Lock Bit; 1 = Locked, 0 = Not Locked Indicator Bits Byte 07 (BA) + 07h DQ5 – Handshake Bit; 1 = Reserved, 0 = Standard Handshake DQ4 and DQ3 – WP# Protection Boot Code; 01 = WP# Protects Top Boot Sectors, DQ2 – DQ0 = reserved Device ID, Byte 0E Device ID, Byte 0F (BA) + 0Eh 303Fh (NS512P) 3141h (NS256P) 3243h (NS128P) 3000h (NS512P) 3100h (NS256P) 3200h (NS128P) Read Data (BA) + 01h (SA) + 02h (BA) + 0Fh Software Functions and Sample Code Table 6.13 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Byte Address BA+AAAh BA+555h BA+AAAh Word Address BA+555h BA+2AAh BA+555h Data 0x00AAh 0x0055h 0x0090h Table 6.14 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Cycle Unlock Cycle 1 Notes 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. Operation Write Byte Address base + xxxxh Word Address base + xxxxh Data 0x00F0h The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. 34 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ 6.5 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices can be setup appropriately as outlined in the configuration register (Table 6.11). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. All addresses are latched on the rising edge of AVD# or falling edge of WE#, and all data is latched on the first rising edge of WE#. Note the following: When the Embedded Program/Erase algorithm is complete, the device returns to the read mode. The system can determine the status of the Program/Erase operation. Refer to the Write Operation Status section for further information. While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt is ignored as only an erase operation can covert a 0 to a 1. Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/Erase Suspend command. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset or power removal immediately terminates the Program/Erase operation and the Program/ Erase command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Write Buffer Programming when using the write buffer. Note: The system may also lock or unlock any sector while the erase operation is suspended. 6.5.1 Single Word Programming Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 11.1 for the required bus cycles and Figure 6.2 for the flowchart. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 35 Data Sheet (Advance Information) When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Figure 6.2 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Data to Address: PA, PD Program Address (PA), Program Data (PD) Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Busy? No Yes Polling Status = Complete? No Yes Error condition (Exceeded Timing Limits) Operation successfully completed Operation failed Software Functions and Sample Code Table 6.15 Single Word Program (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. 36 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */ 6.5.2 Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Note: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order. The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address must be the least significant address and must be incremental and that the write buffer data cannot be in different sectors. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/data pairs do not match the word count, the program buffer to flash command is ignored. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED in the following ways: Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this condition). Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 37 Data Sheet (Advance Information) Software Functions and Sample Code Table 6.16 Write Buffer Program (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N–1)h Program Address Program Address Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* A write buffer begins at addresses evenly divisible */ /* by 0x20. UINT16 i; */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i n=14) Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns (for example, 10 µs => n=14) Erase Suspend Time-out Maximum 2N μs Program Suspend Time-out Maximum 2N μs Bank Organization: X = Number of banks Bank 0 Region Information. X = Number of sectors in bank Description 45h 0014h 46h 47h 48h 49h 0002h 0001h 0000h 0008h 0078h (NS128P) 00F0h (NS256P) 01E0h (NS512P) 0001h 0000h 0085h 0095h 0003h (NS128P) 0003h (NS256P) 0005h (NS512P) 0001h 0001h 0008h 0014h 0014h 0005h 0005h 0010h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 83 Data Sheet (Advance Information) Table 11.6 Primary Vendor-Specific Extended Query (Sheet 2 of 2) Addresses 59h Data 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 000Bh (NS128P) 0013h (NS256P) 0020h (NS512P) Description Bank 1 Region Information. X = Number of sectors in bank 5Ah Bank 2 Region Information. X = Number of sectors in bank 5Bh Bank 3 Region Information. X = Number of sectors in bank 5Ch Bank 4 Region Information. X = Number of sectors in bank 5Dh Bank 5 Region Information. X = Number of sectors in bank 5Eh Bank 6 Region Information. X = Number of sectors in bank 5Fh Bank 7 Region Information. X = Number of sectors in bank 60h Bank 8 Region Information. X = Number of sectors in bank 61h Bank 9 Region Information. X = Number of sectors in bank 62h Bank 10 Region Information. X = Number of sectors in bank 63h Bank 11 Region Information. X = Number of sectors in bank 64h Bank 12 Region Information. X = Number of sectors in bank 65h Bank 13 Region Information. X = Number of sectors in bank 66h Bank 14 Region Information. X = Number of sectors in bank 67h Bank 15 Region Information. X = Number of sectors in bank 84 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 12. Revision History Section Revision A (June 29, 2006) Initial release Revision A1 (February 20, 2007) The tAVDS specification is changed from 4 ns to 5 ns The wait state for 83 MHz is changed to 8 ICC3(Max) is changed to 70 µA and ICC6(Max) is changed to 40 µA VIL (Min) is changed to -0.2 V tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies tCEZ (Max) is changed to 10 ns across all frequencies Global tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz) tRDY(Max) is changed to 10 ns tRACC(Max) is changed to 7.6 ns for 108 MHz tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz Erase and Programing Performance table is updated tCE in Asynchronous mode is changed to 83ns Description February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 85 Data Sheet (Advance Information) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2005-2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 86 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007

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