S29WS256N0PBFW110

S29WSxxxN MirrorBit™ Flash Family S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet PRELIMINARY General Description The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. They operate up to 80 MHz and use a single VCC of 1.7–1.95 volts that makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption. Distinctive Characteristics Single 1.8 V read/program/erase (1.70–1.95 V) 110 nm MirrorBit™ Technology Simultaneous Read/Write operation with zero latency 32-word Write Buffer Sixteen-bank architecture consisting of 16/8/4 Mbit for WS256N/128N/064N, respectively Four 16 Kword sectors at both top and bottom of memory array 254/126/62 64 Kword sectors (WS256N/128N/ 064N) Programmable burst read modes — Linear for 32, 16 or 8 words linear read with or without wrap-around — Continuous sequential read mode SecSi™ (Secured Silicon) Sector region consisting of 128 words each for factory and customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) RDY output indicates data available to system Command set compatible with JEDEC standards Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Offered Packages — WS064N: 80-ball FBGA (7 mm x 9 mm) — WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI) Industrial Temperature range (contact factory) Performance Characteristics Read Access Times Speed Option (MHz) Max. Synch. Latency, ns (tIACC) Max. Synch. Burst Access, ns (tBACC) Max. Asynch. Access Time, ns (tACC) Max CE# Access Time, ns (tCE) Max OE# Access Time, ns (tOE) 80 69 9 70 70 11.2 66 69 11.2 70 70 11.2 54 69 13.5 70 70 13.5 Current Consumption (typical values) Continuous Burst Read @ 66 MHz Simultaneous Operation (asynchronous) Program (asynchronous) Erase (asynchronous) Standby Mode (asynchronous) 35 mA 50 mA 19 mA 19 mA 20 µA Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 40 µs 9.4 µs 6 µs 150 ms 600 ms Publication Number S29WSxxxN_00 Revision F Amendment 0 Issue Date October 29, 2004 Preliminary Table of Contents 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . .5 2. Input/Output Descriptions & Logic Symbol . . . .6 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. Physical Dimensions/Connection Diagrams . . . .8 4.1 Related Documents ........................................................................ 8 4.2 Special Handling Instructions for FBGA Package ................. 8 4.3 MCP Look-ahead Connection Diagram ................................. 13 5. Additional Resources . . . . . . . . . . . . . . . . . . . . . 15 6. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Memory Map .................................................................................... 16 7. Device Operations . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 Device Operation Table ............................................................... 19 7.2 Asynchronous Read ...................................................................... 19 7.3 Synchronous (Burst) Read Mode & Configuration Register ........................................................................20 7.3.1 Continuous Burst Read Mode .......................................... 24 7.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around ....................................................................... 25 7.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around ................................................................ 25 7.3.4 Configuration Register ....................................................... 25 7.4 Autoselect ....................................................................................... 26 7.5 Program/Erase Operations ........................................................ 29 7.5.1. Single Word Programming ................................................ 29 7.5.2 Write Buffer Programming ................................................ 31 7.5.3 Sector Erase ........................................................................... 34 7.5.4 Chip Erase Command Sequence ..................................... 38 7.5.5 Erase Suspend/Erase Resume Commands ................... 38 7.5.6 Program Suspend/Program Resume Commands ....... 39 7.5.7 Accelerated Program/Chip Erase ...................................40 7.5.8 Unlock Bypass ........................................................................ 41 7.5.9 Write Operation Status ..................................................... 42 7.6 Simultaneous Read/Write ..........................................................48 7.7 Writing Commands/Command Sequences ..........................48 7.8 Handshaking ...................................................................................48 7.9 Hardware Reset ............................................................................ 49 7.10 Software Reset ............................................................................. 49 8. Advanced Sector Protection/Unprotection . . . 51 8.1 Lock Register .................................................................................. 52 8.2 Persistent Protection Bits .......................................................... 52 8.3 Dynamic Protection Bits .............................................................53 8.4 Persistent Protection Bit Lock Bit ...........................................53 8.5 Password Protection Method ...................................................54 8.6 Advanced Sector Protection Software Examples ...............56 8.7 Hardware Data Protection Methods ......................................56 8.7.1. WP# Method .........................................................................56 8.7.2 ACC Method .........................................................................56 8.7.3 Low VCC Write Inhibit .......................................................57 8.7.4 Write Pulse “Glitch Protection” .....................................57 8.7.5 Power-Up Write Inhibit .....................................................57 9. Power Conservation Modes . . . . . . . . . . . . . . . 58 9.1 Standby Mode ................................................................................. 58 9.2 Automatic Sleep Mode ............................................................... 58 9.3 Hardware RESET# Input Operation ...................................... 58 9.4 Output Disable (OE#) ................................................................ 58 10. SecSiTM (Secured Silicon) Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.1 Factory SecSiTM Sector .................................................................59 10.2 Customer SecSiTM Sector .......................................................... 60 10.3 SecSiTM Sector Entry and SecSi Sector Exit Command Sequences .......................................................................... 60 11. Electrical Specifications . . . . . . . . . . . . . . . . . . 62 11.1 Absolute Maximum Ratings ....................................................... 62 11.2 Operating Ranges ..........................................................................63 11.3 Test Conditions .............................................................................63 11.4 Key to Switching Waveforms ................................................. 64 11.5 Switching Waveforms ................................................................. 64 11.6 VCC Power-up .............................................................................. 64 11.7 DC Characteristics (CMOS Compatible) .............................65 11.8 AC Characteristics ...................................................................... 66 11.8.1. CLK Characterization ....................................................... 66 11.8.2 Synchronous/Burst Read ...................................................67 11.8.3 Timing Diagrams ................................................................. 68 11.8.4 AC Characteristics—Asynchronous Read ................. 70 11.8.5 Hardware Reset (RESET#) ..............................................72 11.8.6 Erase/Program Timing ........................................................73 11.8.7 Erase and Programming Performance ...........................83 11.8.8 BGA Ball Capacitance ....................................................... 84 12. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 Common Flash Memory Interface ..........................................88 13. Commonly Used Terms . . . . . . . . . . . . . . . . . . 92 14. Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00F0 October 29, 2004 Preliminary List of Figures Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .......................................................... 10 Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N) .................................................................................................................... 11 Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package ............................................................... 12 Figure 4.5. MCP Look-ahead Diagram ................................................................................................................................................... 14 Figure 7.2. Synchronous Read ............................................................................................................................................................. 24 Figure 7.19. Single Word Program....................................................................................................................................................... 30 Figure 7.22. Write Buffer Programming Operation ................................................................................................................................. 34 Figure 7.24. Sector Erase Operation.................................................................................................................................................... 37 Figure 7.33. Write Operation Status Flowchart ...................................................................................................................................... 44 Figure 8.2. Lock Register Program Algorithm ......................................................................................................................................... 55 Figure 11.2. Maximum Positive Overshoot Waveform.............................................................................................................................. 62 Figure 11.3. Test Setup ...................................................................................................................................................................... 63 Figure 11.4. Input Waveforms and Measurement Levels.......................................................................................................................... 64 Figure 11.5. VCC Power-up Diagram ..................................................................................................................................................... 64 Figure 11.6. CLK Characterization ........................................................................................................................................................ 66 Figure 11.7. CLK Synchronous Burst Mode Read .................................................................................................................................... 68 Figure 11.8. 8-word Linear Burst with Wrap Around ............................................................................................................................... 69 Figure 11.9. 8-word Linear Burst without Wrap Around ........................................................................................................................... 69 Figure 11.10. Linear Burst with RDY Set One Cycle Before Data ............................................................................................................... 70 Figure 11.11. Asynchronous Mode Read................................................................................................................................................ 71 Figure 11.12. Reset Timings................................................................................................................................................................ 72 Figure 11.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses ............................................................................................. 74 Figure 11.13. Asynchronous Program Operation Timings: WE# Latched Addresses ..................................................................................... 75 Figure 11.14. Synchronous Program Operation Timings: CLK Latched Addresses ........................................................................................ 76 Figure 11.15. Accelerated Unlock Bypass Programming Timing ................................................................................................................ 77 Figure 11.16. Data# Polling Timings (During Embedded Algorithm) .......................................................................................................... 77 Figure 11.17. Toggle Bit Timings (During Embedded Algorithm) ............................................................................................................... 78 Figure 11.18. Synchronous Data Polling Timings/Toggle Bit Timings ......................................................................................................... 78 Figure 11.19. DQ2 vs. DQ6 ................................................................................................................................................................. 79 Figure 11.20. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................................. 79 Figure 11.21. Latency with Boundary Crossing into Program/Erase Bank ................................................................................................... 80 Figure 11.22. Example of Wait States Insertion ..................................................................................................................................... 81 Figure 11.23. Back-to-Back Read/Write Cycle Timings ............................................................................................................................ 82 October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 3 Preliminary List of Tables Read Access Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Current Consumption (typical values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Typical Program & Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2.1. Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 6.1. S29WS256N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6.2. S29WS128N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6.3. S29WS064N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7.4. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7.5. Address Latency for x Wait States (≤ 80 MHz, WS256N only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 7.6. Address Latency for 6 Wait States (≤ 80 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 7.7. Address Latency for 5 Wait States (≤ 68 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 7.8. Address Latency for 4 Wait States (≤ 54 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 7.9. Address Latency for 3 Wait States (≤ 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 7.10. Address/Boundary Crossing Latency for 6 Wait States (≤ 80 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7.11. Address/Boundary Crossing Latency for 5 Wait States (≤ 68 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7.12. Address/Boundary Crossing Latency for 4 Wait States (≤ 54 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7.13. Address/Boundary Crossing Latency for 3 Wait States (≤ 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7.14. Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7.15. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.16. Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7.17. Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7.18. Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 7.20. Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7.21. Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7.23. Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7.25. Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7.26. Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 7.27. Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 7.28. Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 7.29. Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 7.30. Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 7.31. Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 7.32. Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 7.34. DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7.35. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 7.36. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 8.1. Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 8.2. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 10.1. SecSiTM Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10.2. SecSi Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 10.3. SecSi Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 10.4. SecSi Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 11.1. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 12.1. Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 12.2. Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table 12.3. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 12.4. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 12.5. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 12.6. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 1 Ordering Information The ordering part number is formed by a valid combination of the following: 256 N 0S BA W 01 0 PACKING TYPE 0 = Tray (standard; see note 1) 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER (Note 3) (Package Ball Count, Package Dimensions, DYB Protect/Unprotect After Power-up) 01 = 84-ball, 8 x 11.6 mm, DYB Unprotect 11 = 80-ball, 7 x 9 mm, DYB Protect TEMPERATURE RANGE (Note 3) W = Wireless (–25°C to +85°C) I = Industrial (–40°C to +85°C, contact factory for availability) PACKAGE TYPE AND MATERIAL BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package SPEED OPTION (BURST FREQUENCY) 0S = 80 MHz 0P = 66 MHz 0L = 54 MHz PROCESS TECHNOLOGY N = 110 nm MirrorBit™ Technology FLASH DENSITY 256 = 256 Mb 128 = 128 Mb 064 = 64 Mb DEVICE FAMILY S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory S29WS S29WSxxxN Valid Combinations (Notes 1, 2, 3) Base Ordering Part Number S29WS256N BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) Speed Option Package Type, Material, & Temperature Range Model Number 01 11 0S, 0P, 0L 01 11 01 11 0, 2, 3 (Note 1) 1.70–1.95 V Packing Type VIO Range DYB Power Up State Unprotect Protect Unprotect Protect Unprotect Protect Package Type (Note 2) S29WS128N 8 mm x 11.6 mm 84-ball MCP-Compatible 7 mm x 9 mm 80-ball MCP-Compatible S29WS064N Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S29” and packing type designator from ordering part number. 3. For 1.5 VIO option, other boot options, or industrial temperature range, contact your local sales office. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 5 Preliminary 2 Input/Output Descriptions & Logic Symbol Table identifies the input and output package connections provided on the device. Table 2.1. Symbol A23–A0 DQ15–DQ0 CE# OE# WE# VCC VIO VSS NC RDY CLK Input/Output Descriptions Description Type Input I/O Input Input Input Supply Input I/O No Connect Output Input Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N). Data input/output. Chip Enable. Asynchronous relative to CLK. Output Enable. Asynchronous relative to CLK. Write Enable. Device Power Supply. VersatileIO Input. Should be tied to VCC. Ground. Not connected internally. Ready. Indicates when valid burst data is ready to be read. Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid. Indicates to device that the valid address is present on the address inputs. When low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. When high, device ignores address inputs. AVD# Input RESET# WP# Input Input Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use (see MCP look-ahead pinout for use with MCP). ACC RFU Input Reserved 6 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 3 Block Diagram VCC VSS VIO DQ15–DQ0 RDY Buffer RDY Erase Voltage Generator Input/Output Buffers WE# RESET# WP# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder VCC Detector Y-Gating Address Latch Timer X-Decoder Cell Matrix AVD# CLK Burst State Control Burst Address Counter Amax–A0* * WS256N: A23-A0 WS128N: A22-A0 WS064N: A21-A0 Figure 3.1. S29WSxxxN Block Diagram October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 7 Preliminary 4 Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S29WSxxxN. 4.1 Related Documents The following documents contain information relating to the S29WSxxxN devices. Click on the title or go to www.amd.com/flash (click on Technical Documentation) or www.fujitsu.com to download the PDF file, or request a copy from your sales office. Migration to the S29WS256N Family Application Note Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 8 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 84-Ball Fine-Pitch Ball Grid Array, 256 & 128 Mb (Top View, Balls Facing Down, MCP Compatible) A1 NC B2 AVD# C2 WP# D2 A3 E2 Ball F6 is RFU on 128 Mb device. A10 B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 RFU D4 RFU E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU B5 RFU C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCC K5 DQ11 L5 VCC B6 RFU C6 WE# D6 RFU E6 A20 F6 A23 G6 RFU H6 DQ4 J6 RFU K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU M10 NC NC A2 F2 A1 G2 A0 H2 CE#f1 J2 RFU K2 RFU L2 RFU M1 NC Figure 4.1. 84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N) October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 9 Preliminary VBH084—84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm 0.05 C (2X) D A D1 e 10 9 e 8 7 6 7 SE E1 E 5 4 3 2 1 M L K J H G F E D C B A A1 CORNER A1 CORNER INDEX MARK B 10 0.05 C (2X) 6 SD φ 0.08 M C φ 0.15 M C A B 7 NXφb TOP VIEW BOTTOM VIEW A A1 SEATING PLANE A2 0.10 C C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC VBH 084 N/A 11.60 mm x 8.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.33 MIN --0.18 0.62 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 --0.80 BSC. 0.40 BSC. (A2-A9, B10-L10, M2-M9, B1-L1) 0.43 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3339 \ 16-038.25b Note: BSC is an ANSI standard for Basic Space Centering Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package 10 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 80-ball Fine-Pitch Ball Grid Array, 64 Mb (Top View, Balls Facing Down, MCP Compatible) A1 AVD# B1 WP# C1 A3 D1 A2 E1 A1 F1 A0 G1 CE#f1 H1 RFU J1 RFU K1 RFU A2 RFU B2 A7 C2 A6 D2 A5 E2 A4 F2 VSS G2 OE# H2 DQ0 J2 DQ8 K2 RFU A3 CLK B3 RFU C3 RFU D3 A18 E3 A17 F3 DQ1 G3 DQ9 H3 DQ10 J3 DQ2 K3 RFU A4 RFU B4 ACC C4 RESET# D4 RDY E4 RFU F4 RFU G4 DQ3 H4 VCC J4 DQ11 K4 VCC A5 RFU B5 WE# C5 RFU D5 A20 E5 RFU F5 RFU G5 DQ4 H5 RFU J5 RFU K5 RFU A6 RFU B6 A8 C6 A19 D6 A9 E6 A10 F6 DQ6 G6 DQ13 H6 DQ12 J6 DQ5 K6 RFU A7 RFU B7 A11 C7 A12 D7 A13 E7 A14 F7 RFU G7 DQ15 H7 DQ7 J7 DQ14 K7 RFU A8 RFU B8 RFU C8 A15 D8 A21 E8 RFU F8 A16 G8 RFU H8 VSS J8 RFU K8 RFU Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N) October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 11 Preliminary TLC080—80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm D 0.15 C (2X) A D1 eD 8 7 6 SE 7 E1 E eE 5 4 3 2 1 PIN A1 CORNER INDEX MARK 10 K J H G F E D C B A B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 6 0.20 C C 0.08 C SIDE VIEW M CAB MC 80X 0.15 0.08 b NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TLC 080 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.17 0.81 NOM ------9.00 BSC. 7.00 BSC. 7.20 BSC. 5.60 BSC. 10 8 80 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3430 \ 16-038.22 \ 10.15.04 Note: BSC is an ANSI standard for Basic Space Centering Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package 12 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 4.3 MCP Look-ahead Connection Diagram Figure 4.5 shows a migration path from the S29WSxxxN to higher densities and the option to include additional die within a single package. Spansion LLC provides this standard lookahead connection diagram that supports NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits NOR Flash and pSRAM and data storage densities up to 4 Gigabits The following multi-chip package (MCP) data sheet(s) are based on the S29WSxxxN. Refer to these documents for input/output descriptions for each product: Publication Number S71WS256_512NC0. The physical package outline may vary between connection diagrams and densities. The connection diagram for any MCP, however, will be a subset of the pinout in Figure 4.5. In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls are reserved; do not connect them to any other signal. For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless Solutions with Spansion Products application note, available on the web or through an AMD or Fujitsu sales office. October 29, 2004 S29WSxxxN_00_F0 S29WSxxxN MirrorBit™ Flash Family 13 Preliminary Legend: A1 NC B1 NC A2 NC B2 NC C2 AVD# D2 WP# E2 A3 F2 A2 G2 A1 H2 A0 J2 CE#f1 K2 CE1#s1 L2 VCCnds M2 A27 N1 NC P1 NC N2 NC P2 NC C3 VSSds D3 A7 E3 A6 F3 A5 G3 A4 H3 VSS J3 OE# K3 DQ0 L4 DQ8 M3 A26 C4 CLK D4 LB#s E4 UB#s F4 A18 G4 A17 H4 DQ1 J4 DQ9 K4 DQ10 L4 DQ2 M4 VSSnds C5 CE#f2 D5 WP/ACC E5 RESET#f F5 RDY G5 CE1#s2 H5 VCCs2 J5 DQ3 K5 VCCf L5 DQ11 M5 VCCf C6 C7 C8 96-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A9 NC B9 NC C9 A10 NC B10 NC Data-storage Only Shared or NC (not connected) VCCds RESET#ds CLKds RY/BY#ds D6 WE# E6 CE2s1 F6 A20 G6 A23 H6 CE2s2 J6 DQ4 K6 VCCs1 L6 A25 M6 CE2#ds D7 A8 E7 A19 F7 A9 G7 A10 H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 VCCQs1 D8 A11 E8 A12 F8 A13 G8 A14 H8 A24 J8 DQ15 K8 DQ7 L8 D9 CE1#ds E9 A15 F9 A21 G9 A22 H9 A16 2nd RAM Only J2 CREs K9 VSS L9 RAM Shared Only 1st RAM Only 2nd Flash Only Flash Shared Only 1st Flash Only DoC Only DQ14 LOCK or WP#/ACCds M8 NC or VCCQds M9 DNU N9 NC P9 NC N10 NC P10 NC NC or ds Figure 4.5. MCP Look-ahead Diagram 14 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_00_F0 October 29, 2004 Preliminary 5 Additional Resources Visit www.amd.com and www.fujitsu.com to obtain the following related documents: Application Notes Using the Operation Status Bits in AMD Devices Understanding Burst Mode Flash Memory Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions Specification Bulletins Contact your local sales office for details. Drivers and Software Support Spansion low-level drivers Enhanced Flash drivers Flash file system CAD Modeling Support VHDL and Verilog IBIS ORCAD Technical Support Contact your local sales office or contact Spansion LLC directly for additional technical support: Email US and Canada: HW.support@amd.com Asia Pacific: asia.support@amd.com Europe, Middle East, and Africa Japan: http://edevice.fujitsu.com/jp/support/tech/#b7 Frequently Asked Questions (FAQ) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 Phone US: (408) 749-5703 Japan (03) 5322-3324 Spansion LLC Locations 915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com October 29, 2004 S29WSxxxN_00_F0 15 Preliminary 6 Product Overview The S29WSxxxN family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/ write burst mode Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/ erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of secured silicon (SecSi™) area for storing customer and factory secured information. The SecSi Sector is One Time Programmable and Protectable (OTTP). 6.1 Memory Map The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 6.1– 6.3. Table 6.1. Bank Size Sector Count Sector Size (KB) Bank S29WS256N Sector & Memory Address Map Sector/ Sector Range SA000 SA001 Address Range 000000h–003FFFh 004000h–007FFFh 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh to 0F0000h–0FFFFFh 100000h–10FFFFh to 1F0000h–1FFFFFh 200000h–20FFFFh to 2F0000h–2FFFFFh 300000h–30FFFFh to 3F0000h–3FFFFFh 400000h–40FFFFh to 4F0000h–4FFFFFh 500000h–50FFFFh to 5F0000h–5FFFFFh 600000h–60FFFFh to 6F0000h–6FFFFFh 700000h–70FFFFh to 7F0000h–7FFFFFh 800000h–80FFFFh to 8F0000h–8FFFFFh 900000h–90FFFFh to 9F0000h–9FFFFFh A00000h–A0FFFFh to AF0000h–AFFFFFh B00000h–B0FFFFh to BF0000h–BFFFFFh C00000h–C0FFFFh to CF0000h–CFFFFFh D00000h–D0FFFFh to DF0000h–DFFFFFh E00000h–E0FFFFh to EF0000h–EFFFFFh F00000h–F0FFFFh to FE0000h–FEFFFFh FF0000h–FF3FFFh FF4000h–FF7FFFh FF8000h–FFBFFFh FFC000h–FFFFFFh Notes 2 MB 4 32 0 SA002 SA003 Contains four smaller sectors at bottom of addressable memory. 15 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA004 to SA018 SA019 to SA034 SA035 to SA050 SA051 to SA066 SA067 to SA082 SA083 to SA098 SA099 to SA114 SA115 to SA130 SA131 to SA146 SA147 to SA162 SA163 to SA178 SA179 to SA194 SA195 to SA210 SA211 to SA226 SA227 to SA242 SA243 to SA257 SA258 All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) 2 MB 4 32 15 SA259 SA260 SA261 Contains four smaller sectors at top of addressable memory. Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. 16 S29WSxxxN_00_F0 October 29, 2004 Preliminary Table 6.2. Bank Size Sector Count Sector Size (KB) 32 4 32 32 32 7 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 32 1 MB 4 32 32 32 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 S29WS128N Sector & Memory Address Map Sector/ Sector Range SA000 SA001 SA002 SA003 SA004 to SA010 SA011 to SA018 SA019 to SA026 SA027 to SA034 SA035 to SA042 SA043 to SA050 SA051 to SA058 SA059 to SA066 SA067 to SA074 SA075 to SA082 SA083 to SA090 SA091 to SA098 SA099 to SA106 SA107 to SA114 SA115 to SA122 SA123 to SA129 SA130 SA131 SA132 SA133 Bank Address Range 000000h–003FFFh 004000h–007FFFh 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh to 070000h–07FFFFh 080000h–08FFFFh to 0F0000h–0FFFFFh 100000h–10FFFFh to 170000h–17FFFFh 180000h–18FFFFh to 1F0000h–1FFFFFh 200000h–20FFFFh to 270000h–27FFFFh 280000h–28FFFFh to 2F0000h–2FFFFFh 300000h–30FFFFh to 370000h–37FFFFh 380000h–38FFFFh to 3F0000h–3FFFFFh 400000h–40FFFFh to 470000h–47FFFFh 480000h–48FFFFh to 4F0000h–4FFFFFh 500000h–50FFFFh to 570000h–57FFFFh 580000h–58FFFFh to 5F0000h–5FFFFFh 600000h–60FFFFh to 670000h–67FFFFh 680000h–68FFFFh to 6F0000h–6FFFFFh 700000h–70FFFFh to 770000h–77FFFFh 780000h–78FFFFh to 7E0000h–7EFFFFh 7F0000h–7F3FFFh 7F4000h–7F7FFFh 7F8000h–7FBFFFh 7FC000h–7FFFFFh Notes 1 MB Contains four smaller sectors at bottom of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) Contains four smaller sectors at top of addressable memory. Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. October 29, 2004 S29WSxxxN_00_F0 17 Preliminary Table 6.3. Bank Size Sector Count Sector Size (KB) Bank S29WS064N Sector & Memory Address Map Sector/ Sector Range SA000 SA001 SA002 Address Range 000000h–003FFFh 004000h–007FFFh 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh 020000h–02FFFFh 030000h–03FFFFh 040000h–04FFFFh to 070000h–07FFFFh 080000h–08FFFFh to 0B0000h–0BFFFFh 0C0000h–0CFFFFh to 0F0000h–0FFFFFh 100000h–10FFFFh to 130000h–13FFFFh 140000h–14FFFFh to 170000h–17FFFFh 180000h–18FFFFh to 1B0000h–1BFFFFh 1C0000h–1CFFFFh to 1F0000h–1FFFFFh 200000h–20FFFFh to 230000h–23FFFFh 240000h–24FFFFh to 270000h–27FFFFh 280000h–28FFFFh to 2B0000h–2BFFFFh 2C0000h–2CFFFFh to 2F0000h–2FFFFFh 300000h–30FFFFh to 330000h–33FFFFh 340000h–34FFFFh to 370000h–37FFFFh 380000h–38FFFFh to 3B0000h–3BFFFFh 3C0000h–3CFFFFh 3D0000h–3DFFFFh 3E0000h–3EFFFFh 3F0000h–3F3FFFh 3F4000h–3F7FFFh 3F8000h–3FBFFFh 3FC000h–3FFFFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) Contains four smaller sectors at bottom of addressable memory. Notes 4 0.5 MB 3 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 0.5 MB 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 0.5 MB 4 32 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 15 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA003 SA004 SA005 SA006 SA007–SA010 SA011–SA014 SA015–SA018 SA019–SA022 SA023–SA026 SA027–SA030 SA031–SA034 SA035–SA038 SA039–SA042 SA043–SA046 SA047–SA050 SA051–SA054 SA055–SA058 SA059–SA062 SA063 SA064 SA065 SA066 SA067 SA068 SA069 Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. 18 S29WSxxxN_00_F0 October 29, 2004 Preliminary 7 Device Operations This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Tables 12.1 and 12.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 7.1 Device Operation Table The device must be setup appropriately for each operation. Table 7.4 describes the required state of each control pin for any particular operation. Table 7.4. Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations (Synchronous) Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L CE# L L L L H X Device Operations OE# L L H H X X WE# H H L L X X Addresses Addr In Addr In Addr In Addr In X X DQ15–0 Data Out Data Out I/O I/O HIGH Z HIGH Z RESET# H H H H H L X X X X CLK X X X L L AVD# X L X X X H H H H H Addr In X X X Addr In X Burst Data Out HIGH Z HIGH Z I/O H H H L H X H X X Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output. 7.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address and data will appear on DQ15–DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output data. The chip enable October 29, 2004 S29WSxxxN_00_F0 19 Preliminary access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. 7.3 Synchronous (Burst) Read Mode & Configuration Register When a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. The device offers both continuous and linear methods of burst read operation, which are discussed in subsections 7.3.1 and 7.3.2, and 7.3.3. Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (tIACC) of each burst access, the burst mode in which to operate, and when RDY will indicate data is ready to be read. Prior to entering the burst mode, the system should first determine the configuration register settings (and read the current register settings if desired via the Read Configuration Register command sequence), and then write the configuration register command sequence. See Section 7.3.4, Configuration Register, and Table 12.1, Memory Array Commands for further details. Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1) Synchronous Read Mode Only Figure 7.1. Synchronous/Asynchronous State Diagram The device outputs the initial word subject to the following operational conditions: tIACC specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. configuration register setting CR13–CR11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that tIACC is lengthened. 20 S29WSxxxN_00_F0 October 29, 2004 Preliminary The device outputs subsequent words tBACC after the active edge of each successive clock cycle, which also increments the internal address counter. The device outputs burst data at this rate subject to the following operational conditions: starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-by-four address incurs the least number of additional wait states that occur after the initial word. The number of additional wait states required increases for burst operations in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where A[1:0] is 01, 10, or 11). boundary crossing: a physical aspect of the device that exists every 128 words, starting at address 00007Fh. Higher operational speeds require one additional wait state. Refer to Tables 7.10–7.13 for details. Figure 11.20 shows the effects of boundary crossings at higher frequencies. clock frequency: the speed at which the device is expected to burst data. Higher speeds require additional wait states after the initial word for proper operation. Tables 7.7–7.13 show the effects of frequency on burst operation. In all cases, with or without latency, the RDY output indicates when the next data is available to be read. Table 7.5 shows the latency that occurs in the S29WS256N device when (x indicates the recommended number of wait states for various operating frequencies, as shown in Table 7.15, configuration register bits CR13-CR11). Tables 7.7–7.9 show the effects of various combinations of the starting address, operating frequency, and wait state setting (configuration register bits CR13–CR11) for the S29WS128N and S29WS064N devices. Tables 7.10–7.13 includes the wait state that occurs when crossing the internal boundary. Table 7.5. Word 0 1 2 3 Address Latency for x Wait States (≤ 80 MHz, WS256N only) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8 Wait States x ws x ws x ws x ws Table 7.6. Word 0 1 2 3 Wait States 6 ws 6 ws 6 ws 6 ws Address Latency for 6 Wait States (≤ 80 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8 Table 7.7. Word 0 1 2 3 Wait States 5 ws 5 ws 5 ws 5 ws Address Latency for 5 Wait States (≤ 68 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8 D9 D9 D9 October 29, 2004 S29WSxxxN_00_F0 21 Preliminary Address Latency for 4 Wait States (≤ 54 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 D5 D6 D7 D7 D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 Table 7.8. Word 0 1 2 3 Wait States 4 ws 4 ws 4 ws 4 ws Table 7.9. Word 0 1 2 3 Wait States 3 ws 3 ws 3 ws 3 ws Address Latency for 3 Wait States (≤ 40 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 7.10. Word 0 1 2 3 Address/Boundary Crossing Latency for 6 Wait States (≤ 80 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 6 ws 6 ws 6 ws 6 ws Wait States Table 7.11. Word 0 1 2 3 Address/Boundary Crossing Latency for 5 Wait States (≤ 68 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8 5 ws 5 ws 5 ws 5 ws Wait States Table 7.12. Word 0 1 2 3 Address/Boundary Crossing Latency for 4 Wait States (≤ 54 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8 D9 D9 D9 4 ws 4 ws 4 ws 4 ws Wait States Table 7.13. Word 0 1 2 3 Address/Boundary Crossing Latency for 3 Wait States (≤ 40 MHz) Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 D5 D6 D7 D7 D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 3 ws 3 ws 3 ws 3 ws Wait States 22 S29WSxxxN_00_F0 October 29, 2004 Preliminary Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR Command Cycle CR = Configuration Register Bits CR15-CR0 Load Initial Address Address = RA RA = Read Address Wait tIACC + Programmable Wait State Setting CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles Read Initial Data RD = DQ[15:0] RD = Read Data Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing See Tables 7.6–7.13 to determine total number of clocks required for X. Read Next Data RD = DQ[15:0] Delay X Clocks Crossing Boundary? No Yes End of Data? Yes Completed Figure 7.2. Synchronous Read 7.3.1 Continuous Burst Read Mode In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. The burst read mode will continue until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. If the address being read crosses a 128-word line boundary and the subsequent word line is not programming or erasing, additional latency cycles are required as shown in Tables 7.10– 7.13. If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device will provide read status information and the clock will be ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. October 29, 2004 S29WSxxxN_00_F0 23 Preliminary 7.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 7.14). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). Table 7.14. Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Burst Address Groups Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,... 7.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32word burst will execute up to the maximum memory address of the selected number of words. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. For example, if the starting address in the 8- word mode is 3Ch, the address range to be read would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read will require a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words. 7.3.4 Configuration Register The configuration register sets various operational features, most of which are associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register can also be read using a command sequence (see Table 12.1). The following list describes the register settings. 24 S29WSxxxN_00_F0 October 29, 2004 Preliminary Table 7.15. CR Bit CR15 Function Set Device Read Mode Settings (Binary) Configuration Register 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Read Mode (default) Enabled 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) Must be set to “1” at higher operating frequencies. See Tables 7.10–7.13. 000 = Data valid on 2nd active CLK edge after addresses latched 001 = Data valid on 3rd active CLK edge after addresses latched 010 = Data valid on 4th active CLK edge after addresses latched (recommended for 54 MHz) 011 = Data valid on 5th active CLK edge after addresses latched (recommended for 66 MHz) 100 = Data valid on 6th active CLK edge after addresses latched (recommended for 80 MHz) 101 = Data valid on 7th active CLK edge after addresses latched (default) 110 = Reserved 111 = Reserved Inserts wait states before initial data is available. Setting greater number of wait states before initial data reduces latency after initial data. See Tables 7.6–7.13. 0 = RDY signal active low 1 = RDY signal active high (default) 1 = default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) When CR13-CR11 are set to 000, RDY will be active with data regardless of CR8 setting. 1 = default 1 = default 0 = default 0 = default 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) CR14 Boundary Crossing CR13 CR12 CR11 Programmable Wait State CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 RDY Polarity Reserved RDY Reserved Reserved Reserved Reserved Burst Wrap Around CR2 CR1 CR0 Burst Length Note: Configuration Register will be in the default state upon power-up or hardware reset. Reading the Configuration Table. The configuration register can be read with a four-cycle command sequence. See Table 12.1 for sequence details. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. 7.4 Autoselect The Autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The Autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 7.17 to 7.16). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register. Note that if a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle of the Autoselect command, the host system can read Autoselect data from that bank and then immediately read array data from the other bank, without exiting the Autoselect mode. October 29, 2004 S29WSxxxN_00_F0 25 Preliminary To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspendread mode if the bank was previously in Erase Suspend). See Table 12.1 for command sequence details. Table 7.16. Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh Autoselect Addresses Read Data 0001h 227Eh 2230 (WS256N) 2231 (WS128N) 2232 (WS064N) 2200 DQ15 - DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake Indicator Bits (See Note) (BA) + 03h DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot Sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase disabled Sector Block Lock/ Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked Note: For WS128N and WS064, DQ1 and DQ0 will be reserved. Software Functions and Sample Code Table 7.17. Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Autoselect Entry Word Address BAx555h BAx2AAh BAx555h Data 0x00AAh 0x0055h 0x0090h (LLD Function = lld_AutoselectEntryCmd) Byte Address BAxAAAh BAx555h BAxAAAh 26 S29WSxxxN_00_F0 October 29, 2004 Preliminary Table 7.18. Cycle Unlock Cycle 1 Operation Write Autoselect Exit Word Address base + XXXh Data 0x00F0h (LLD Function = lld_AutoselectExitCmd) Byte Address base + XXXh Notes: 1. Any offset within the device will work. 2. BA = Bank Address. The bank address is required. 3. base = base address. The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ October 29, 2004 S29WSxxxN_00_F0 27 Preliminary 7.5 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in details during the following sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in Table 6.4. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. Note the following: When the Embedded Program algorithm is complete, the device then returns to the read mode. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. A “0” cannot be programmed back to a “1.” Attempting to do so will cause the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. SecSi Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries for single word programming operation. Programming to the same word address multiple times without intervening erases is limited. For such application requirements, please contact your local Spansion representative. 7.5.1. Single Word Programming Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8-, 16- or 32-bits wide. While this method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 12.1 for the required bus cycles and Figure 7.19 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. During programming, any command (except the Suspend Program command) is ignored. The SecSi Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. 28 S29WSxxxN_00_F0 October 29, 2004 Preliminary A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming to the same address multiple times continuously (for example, “walking” a bit within a word) for an extended period is not recommended. For more information, contact your local sales office. Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Data to Address: PA, PD Program Address (PA), Program Data (PD) Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Busy? No Yes Polling Status = Done? No Yes Error condition (Exceeded Timing Limits) PASS. Device is in read mode. FAIL. Issue reset command to return to read array mode. Figure 7.19. Single Word Program October 29, 2004 S29WSxxxN_00_F0 29 Preliminary Software Functions and Sample Code Table 7.20. Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Operation Write Write Write Write Single Word Program Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word (LLD Function = lld_ProgramCmd) Note: Base = Base Address. The following is a C source code example of using the single word program function. Refer to t he S pans io n Lo w Lev el Driver U s er ’s Gu ide ( avail able on www.am d.c o m a nd www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */ 7.5.2 Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard “word” programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the system writes the number of “word locations minus 1” that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the “Program Buffer to Flash” confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (Number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The “write-buffer-page” is selected by using the addresses AMAX - A5. The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple “write-buffer-pages.” This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected “write-buffer-page”, the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/ data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter will be decremented for every data load operation. Also, the last data loaded at a location before the “Program Buffer to Flash” confirm command will be programmed into the 30 S29WSxxxN_00_F0 October 29, 2004 Preliminary device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the “Program Buffer to Flash” command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then “go busy.” The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the “Number of Locations to Program” step. Write to an address in a sector different than the one specified during the Write-BufferLoad command. Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address” during the “write buffer data loading” stage of the operation. Write data other than the “Confirm Command” after the specified number of “data load” cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when using the write buffer Programming features in Unlock Bypass mode. Note that the SecSITM sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. However, programming the same word address multiple times without intervening erases requires a modified programming method. Please contact your local SpansionTM representative for details. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately eight times faster than programming one word at a time. October 29, 2004 S29WSxxxN_00_F0 31 Preliminary Software Functions and Sample Code Table 7.21. Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Write Buffer Program Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N–1)h (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Operation Write Write Write Write Program Address Program Address Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h Notes: 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. The following is a C source code example of using the write buffer program function. Refer to t he S pans io n Lo w Lev el Driver U s er ’s Gu ide ( avail able on www.am d.c o m a nd www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* Example: Write Buffer Abort Reset */ *( (UINT16 *)addr + 0x555 ) = 0x00AA; *( (UINT16 *)addr + 0x2AA ) = 0x0055; *( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write unlock cycle 1 /* write unlock cycle 2 /* write buffer abort reset */ */ */ 32 S29WSxxxN_00_F0 October 29, 2004 Preliminary Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Issue Write Buffer Load Command: Address 555h, Data 25h Load Word Count to Program Program Data to Address: SA = wc wc = number of words – 1 Yes wc = 0? Confirm command: SA 29h No Wait 4 µs Write Next Word, Decrement wc: PA data , wc = wc – 1 No Write Buffer Abort Desired? Perform Polling Algorithm Yes Write to a Different Sector Address to Cause Write Buffer Abort (see Write Operation Status flowchart) Polling Status = Done? No No Yes Error? Yes Write Buffer Abort? No Yes RESET. Issue Write Buffer Abort Reset Command FAIL. Issue reset command to return to read array mode. PASS. Device is in read mode. Figure 7.22. 7.5.3 Sector Erase Write Buffer Programming Operation The sector erase function erases one or more sectors in the memory array. (See Table 12.1, Memory Array Commands; and Figure 7.24, Sector Erase Operation.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of October 29, 2004 S29WSxxxN_00_F0 33 Preliminary sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to “Write Operation Status” for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 7.24 illustrates the algorithm for the erase operation. Refer to the “Erase/Program Operations” section for parameters and timing diagrams. 34 S29WSxxxN_00_F0 October 29, 2004 Preliminary Software Functions and Sample Code Table 7.23. Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command Operation Write Write Write Write Write Write Sector Erase Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Sector Address Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h (LLD Function = lld_SectorEraseCmd) Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA. The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Sector Erase Command *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)sector_address ) */ )= )= )= )= )= = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */ October 29, 2004 S29WSxxxN_00_F0 35 Preliminary Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure No Select Additional Sectors? Yes Write Additional Sector Addresses • Each additional cycle must be written within tSEA timeout • Timeout resets after each additional cycle is written • The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands No Poll DQ3. DQ3 = 1? Yes Yes Last Sector Selected? No • No limit on number of sectors • Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data Wait 4 µs Perform Write Operation Status Algorithm (see Figure 7.33) Status may be obtained by reading DQ7, DQ6 and/or DQ2. Yes Done? No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits) PASS. Device returns to reading array. FAIL. Write reset command to return to reading array. Notes: 1. 2. See Table 12.1 for erase command sequence. See the section on DQ3 for information on the sector erase timeout. Figure 7.24. Sector Erase Operation 36 S29WSxxxN_00_F0 October 29, 2004 Preliminary 7.5.4 Chip Erase Command Sequence Chip erase is a six-bus cycle operation as indicated by Table 12.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The “Command Definition” section in the appendix shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Software Functions and Sample Code Table 7.25. Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command Operation Write Write Write Write Write Write Chip Erase Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h (LLD Function = lld_ChipEraseCmd) The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x000 ) = = = = = = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */ 7.5.5 Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. How- October 29, 2004 S29WSxxxN_00_F0 37 Preliminary ever, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 7.35 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to the “Write Buffer Programming Operation” section and the “Autoselect Command Sequence” section for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Software Functions and Sample Code Table 7.26. Cycle 1 Operation Write Erase Suspend Word Address Bank Address Data 00B0h (LLD Function = lld_EraseSuspendCmd) Byte Address Bank Address The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */ Table 7.27. Cycle 1 Operation Write Erase Resume Word Address Bank Address Data 0030h (LLD Function = lld_EraseResumeCmd) Byte Address Bank Address The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */ 7.5.6 Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a “Write to Buffer” programming operation so that data can read from any nonsuspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) 38 S29WSxxxN_00_F0 October 29, 2004 Preliminary and updates the status bits. Addresses are “don't-cares” when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system must write the Program Resume command (address bits are “don't care”) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Software Functions and Sample Code Table 7.28. Cycle 1 Operation Write Program Suspend Word Address Bank Address Data 00B0h (LLD Function = lld_ProgramSuspendCmd) Byte Address Bank Address The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */ Table 7.29. Cycle 1 Operation Write Program Resume Word Address Bank Address Data 0030h (LLD Function = lld_ProgramResumeCmd) Byte Address Bank Address The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 7.5.7 Accelerated Program/Chip Erase Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. October 29, 2004 S29WSxxxN_00_F0 39 Preliminary The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated chip program and erase should be performed at room temperature (25°C ±10°C). If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising ACC to VHH. The ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result. The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. tACC locks all sector if set to VIL; tACC should be set to VIH for all other conditions. 7.5.8 Unlock Bypass The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The “Command Definition Summary” section shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. Software Functions and Sample Code The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the S pansion Low Level Driver User’s Guide ( available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. Table 7.30. Cycle 1 2 3 Description Unlock Unlock Entry Command Unlock Bypass Entry Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h */ */ */ (LLD Function = lld_UnlockBypassEntryCmd) Operation Write Write Write Data 00AAh 0055h 0020h /* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock /* At this point, programming only takes two write cycles. /* Once you enter Unlock Bypass Mode, do a series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations. cycle 1 cycle 2 bypass command */ */ */ */ */ 40 S29WSxxxN_00_F0 October 29, 2004 Preliminary Table 7.31. Cycle 1 2 Description Program Setup Command Program Command Unlock Bypass Program Byte Address Base + xxxh Program Address Word Address Base +xxxh Program Address Data 00A0h Program Data (LLD Function = lld_UnlockBypassProgramCmd) Operation Write Write /* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; *( (UINT16 *)pa ) = data; /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */ /* write program setup command /* write data to be programmed */ */ Table 7.32. Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2 Operation Write Write Unlock Bypass Reset Byte Address Base + xxxh Base + xxxh Word Address Base +xxxh Base +xxxh Data 0090h 0000h (LLD Function = lld_UnlockBypassResetCmd) /* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000; 7.5.9 Write Operation Status The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the October 29, 2004 S29WSxxxN_00_F0 41 Preliminary system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles. See the following for more information: Table 7.35, Write Operation Status, shows the outputs for Data# Polling on DQ7. Figure 7.33, Write Operation Status Flowchart, shows the D a t a # P o l l i n g a l g o r i t h m ; a n d F i g u r e 1 1 . 1 6 , D a t a # Po l l i n g T i m i n g s (During Embedded Algorithm), shows the Data# Polling timing diagram. 42 S29WSxxxN_00_F0 October 29, 2004 Preliminary START Read 1 (Note 6) DQ7=valid data? NO YES Erase Operation Complete Read 1 DQ5=1? NO YES Read 2 YES Read3= valid data? NO YES Write Buffer Programming? Read 2 Read 3 Program Operation Failed YES Programming Operation? NO Read 3 Device BUSY, Re-Poll NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) Device BUSY, Re-Poll Read 2 DQ2 toggling? NO YES DEVICE ERROR (Note 5) (Note 4) Read3 DQ1=1? YES NO NO YES Device BUSY, Re-Poll Erase Operation Complete Device in Erase/Suspend Mode Read 3 Read3 DQ1=1 AND DQ7 ≠ Valid Data? YES Write Buffer Operation Failed NO Notes: 1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3. May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4. Write buffer error if DQ1 of last read =1. 5. Invalid state, use RESET command to exit operation. 6. Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. Data polling algorithm valid for all operations except advanced sector protection. Device BUSY, Re-Poll Figure 7.33. Write Operation Status Flowchart October 29, 2004 S29WSxxxN_00_F0 43 Preliminary DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 7.33, Write Operation Status Flowchart; Figure 11.17, Toggle Bit Timings (During Embedded Algorithm), and Tables 7.34 and 7.35. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state. DQ2: Toggle Bit II . The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 7.34 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 7.33, the “DQ6: Toggle Bit I” section, and Figures 11.16–11.19. 44 S29WSxxxN_00_F0 October 29, 2004 Preliminary Table 7.34. If device is programming, DQ6 and DQ2 Indications then DQ6 toggles, toggles, toggles, does not toggle, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable. and the system reads at any address, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, actively erasing, erase suspended, at an address within sectors not selected for erasure, at any address, returns array data, programming in erase suspend toggles, Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 7.33 for more details. DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has ex- ceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timeout State Indicator. A fter writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details. October 29, 2004 S29WSxxxN_00_F0 45 Preliminary After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 7.35 shows the status of DQ3 relative to the other status bits. DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details. Table 7.35. Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector Erase Suspended Sector Non-Erase Suspended Sector Write Operation Status DQ7 (Note 2) DQ7# 0 INVALID (Not Allowed) Data 1 Data DQ7# DQ7# DQ7# DQ7# DQ6 Toggle Toggle INVALID (Not Allowed) Data No toggle Data Toggle Toggle Toggle Toggle DQ5 (Note 1) 0 0 INVALID (Not Allowed) Data 0 Data 0 0 1 0 DQ3 N/A 1 INVALID (Not Allowed) Data N/A Data N/A N/A N/A N/A DQ2 (Note 2) No toggle Toggle INVALID (Not Allowed) Data Toggle Data N/A N/A N/A N/A DQ1 (Note 4) 0 N/A INVALID (Not Allowed) Data N/A Data N/A 0 0 1 Program Suspend Mode (Note 3) Erase Suspend Mode Erase-SuspendRead Erase-Suspend-Program Write to Buffer (Note 5) BUSY State Exceeded Timing Limits ABORT State Notes: 1. 2. 3. 4. 5. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. Data are invalid for addresses in a Program Suspended sector. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. 46 S29WSxxxN_00_F0 October 29, 2004 Preliminary 7.6 Simultaneous Read/Write The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 11.23, Back-to-Back Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics (CMOS Compatible) table for read-while-program and read-while-erase current specification. 7.7 Writing Commands/Command Sequences When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 6.1–6.3 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current specification for the write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asynchronous” contain timing specification tables and timing diagrams for write operations. 7.8 Handshaking The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#. When the device is configured to operate in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the RDY pin (depending on the setting for bit 10 in the Configuration Register). It is recommended that the host system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to ensure optimal burst mode operation (see Table 7.15, Configuration Register). Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle before data is ready. October 29, 2004 S29WSxxxN_00_F0 47 Preliminary 7.9 Hardware Reset The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current will be greater. RESET# may be tied to the system reset circuitry which enables the system to read the bootup firmware from the Flash memory upon a system reset. See Figures 11.5 and 11.12 for timing diagrams. 7.10 Software Reset Software reset is part of the command set (see Table 12.1) that also returns the device to array read mode and must be used for the following conditions: 1. 2. 3. 4. 5. to exit Autoselect mode when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed exit sector lock/unlock operation. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. after any aborted operations Software Functions and Sample Code Table 7.36. Cycle Reset Command Operation Write Reset Byte Address Base + xxxh Word Address Base + xxxh Data 00F0h (LLD Function = lld_ResetCmd) Note: Base = Base Address. The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. /* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. 48 S29WSxxxN_00_F0 October 29, 2004 Preliminary If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence. If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command will not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details]. October 29, 2004 S29WSxxxN_00_F0 49 Preliminary 8 Advanced Sector Protection/Unprotection The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1. Hardware Methods Software Methods Lock Register (One Time Programmable) ACC = VIL (All sectors locked) Password Method (DQ2) Persistent Method (DQ1) (All boot sectors locked) WP# = VIL 64-bit Password (One Time Protect) PPB Lock Bit 0 = PPBs Locked 1,2,3 1 = PPBs Unlocked 1. Bit is volatile, and defaults to “1” on reset. 2. Programming to “0” locks all PPBs to their current state. 3. Once programmed to “0”, requires hardware reset to unlock. Memory Array Sector 0 Sector 1 Sector 2 Persistent Protection Bit (PPB)4,5 PPB 0 PPB 1 PPB 2 Dynamic Protection Bit (PPB)6,7,8 DYB 0 DYB 1 DYB 2 Sector N-2 Sector N-1 Sector N3 3. N = Highest Address Sector. PPB N-2 PPB N-1 PPB N 4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively DYB N-2 DYB N-1 DYB N 6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is “1” (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options). Figure 8.1. Advanced Sector Protection/Unprotection 50 S29WSxxxN_00_F0 October 29, 2004 Preliminary 8.1 Lock Register As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Ordering Information). The device programmer or host system must then choose which sector protection method to use. Programming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit (DQ1) Lock Register Password Protection Mode Lock Bit (DQ2) Table 8.1. Device S29WS256N Lock Register DQ3 1 DQ15-05 1 DQ4 1 DYB Lock Boot Bit DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Customer SecSi Sector Protection Bit S29WS128N/ S29WS064N Undefined 0 = sectors power up protected 1 = sectors power up unprotected PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit SecSi Sector Protection Bit For programming lock register bits refer to Table 12.2. Notes 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation will abort. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: 1. 2. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections 8.2–8.6. 8.2 Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. Notes 1. 2. 3. 4. Each PPB is individually programmed and all are erased in parallel. Entry command disables reads and writes for the bank selected. Reads within that bank will return the PPB status for that sector. Reads from other banks are allowed while writes are not allowed. October 29, 2004 S29WSxxxN_00_F0 51 Preliminary 5. 6. 7. 8. 9. All Reads must be performed using the Asynchronous mode. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program or erase command will not execute and will time-out without programming or erasing the PPB. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 10. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart below. 8.3 Dynamic Protection Bits Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs will be set (programmed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. Notes 1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. 3. 4. 5. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors may be modified depending upon the PPB state of that sector (see Table 8.2). The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to “0”). It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again will lock the PPBs, and the device operates normally again. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH. 6. 8.4 Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to “0”), this bit locks all PPB and when cleared (programmed to “1”), unlocks each sector. There is only one PPB Lock Bit per device. Notes 1. 2. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the desired settings. 52 S29WSxxxN_00_F0 October 29, 2004 Preliminary 8.5 Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”. The password is all “1”s when shipped from the factory. All 64-bit password combinations are valid as a password. There is no means to verify what the password is after it is set. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. The Password Mode Lock Bit is not erasable. The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur. 2. 3. 4. 5. 6. 7. 8. 9. 10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. October 29, 2004 S29WSxxxN_00_F0 53 Preliminary Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Enter Lock Register Command: Address 555h, Data 40h Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD XXXh = Address don’t care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock data may only be progammed once. Wait 4 µs Perform Polling Algorithm (see Write Operation Status flowchart) Yes Done? No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits) PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. FAIL. Write rest command to return to reading array. Figure 8.2. Lock Register Program Algorithm 54 S29WSxxxN_00_F0 October 29, 2004 Preliminary 8.6 Advanced Sector Protection Software Examples Table 8.2. Unique Device PPB Lock Bit 0 = locked 1 = unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1 Sector Protection Schemes Sector DYB 0 = protected 1 = unprotected x x 1 0 x x 0 1 Sector PPB 0 = protected 1 = unprotected 0 0 1 1 0 0 1 1 Sector Protection Status Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature. 8.7 Hardware Data Protection Methods The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods: 8.7.1. WP# Method The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the “outermost” boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution 8.7.2 ACC Method This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are disabled and hence all sectors are protected. October 29, 2004 S29WSxxxN_00_F0 55 Preliminary 8.7.3 Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. 8.7.4 Write Pulse “Glitch Protection” Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 8.7.5 Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. 56 S29WSxxxN_00_F0 October 29, 2004 Preliminary October 29, 2004 S29WSxxxN_00_F0 57 Preliminary 9 Power Conservation Modes 9.1 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 i n “DC Characteristics” represents the standby current specification 9.2 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in “DC Characteristics” represents the automatic sleep mode current specification. 9.3 Hardware RESET# Input Operation The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. 9.4 Output Disable (OE#) When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. 58 S29WSxxxN_00_F0 October 29, 2004 Preliminary 10 SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 words in length that consists of 128 words for factory data and 128 words for customersecured areas. All SecSi reads outside of the 256-word address range will return invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory SecSi Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer SecSi Sector is locked when shipped from the factory. Please note the following general conditions: While SecSi Sector access is enabled, simultaneous operations are allowed except for Bank 0. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads can be performed in the Asynchronous or Synchronous mode. Burst mode reads within SecSi Sector will wrap from address FFh back to address 00h. Reads outside of sector 0 will return memory array data. Continuous burst read past the maximum address is undefined. Sector 0 is remapped from memory array to SecSi Sector array. Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command must be issued to exit SecSi Sector Mode. The SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. Table 10.1. Sector Customer Factory SecSiTM Sector Addresses Address Range 000080h-0000FFh 000000h-00007Fh Sector Size 128 words 128 words 10.1 Factory SecSiTM Sector The Factory SecSi Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8 Word secure ESN only within the Factory SecSi Sector Customer code within the Customer SecSi Sector through the SpansionTM programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory SecSi Sector and Customer SecSi Sector permanently locked. Contact your local representative for details on using Spansion programming services. October 29, 2004 S29WSxxxN_00_F0 59 Preliminary 10.2 Customer SecSiTM Sector The Customer SecSi Sector is typically shipped unprotected (DQ6 set to “0”), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer SecSi Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer SecSi Sector area is protected, the Customer Indicator Bit will be permanently set to “1.” The Customer SecSi Sector can be read any number of times, but can be programmed and locked only once. The Customer SecSi Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer SecSi Sector area and none of the bits in the Customer SecSi Sector memory space can be modified in any way. The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer SecSi Sector, but reading in Banks 1 through 15 is available. Once the Customer SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence which return the device to the memory array at sector 0. 10.3 SecSiTM Sector Entry and SecSi Sector Exit Command Sequences The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. See Command Definition Table [SecSiTM Sector Command Table, Appendix Table 12.1 for address and data requirements for both command sequences. The SecSi Sector Entry Command allows the following commands to be executed Read customer and factory SecSi areas Program the customer SecSi Sector After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. Software Functions and Sample Code The following are C functions and source code examples of using the SecSi Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines. Table 10.2. Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle Operation Write Write Write SecSi Sector Entry Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h (LLD Function = lld_SecSiSectorEntryCmd) Note: Base = Base Address. /* Example: SecSi Sector Entry Command */ 60 S29WSxxxN_00_F0 October 29, 2004 Preliminary *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; *( (UINT16 *)base_addr + 0x555 ) = 0x0088; /* write unlock cycle 1 /* write unlock cycle 2 /* write Secsi Sector Entry Cmd */ */ */ Table 10.3. Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Operation Write Write Write Write SecSi Sector Program Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word (LLD Function = lld_ProgramCmd) Note: Base = Base Address. /* Once in the SecSi Sector mode, you program */ /* words using the programming algorithm. */ Table 10.4. Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle Operation Write Write Write SecSi Sector Entry Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0090h (LLD Function = lld_SecSiSectorExitCmd) Note: Base = Base Address. /* Example: SecSi Sector *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr Exit Command */ + 0x555 ) = 0x00AA; + 0x2AA ) = 0x0055; + 0x555 ) = 0x0090; + 0x000 ) = 0x0000; /* /* /* /* write write write write unlock cycle unlock cycle SecSi Sector SecSi Sector 1 2 Exit cycle 3 Exit cycle 4 */ */ */ */ October 29, 2004 S29WSxxxN_00_F0 61 Preliminary 11 Electrical Specifications 11.1 Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 3. 4. 20 ns +0.8 V –0.5 V –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 20 ns Figure 11.1. Maximum Negative Overshoot Waveform Figure 11.2. Maximum Positive Overshoot Waveform 62 S29WSxxxN_00_F0 October 29, 2004 Preliminary 11.2 Operating Ranges Wireless (W) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Supply Voltages VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Contact local sales office for VIO = 1.35 to +1.70 V.) +1.70 V to +1.95 V Notes: Operating ranges define those limits between which the functionality of the device is guaranteed. 11.3 Test Conditions Device Under Test CL Figure 11.3. Table 11.1. Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Test Specifications All Speed Options 30 3.0 @ 54, 66 MHz 2.5 @ 80 MHz 0.0–VIO VIO/2 VIO/2 Unit pF ns V V V October 29, 2004 S29WSxxxN_00_F0 63 Preliminary 11.4 Key to Switching Waveforms WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS 11.5 Switching Waveforms All Inputs and Outputs VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output Figure 11.4. Input Waveforms and Measurement Levels 11.6 VCC Power-up Parameter tVCS Description VCC Setup Time Test Setup Min Speed 1 Unit ms Notes: 1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs 2. VCC ramp rate –0.1 V. 8. Total current during accelerated programming is the sum of VACC and VCC currents. 9. VACC = VHH on ACC input. October 29, 2004 S29WSxxxN_00_F0 65 Preliminary 11.8 AC Characteristics 11.8.1. CLK Characterization Parameter fCLK tCLK tCH tCL tCR tCF Description CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Max Min Min 54 MHz 54 18.5 7.4 66 MHz 66 15.1 6.1 80 MHz 80 12.5 5.0 Unit MHz ns ns Max 3 3 2.5 ns tCLK tCH tCL CLK tCR tCF Figure 11.6. CLK Characterization 66 S29WSxxxN_00_F0 October 29, 2004 Preliminary 11.8.2 Synchronous/Burst Read Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tCAS tAVC tAVD tAOE Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z (Note 2) Output Enable to High Z (Note 2) CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse AVD Low to OE# Low Description Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Max 5 13.5 13.5 5 7 4 13.5 13.5 10 10 4 4 11.2 0 4 8 38.4 3.5 9 11.2 11.2 54 MHz 66 MHz 69 11.2 4 6 3 9 9 80 MHz Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. October 29, 2004 S29WSxxxN_00_F0 67 Preliminary 11.8.3 Timing Diagrams 5 cycles for initial access shown. tCES CE# 1 CLK tAVC AVD# tACS Addresses Aa 18.5 ns typ. (54 MHz) tCEZ 6 7 2 3 4 5 tAVD tACH Data (n) tIACC tAOE OE# tOE RDY (n) Hi-Z Da Da + 1 tBACC Hi-Z Da + 2 Da + 3 Da + n tBDH tRACC tOEZ Hi-Z tCR tRDYS Hi-Z Da Da + 1 Da + 2 Da + 2 Da + n Data (n + 1) RDY (n + 1) Hi-Z Hi-Z Data (n + 2) Da Da + 1 Da + 1 Da + 1 Da + n Hi-Z RDY (n + 2) Hi-Z Hi-Z Data (n + 3) Da Da Da Da Da + n Hi-Z RDY (n + 3) Hi-Z Hi-Z Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. 3. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode. Figure 11.7. CLK Synchronous Burst Mode Read 68 S29WSxxxN_00_F0 October 29, 2004 Preliminary tCES CE# 1 CLK tAVC AVD# tACS Addresses Ac 7 cycles for initial access shown. 2 3 4 5 6 7 tAVD tACH Data tIACC tAOE OE# tCR RDY Hi-Z DC DD tBACC DE DF D8 DB tBDH tRACC tOE tRACC tRDYS Notes: 1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode with wrap around. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (0-F). Figure 11.8. 8-word Linear Burst with Wrap Around tCES CE# 1 CLK tAVC AVD# tACS Addresses Ac 7 cycles for initial access shown. 2 3 4 5 6 7 tAVD tACH Data tAOE OE# tCR RDY Hi-Z tBACC tIACC DC DD DE DF D10 D13 tBDH tOE tRACC tRACC tRDYS Notes: 1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY. The device is in asynchronous mode with out wrap around. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 1st address in range (c-13). Figure 11.9. 8-word Linear Burst without Wrap Around October 29, 2004 S29WSxxxN_00_F0 69 Preliminary tCES CE# 1 CLK tAVC AVD# tACS Addresses Aa 6 wait cycles for initial access shown. tCEZ 6 2 3 4 5 tAVD tACH Data tIACC tAOE OE# tCR RDY Hi-Z Da Da+1 tBACC Hi-Z Da+2 Da+3 Da + n tBDH tRACC tOE tOEZ Hi-Z tRDYS Notes: 1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one cycle before valid data. Figure 11.10. Linear Burst with RDY Set One Cycle Before Data 11.8.4 AC Characteristics—Asynchronous Read Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Description Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Output Enable Hold Time Read Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min 7 13.5 0 10 10 0 54 MHz 66 MHz 70 70 8 4 6 11.2 80 MHz Unit ns ns ns ns ns ns ns ns ns ns Output Enable to High Z (see Note) CE# Setup Time to AVD# Note: Not 100% tested. 70 S29WSxxxN_00_F0 October 29, 2004 Preliminary CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS Note: RA = Read Address, RD = Read Data. OE# tCE Valid RD tOEZ RA tAAVDH Figure 11.11. Asynchronous Mode Read October 29, 2004 S29WSxxxN_00_F0 71 Preliminary 11.8.5 Hardware Reset (RESET#) Parameter JEDEC Std. tRP tRH RESET# Pulse Width Reset High Time Before Read (See Note) Description Min Min All Speed Options 30 200 Unit µs ns Note: Not 100% tested. CE#, OE# tRH RESET# tRP Figure 11.12. Reset Timings 72 S29WSxxxN_00_F0 October 29, 2004 Preliminary 11.8.6 Erase/Program Timing Parameter JEDEC tAVAV tAVWL tWLAX Standard tWC tAS tAH tAVDP Write Cycle Time (Note 1) Description Min Synchronous Asynchronous Synchronous Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Max Max Typ Typ 54 MHz 66 MHz 70 5 0 9 20 8 80 MHz Unit ns ns ns ns ns Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High tDVWH tWHDX tGHWL tWHEH tWLWH tWHWL tDS tDH tGHWL tCAS tCH tWP tWPH tSR/W tVID tVIDS tVCS 45 0 0 0 0 30 20 0 500 1 50 5 5 5 5 5 5 3 50 20 20 100 1 20 ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns µs µs µs µs µs Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Clock Setup Time to WE# Noise Pulse Margin on WE# Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Sector Protection Toggle Time During Programming Within a Protected Sector tELWL tCS tAVSW tAVHW tAVSC tAVHC tCSW tWEP tSEA tESL tPSL tASP tPSP Notes: 1. 2. 3. 4. 5. Not 100% tested. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. See the “Erase and Programming Performance” section for more information. Does not include the preprogramming time. October 29, 2004 S29WSxxxN_00_F0 73 Preliminary VIH Erase Command Sequence (last two cycles) Read Status Data CLK VIL tAVDP AVD# tAS Addresses 2AAh tAH SA 555h for chip erase 10h for chip erase VA In Progress VA Data 55h 30h tDS tDH Complete CE# OE# tWP WE# tCS tVCS VCC tCH tWHWH2 tWPH tWC Figure 11.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses 74 S29WSxxxN_00_F0 October 29, 2004 Preliminary Program Command Sequence (last two cycles) Read Status Data VIH CLK VIL tAVSW tAVDP tAVHW AVD tAS tAH Addresses 555h PA VA In Progress VA Data tCAS CE# A0h tDS tDH PD Complete OE# tWP WE# tCH tWHWH1 tCS tWC tVCS VCC tWPH Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 11.13. Asynchronous Program Operation Timings: WE# Latched Addresses October 29, 2004 S29WSxxxN_00_F0 75 Preliminary Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD tAVDP Addresses 555h PA VA Read Status Data VA In Progress Data tCAS CE# A0h PD tDS tDH Complete OE# tCSW tWP tCH WE# tWHWH1 tWPH tWC tVCS VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first rising edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 11.14. Synchronous Program Operation Timings: CLK Latched Addresses 76 S29WSxxxN_00_F0 October 29, 2004 Preliminary CE# AVD# WE# Addresses Data Don't Care A0h PA Don't Care PD Don't Care OE# ACC VID tVIDS tVID VIL or VIH Note: Use setup and hold times from conventional program operation. Figure 11.15. Accelerated Unlock Bypass Programming Timing AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA High Z tCEZ tOE tOEZ High Z Data Status Data Status Data Notes: 1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. Figure 11.16. Data# Polling Timings (During Embedded Algorithm) October 29, 2004 S29WSxxxN_00_F0 77 Preliminary AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA High Z tCEZ tOE tOEZ Data High Z Status Data Status Data Notes: 1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. Figure 11.17. Toggle Bit Timings (During Embedded Algorithm) CE# CLK AVD# Addresses VA VA OE# tIACC tIACC Status Data Status Data Data RDY Notes: 1. 2. 3. The timings are similar to synchronous read timings. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before data. Figure 11.18. Synchronous Data Polling Timings/Toggle Bit Timings 78 S29WSxxxN_00_F0 October 29, 2004 Preliminary Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 11.19. DQ2 vs. DQ6 Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 CLK Address (hex) AVD# 7C (stays high) C125 7D C126 7E C127 7F C127 7F C128 80 C129 81 C130 82 C131 83 tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D124 D125 D126 D127 D128 D129 D130 OE#, CE# (stays low) Notes: 1. 2. 3. 4. 5. RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. RDY will not go low and no additional wait states will be required if the Burst frequency is 66 MHz October 29, 2004 S29WSxxxN_00_F0 79 Preliminary Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 CLK Address (hex) AVD# 7C (stays high) C125 7D C126 7E C127 7F C127 7F tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D124 D125 D126 D127 Read Status OE#, CE# Notes: 1. 2. 3. 4. 5. (stays low) RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. RDY will not go low and no additional wait states will be required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in the Configuration Register is set to 0. Figure 11.21. Latency with Boundary Crossing into Program/Erase Bank 80 S29WSxxxN_00_F0 October 29, 2004 Preliminary Data D0 D1 AVD# Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following addresses being latched OE# 1 CLK 0 1 2 3 4 5 6 7 2 3 4 5 number of clock cycles programmed Wait State Configuration Register Setup: D13, D13, D13, D13, D13, D13, D13, D13, D12, D12, D12, D12, D12, D12, D12, D12, D11 D11 D11 D11 D11 D11 D11 D11 = = = = = = = = “111” “110” “101” “100” “011” “010” “001” “000” ⇒ Reserved ⇒ Reserved ⇒ 5 programmed, 7 total ⇒ 4 programmed, 6 total ⇒ 3 programmed, 5 total ⇒ 2 programmed, 4 total ⇒ 1 programmed, 3 total ⇒ 0 programmed, 2 total Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”. Figure 11.22. Example of Wait States Insertion October 29, 2004 S29WSxxxN_00_F0 81 Preliminary Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tWC tRC tRC tWC CE# OE# tOE tOEH WE# tWPH tWP tDS PD/30h tGHWL tACC tDH RD tOEZ tOEH RD AAh Data tSR/W Addresses PA/SA RA RA 555h tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 11.23. Back-to-Back Read/Write Cycle Timings 82 S29WSxxxN_00_F0 October 29, 2004 Preliminary 11.8.7 Erase and Programming Performance Parameter Sector Erase Time 64 Kword 16 Kword VCC VCC VCC Chip Erase Time ACC VCC ACC VCC ACC VCC ACC VCC Chip Programming Time (Note 3) ACC Typ (Note 1) 0.6