S29WS256P0PBAW002

S29WS-P MirrorBit® Flash Family S29WS512P, S29WS256P, S29WS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory S29WS-P Cover Sheet Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S29WS-P_00 Revision A Amendment 11 Issue Date September 28, 2007 Data Sheet Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. 2 S29WS-P S29WS-P_00_A11 September 28, 2007 S29WS-P MirrorBit® Flash Family S29WS512P, S29WS256P, S29WS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory Data Sheet Features Single 1.8 V read/program/erase (1.70–1.95 V) 90 nm MirrorBit™ Technology Simultaneous Read/Write operation with zero latency Random page read access mode of 8 words with 20 ns intra page access time 32 Word / 64 Byte Write Buffer Sixteen-bank architecture consisting of 32/16/8 Mwords for 512/256/128P, respectively Four 16 Kword sectors at both top and bottom of memory array 510/254/126 64Kword sectors (WS512/256/128P) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and 128 words for customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Handshaking by monitoring RDY Offered Packages – WS512P/WS256P/WS128P: 84-ball FBGA (11.6 mm x 8 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI) General Description The Spansion S29WS512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption. Performance Characteristics Read Access Times Speed Option (MHz) Max. Synch Access Time (tIACC) Max. Synch. Burst Access, ns (tBACC) Max OE# Access Time, ns (tOE) Max. Asynch. Access Time, ns (tACC) 104 103.8 7.6 7.6 80 Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 40 µs 9.4 µs 6 µs 350 ms 600 ms Current Consumption (typical values) Continuous Burst Read @ 104 MHz Simultaneous Operation 104 MHz Program Standby Mode 36 mA 40 mA 20 mA 20 µA Publication Number S29WS-P_00 Revision A Amendment 11 Issue Date September 28, 2007 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2. 3. 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 MCP Look-ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 13 5. 6. 7. Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Synchronous (Burst) Read Mode & Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Simultaneous Read/Program or Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Power-up/Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 19 20 20 28 32 34 51 51 52 52 52 54 55 55 56 58 58 59 60 62 62 62 62 62 63 63 64 64 66 66 66 67 68 68 68 69 8. 9. 10. 11. 4 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 11.8 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.10 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12. 13. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 September 28, 2007 S29WS-P_00_A11 S29WS-P 5 Data Sheet Figures Figure 4.1 Figure 4.2 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 8.1 Figure 8.2 Figure 8.3 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12 Figure 11.13 Figure 11.14 Figure 11.15 Figure 11.16 Figure 11.17 Figure 11.18 Figure 11.19 Figure 11.20 Figure 11.21 Figure 11.22 Figure 11.23 Figure 11.24 Figure 11.25 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBH084—84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package. . . . . Synchronous/Asynchronous State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 8-word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# Toggling - Case 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Mode (AVD# tied to CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 28 29 35 39 42 48 54 57 60 66 66 68 68 69 69 71 71 72 73 73 74 74 75 77 78 79 79 80 80 81 81 82 82 83 6 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Tables Table 2.1 Table 6.1 Table 6.2 Table 6.3 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Table 7.13 Table 7.14 Table 7.15 Table 7.16 Table 7.17 Table 7.18 Table 7.19 Table 7.20 Table 7.21 Table 7.22 Table 7.23 Table 7.24 Table 7.25 Table 7.26 Table 7.27 Table 7.28 Table 7.29 Table 7.30 Table 7.31 Table 7.32 Table 7.33 Table 7.34 Table 7.35 Table 7.36 Table 7.37 Table 7.38 Table 7.39 Table 7.40 Table 7.41 Table 7.42 Table 7.43 Table 7.44 Table 7.45 Table 7.46 Table 7.47 Table 7.48 Table 8.1 Table 8.2 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 S29WS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 S29WS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 S29WS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Page Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 09 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 11 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 10 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Reset (LLD Function = lld_ResetCmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 September 28, 2007 S29WS-P_00_A11 S29WS-P 7 Data Sheet Table 8.3 Table 8.4 Table 8.5 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 Table 11.7 Table 12.1 Table 12.2 Table 12.3 Table 12.4 Table 12.5 Table 12.6 S29WS512P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 S29WS256P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 S29WS128P Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Non-Continuous Burst Mode with Wrap Around Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . .70 Continuous Burst Mode with No Wrap Around Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .70 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 8 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 1. Ordering Information The ordering part number is formed by a valid combination of the following: S29WS 512 P xx BA W 00 0 Packing Type 0 = Tray (standard; see note 1) 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number (Chip Enable Options) 00 = Default Temperature Range W = Wireless (–25°C to +85°C) Package Type And Material BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package Speed Option (Burst Frequency) 0L = 54 MHz 0P = 66 MHz 0S = 80 MHz AB = 104 MHz Process Technology P = 90 nm MirrorBit®Technology Flash Density 512= 512 Mb 256= 256 Mb 128= 128 Mb Device Family S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory 1.1 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29WS512P Valid Combinations (Notes 1, 2) Base Ordering Part Number S29WS512P S29WS256P Advance S29WS128P Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. 0L, 0P, 0S, AB BAW (Lead (Pb)-free Compliant), BFW (Lead (Pb)-free) 0, 2, 3 (Note 1) 00 11.6 mm x 8 mm 84-ball MCP-Compatible Product Status Speed Option Package Type, Material, & Temperature Range Packing Type Model Numbers Package Type (Note 2) 11.6 mm x 8 mm 84-ball MCP-Compatible September 28, 2007 S29WS-P_00_A11 S29WS-P 9 Data Sheet 2. Input/Output Descriptions & Logic Symbol Table identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Symbol AMAX–A0 DQ15–DQ0 CE# OE# WE# VCC VCCQ VSS NC RDY CLK Type Input I/O Input Input Input Supply Supply Supply No Connect Output Input Description Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and 22 for WS128P) Data input/output. Chip Enable. Asynchronous relative to CLK. Output Enable. Asynchronous relative to CLK. Write Enable. Device Power Supply Device Input/Output Power Supply (Must be ramped simultaneously with VCC) Ground. Not connected internally. Ready. Indicates when valid burst data is ready to be read. Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid. Indicates to device that the valid address is present on the address inputs. AVD# Input When low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. When high, device ignores address inputs. RESET# WP# ACC RFU Input Input Input Reserved Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use (see MCP look-ahead pinout for use with MCP). 10 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 3. Block Diagrams VCC Y-Decoder Bank Address Latches and Control Logic VSS VCCQ DQ15–DQ0 Bank 0 AMAX–A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder DQ15–DQ0 Bank 1 WP# ACC RESET# WE# CEx# AVD# RDY DQ15–DQ0 AMAX–A0 X-Decoder DQ15–DQ0 Status STATE CONTROL & COMMAND REGISTER AMAX–A0 Control X-Decoder Latches and Control Logic Y-Decoder Bank Address Bank (n-1) DQ15–DQ0 AMAX–A0 X-Decoder Bank Address Latches and Control Logic Y-Decoder Bank (n) DQ15–DQ0 Notes: 1. AMAX-A0 = A24-A0 for the WS512P, A23-A0 for the WS256P, and A22-A0 for the WS128P. 2. n = 15 for WS512P / WS256P / WS128P. 4. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S29WS-P. 4.1 Related Documents The following documents contain information relating to the S29WS-P devices. Click on the title or go to www.spansion.com to download the PDF file, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. September 28, 2007 S29WS-P_00_A11 S29WS-P 11 Data Sheet Figure 4.1 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb (Top View, Balls Facing Down, MCP Compatible) A1 NC B2 AVD# C2 WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 F-CE# J2 RFU K2 RFU L2 RFU M1 NC B3 VSS C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 RFU D4 RFU E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 VSS B5 RFU C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCC K5 DQ11 L5 VCC B6 VCC C6 WE# D6 RFU E6 A20 F6 A23 G6 RFU H6 DQ4 J6 RFU K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 A24 H8 DQ15 J8 DQ7 K8 DQ14 L8 VCCQ B9 RFU C9 RFU D9 A15 E9 A10 NC Legend Reserved for Future Use Do Not Use Ground A21 F9 A22 G9 A16 H2 RFU J9 VSS K9 RFU L9 RFU M10 NC Power Notes: 1. Balls F6 and G8 are RFU on the WS128P. 2. Ball G8 is RFU on the WS256P. 3. VCC pins must ramp simultaneously. 12 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Figure 4.2 VBH084—84-ball Fine-Pitch Ball Grid Array, 11.6 x 8 mm MCP Compatible Package 0.05 C (2X) D A D1 e 10 9 e 8 7 6 7 SE E1 E 5 4 3 2 1 M L K J H G F E D C B A A1 CORNER A1 CORNER INDEX MARK B 10 0.05 C (2X) 6 SD φ 0.08 M C φ 0.15 M C A B 7 NXφb TOP VIEW BOTTOM VIEW A A1 SEATING PLANE A2 0.10 C C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC VBH 084 N/A 11.60 mm x 8.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.33 MIN --0.18 0.62 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 --0.80 BSC. 0.40 BSC. (A2-A9, B10-L10, M2-M9, B1-L1) 0.43 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3339 \ 16-038.25b Note: BSC is an ANSI standard for Basic Space Centering. 4.3 MCP Look-ahead Connection Diagram Spansion Inc. provides this standard look-ahead connection diagram that supports NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits NOR Flash and pSRAM and data storage densities up to 4 Gigabits The physical package outline may vary between connection diagrams and densities. The connection diagram for any MCP, however, is a subset of the pinout. September 28, 2007 S29WS-P_00_A11 S29WS-P 13 Data Sheet In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls are reserved; do not connect them to any other signal. For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless Solutions with Spansion Products application note (publication number: Design_Scalable_Wireless_AN), available on the web or through a Spansion sales office. 14 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 5. Additional Resources Visit www.spansion.com to obtain the following related documents: Application Notes Using the Operation Status Bits in AMD Devices Understanding Burst Mode Flash Memory Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions Specification Bulletins Contact your local sales office for details. Drivers and Software Support Spansion low-level drivers True Flash File System CAD Modeling Support VHDL and Verilog IBIS ORCAD® Schematic Symbols Technical Support Contact your local sales office or contact Spansion Inc. directly for additional technical support: http://www.spansion.com/flash_memory_products/support/ses/index.html Spansion Inc. Locations 915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited Cube-Kawasaki 9F/10F, 1-14 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa, 210-0024, Japan Phone: 044-223-1700 (active from Nov.28th) http://www.spansion.com September 28, 2007 S29WS-P_00_A11 S29WS-P 15 Data Sheet 6. Product Overview The S29WS-P family consists of 512, 256, and 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable. 6.1 Memory Map The S29WS512/256/128P Mbit devices consist of 16 banks organized as shown in Tables 6.1–6.3. Table 6.1 S29WS512P Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) 32 32 4 32 4 MB 32 128 … 31 0 SA002 SA003 SA004 … 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh … Sector Starting Address – Sector Ending Address (see note) Bank Sector/ Sector Range SA000 SA001 Address Range 000000h–003FFFh 004000h–007FFFh Sector Starting Address – Sector Ending Address Notes 128 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 4 MB 32 32 32 32 32 32 32 32 32 32 32 32 32 32 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA034 SA035–SA066 SA067–SA098 SA099–SA130 SA131–SA162 SA163–SA194 SA195–SA226 SA227–SA258 SA259–SA290 SA291–SA322 SA323–SA354 SA355–SA386 SA387–SA418 SA419–SA450 SA451–SA482 SA483 1F0000h–1FFFFFh 200000h–3FFFFFh ………… E00000h–FFFFFFh 1000000-11FFFFF …………… First Sector, Starting Address – Last Sector, Ending Address (see note) 1C00000h-1DFFFFFh 1E00000h-1E0FFFFh Sector Starting Address – Sector Ending Address (see note) 31 128 SA513 4 MB 4 32 SA516 SA517 15 SA514 SA515 … 1FE0000h-1FEFFFFh 1FF0000h-1FF3FFFh 1FF4000h-1FF7FFFh 1FF8000h-1FFBFFFh 1FFC000h-1FFFFFFh Sector Starting Address – Sector Ending Address Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA033) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. 16 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 6.2 S29WS256P Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) Bank Sector/ Sector Range SA000 SA001 4 2 MB 32 0 SA002 SA003 15 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SA004 to SA018 SA019 to SA034 SA035 to SA050 SA051 to SA066 SA067 to SA082 SA083 to SA098 SA099 to SA114 SA115 to SA130 SA131 to SA146 SA147 to SA162 SA163 to SA178 SA179 to SA194 SA195 to SA210 SA211 to SA226 SA227 to SA242 SA243 to SA257 SA258 2 MB 4 32 SA260 SA261 FF8000h–FFBFFFh FFC000h–FFFFFFh 15 SA259 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh to 0F0000h–0FFFFFh 100000h–10FFFFh to 1F0000h–1FFFFFh 200000h–20FFFFh to 2F0000h–2FFFFFh 300000h–30FFFFh to 3F0000h–3FFFFFh 400000h–40FFFFh to 4F0000h–4FFFFFh 500000h–50FFFFh to 5F0000h–5FFFFFh 600000h–60FFFFh to 6F0000h–6FFFFFh 700000h–70FFFFh to 7F0000h–7FFFFFh 800000h–80FFFFh to 8F0000h–8FFFFFh 900000h–90FFFFh to 9F0000h–9FFFFFh A00000h–A0FFFFh to AF0000h–AFFFFFh B00000h–B0FFFFh to BF0000h–BFFFFFh C00000h–C0FFFFh to CF0000h–CFFFFFh D00000h–D0FFFFh to DF0000h–DFFFFFh E00000h–E0FFFFh to EF0000h–EFFFFFh F00000h–F0FFFFh to FE0000h–FEFFFFh FF0000h–FF3FFFh FF4000h–FF7FFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) Address Range 000000h–003FFFh 004000h–007FFFh Contains four smaller sectors at bottom of addressable memory. Notes Note This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. September 28, 2007 S29WS-P_00_A11 S29WS-P 17 Data Sheet Table 6.3 S29WS128P Sector & Memory Address Map Bank Size Sector Count Sector Size (KB) 32 32 4 1 MB 32 32 7 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 32 1 MB 4 32 32 SA132 SA133 7F8000h–7FBFFFh 7FC000h–7FFFFFh 32 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 SA002 SA003 SA004 to SA010 SA011 to SA018 SA019 to SA026 SA027 to SA034 SA035 to SA042 SA043 to SA050 SA051 to SA058 SA059 to SA066 SA067 to SA074 SA075 to SA082 SA083 to SA090 SA091 to SA098 SA099 to SA106 SA107 to SA114 SA115 to SA122 SA123 to SA129 SA130 SA131 008000h–00BFFFh 00C000h–00FFFFh 010000h–01FFFFh to 070000h–07FFFFh 080000h–08FFFFh to 0F0000h–0FFFFFh 100000h–10FFFFh to 170000h–17FFFFh 180000h–18FFFFh to 1F0000h–1FFFFFh 200000h–20FFFFh to 270000h–27FFFFh 280000h–28FFFFh to 2F0000h–2FFFFFh 300000h–30FFFFh to 370000h–37FFFFh 380000h–38FFFFh to 3F0000h–3FFFFFh 400000h–40FFFFh to 470000h–47FFFFh 480000h–48FFFFh to 4F0000h–4FFFFFh 500000h–50FFFFh to 570000h–57FFFFh 580000h–58FFFFh to 5F0000h–5FFFFFh 600000h–60FFFFh to 670000h–67FFFFh 680000h–68FFFFh to 6F0000h–6FFFFFh 700000h–70FFFFh to 770000h–77FFFFh 780000h–78FFFFh to 7E0000h–7EFFFFh 7F0000h–7F3FFFh 7F4000h–7F7FFFh Contains four smaller sectors at top of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) Bank Sector/ Sector Range SA000 SA001 Address Range 000000h–003FFFh 004000h–007FFFh Contains four smaller sectors at bottom of addressable memory. Notes Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh. 7. Device Operations This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 12.1 on page 85 and Table 12.2 on page 87). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 18 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 7.1 Device Operation Table The device must be setup appropriately for each operation. Table 7.1 describes the required state of each control pin for any particular operation. Table 7.1 Device Operations Operation Asynchronous Read - Addresses Latched Asynchronous Read AVD# Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations Latch Starting Burst Address by CLK Advance Burst read to next address Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L X L X X X H H H H H X X L H X X Addr In X X X Addr In Output Invalid Output Valid HIGH Z HIGH Z Output Invalid = toggle. X H HIGH Z HIGH Z X H H H L H CE# L L L L H X OE# L L H H X X L X X X X X X WE# H H CLK X X X L L AVD# Amax–A0 Addr In Addr In Addr In Addr In X X DQ15–0 Output Valid Output Valid Input Valid I/O HIGH Z HIGH Z RDY H H H H HIGH Z HIGH Z RESET# H H H H H Legend: L = Logic 0, H = Logic 1, X = can be either VIL or VIH., Note: Address is latched on the rising edge of clock. = rising edge, = high to low, 7.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address, preventing changes to the address lines from effecting the address being accessed.. Data is output on DQ15-DQ0 pins after the access time (tACC) has elapsed from the falling edge of AVD#, or the last time the address lines changed while AVD# was low. September 28, 2007 S29WS-P_00_A11 S29WS-P 19 Data Sheet 7.3 Page Mode Read The device is capable of fast page mode read. This mode provides fast (tPACC) random read access speed for locations within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. It does not matter if AVD# stays low or toggles. However, the address input must be always valid and stable if AVD# is low during the page read. The random or initial page access is tACC or tCE (depending on how the device was accessed) and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (=VIH), the reassertion of CE# for subsequent access has access time of tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page. Table 7.2 Page Select Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 7.4 Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operations and can be automatically enabled for burst mode. To enter into synchronous mode, the configuration register will need to be set. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. Once the system has written the Set Configuration Register command sequence, the device is enabled for synchronous reads only. The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge of the clock. RDY indicates the initial latency. 7.4.1 Latency Tables for Variable Wait State The following tables show the latency for variable wait state in a continuous Burst operation Table 7.3 Address Latency for 11 Wait States Word 0 1 2 3 Initial Wait D0 D1 D2 D3 11 ws D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 1 ws D2 D3 D4 D5 D6 D7 1 ws 1 ws D3 D4 D5 D6 D7 1 ws 1 ws 1 ws D4 D5 D6 D7 1 ws 1 ws 1 ws 1 ws D5 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D8 D8 D8 D8 D9 D9 D9 D9 D9 D9 D9 D9 D10 D10 D10 D10 D10 D10 D10 D10 … … … … … … … … D124 D124 D124 D124 D124 D124 D124 D124 D125 D125 D125 D125 D125 D125 D125 D125 D126 D126 D126 D126 D126 D126 D126 D126 D127 D127 D127 D127 D127 D127 D127 D127 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 D0 D0 D0 D0 4 5 6 7 20 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 7.4 Address Latency for 10 Wait States Word 0 1 2 3 10 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 … … … … D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 … … … … D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Table 7.5 Address Latency for 09 Wait States Word 0 1 2 3 9 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 … … … … D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 … … … … D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Table 7.6 Address Latency for 8 Wait States Word 0 1 2 3 8 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 Table 7.7 Address Latency for 7 Wait States Word 0 1 2 3 7 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 September 28, 2007 S29WS-P_00_A11 S29WS-P 21 Data Sheet Table 7.8 Address Latency for 6 Wait States Word 0 1 2 3 6 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 7.9 Address Latency for 5 Wait States Word 0 1 2 3 5 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 7.10 Address Latency for 4 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 D13 D13 D13 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 7.11 Address Latency for 3 Wait States Word 0 1 2 3 3 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 D9 D10 D11 D11 D10 D11 D12 D12 D11 D12 D13 D13 D12 D13 D14 D14 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 22 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 7.4.2 Latency for Boundary Crossing during First Read The following tables show the latency at End of Word Line for boundary corssing during First Read in continuous burst operation Table 7.12 Address Latency for 11 Wait States Word 0 1 2 3 11 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 Table 7.13 Address Latency for 10 Wait States Word 0 1 2 3 10 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Table 7.14 Address Latency for 9 Wait States Word 0 1 2 3 9 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws D0 D0 D0 D0 Table 7.15 Address Latency for 8 Wait States Word 0 1 2 3 8 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 D0 D0 D0 D0 D1 D1 D1 September 28, 2007 S29WS-P_00_A11 S29WS-P 23 Data Sheet Table 7.16 Address Latency for 7 Wait States Word 0 1 2 3 7 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 D0 D0 D127 D0 D1 D1 D0 D1 D2 D2 Table 7.17 Address Latency for 6 Wait States Word 0 1 2 3 6 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3 Table 7.18 Address Latency for 5 Wait States Word 0 1 2 3 5 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 1 ws 1 ws 1 ws D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D4 D4 D4 D4 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3 Table 7.19 Address Latency for 4 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 1 ws 1 ws D127 D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D2 D3 D3 D3 D3 D12 D12 D12 D4 D5 D5 D5 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3 24 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 7.20 Address Latency for 3 Wait States Word 0 1 2 3 3 ws 4 5 6 7 D124 D125 D126 D127 D125 D126 D127 1 ws D126 D127 D0 D0 D127 D0 D1 D1 D0 D1 D2 D2 D1 D2 D3 D3 D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 Initial Wait D120 D121 D122 D123 D121 D122 D123 D124 D122 D123 D124 D125 D123 D124 D125 D126 D124 D125 D126 D127 D125 D126 D127 D0 D126 D127 D0 D1 D127 D0 D1 D2 D0 D1 D2 D3 7.4.3 Latency at End of Word Line for Boundary Crossing After Second Read in Continuous Burst Operation The following tables show the latency for boundary crossing after Second Read in a continuous Burst operation. Table 7.21 Address Latency for 11 Wait States Word 0 1 2 3 Initial Wait D112 D113 D114 D115 11 ws D116 D117 D118 D119 D113 D114 D115 D116 D117 D118 D119 1 ws D114 D115 D116 D117 D118 D119 1 ws 1 ws D115 D116 D117 D118 D119 1 ws 1 ws 1 ws D116 D117 D118 D119 1 ws 1 ws 1 ws 1 ws D117 D118 D119 1 ws 1 ws 1 ws 1 ws 1 ws D118 D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D120 D120 D120 D120 D121 D121 D121 D121 D121 D121 D121 D121 D122 D122 D122 D122 D122 D122 D122 D122 D123 D123 D123 D123 D123 D123 D123 D123 D124 D124 D124 D124 D124 D124 D124 D124 D125 D125 D125 D125 D125 D125 D125 D125 D126 D126 D126 D126 D126 D126 D126 D126 D127 D127 D127 D127 D127 D127 D127 D127 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws 2 ws D0 D0 D0 D0 D0 D0 D0 D0 4 5 6 7 Table 7.22 Address Latency for 10 Wait States Word 0 1 2 3 10 ws 4 5 6 7 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Initial Wait D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 1 ws 1 ws 1 ws 1 ws D0 D0 D0 D0 Table 7.23 Address Latency for 9 Wait States Word 0 1 2 3 9 ws 4 5 6 7 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 September 28, 2007 S29WS-P_00_A11 S29WS-P 25 Data Sheet Table 7.24 Address Latency for 8 Wait States Word 0 1 2 3 8 ws 4 5 6 7 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D113 D114 D113 D113 D114 D115 D114 D114 D115 D116 D115 D115 D116 D117 D116 D116 D117 D118 D117 D117 D118 D119 D118 D118 D119 1 ws D119 D119 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Table 7.25 Address Latency for 7 Wait States Word 0 1 2 3 7 ws 4 5 6 7 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Table 7.26 Address Latency for 6 Wait States Word 0 1 2 3 6 ws 4 5 6 7 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Table 7.27 Address Latency for 5 Wait States Word 0 1 2 3 5 ws 4 5 6 7 D112 D113 D114 D115 D113 D114 D115 D116 D114 D115 D116 D117 D115 D116 D117 D118 D116 D117 D118 D119 D117 D118 D119 1 ws D118 D119 1 ws 1 ws D119 1 ws 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 26 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 7.28 Address Latency for 4 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D112 D112 D113 D114 D113 D113 D114 D115 D114 D114 D115 D116 D115 D115 D116 D117 D116 D116 D117 D118 D117 D117 D118 D119 D118 D118 D119 1 ws D119 D119 1 ws 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Table 7.29 Address Latency for 3 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 1 ws D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 Initial Wait D112 D112 D112 D112 D113 D113 D113 D113 D114 D114 D114 D114 D115 D115 D115 D115 D116 D116 D116 D116 D117 D117 D117 D117 D118 D118 D118 D118 D119 D119 D119 D119 D120 D120 D120 D120 D121 D121 D121 D121 D122 D122 D122 D122 D123 D123 D123 D123 D124 D124 D124 D124 D125 D125 D125 D125 D126 D126 D126 D126 D127 D127 D127 D127 D0 D0 D0 D0 September 28, 2007 S29WS-P_00_A11 S29WS-P 27 Data Sheet 7.5 Synchronous (Burst) Read Mode & Configuration Register See Configuration Registers on page 31, and Table 12.1, Memory Array Commands on page 85, for further details. Figure 7.1 Synchronous/Asynchronous State Diagram Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1) Synchronous Read Mode Only 28 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Figure 7.2 Synchronous Read Flow Chart Note: Setup Configuration Register parameters Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR Command Cycle CR = Configuration Register Bits CR15-CR0 Load Initial Address Address = RA RA = Read Address Wait tIACC + Programmable Wait State Setting CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles Read Initial Data RD = DQ[15:0] RD = Read Data Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing Refer to the Latency tables. Read Next Data RD = DQ[15:0] Delay X Clocks Crossing Boundary? No Yes End of Data? Yes Completed 7.5.1 Continuous Burst Read Mode In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET#= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary with in the same bank, but not into a program or erase suspended sector (as mentioned above), additional latency cycles are required as reflected by the configuration register table (Table 7.31). If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. September 28, 2007 S29WS-P_00_A11 S29WS-P 29 Data Sheet 7.5.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 7.30). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 383Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note In this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. Table 7.30 Burst Address Groups Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,... Group Address Ranges 7.5.3 8-, 16-, 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 3Ch43h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state. 30 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 7.5.4 Configuration Registers This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 12.1 on page 85). The following list describes the register settings. Table 7.31 Configuration Register CR Bit CR0.15 CR0.14 CR1.0 CR0.13 CR0.12 Function Set Device Read Mode Reserved (Not used) Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (Default) 0 = Reserved (Default) 1 = Reserved 0000 = initial data is valid on the 2nd rising CLK edge after addresses are latched 0001 = initial data is valid on the 3rd rising CLK edge after addresses are latched 0010 = initial data is valid on the 4th rising CLK edge after addresses are latched 0011 = initial data is valid on the 5th rising CLK edge after addresses are latched 0100 = initial data is valid on the 6th rising CLK edge after addresses are latched 0101 = initial data is valid on the 7th rising CLK edge after addresses are latched 0110 = Reserved Programmable Wait State CR0.11 0111 = Reserved 1000 = initial data is valid on the 8th rising CLK edge after addresses are latched 1001 = initial data is valid on the 9th rising CLK edge after addresses are latched 1010 = initial data is valid on the 10th rising CLK edge after addresses are latched 1011 = initial data is valid on the 11th rising CLK edge after addresses are latched 1100 = Reserved 1101 = default 1110 = Reserved 1111 = Reserved CR0.10 RDY Polarity Reserved (Not used) RDY Reserved (Not used) Reserved Reserved RDY Function Burst Wrap Around 0 = RDY signal is active low 1 = RDY signal is active high (Default) 0 = Reserved 1 = Reserved (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved (Default) 1 = Reserved 0 = RDY (Default) 1 = Reserved 0 = No Wrap Around Burst 1 = Wrap Around Burst (Default) 000 = Continuous (Default) 010 = 8-Word Linear Burst Burst Length CR0.0 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes: 1. Device will be in the Asynchronous Mode upon power-up or hardware reset. 2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default). 3. CR0.3 is ignored if in continuous read mode (no warp around). 4. A software reset command is required after reading or writing the configuration registers in order to set the device back to array read mode. CR0.9 CR0.8 CR0.7 CR0.6 CR0.5 CR0.4 CR0.3 CR0.2 CR0.1 September 28, 2007 S29WS-P_00_A11 S29WS-P 31 Data Sheet 5. Refer to Table 12.1 on page 85 for reading the settings and writing onto configuration registers command sequences. 6. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings. 7.6 Autoselect The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 7.32 on page 32). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). See Table 12.1 on page 85 for command sequence details. Table 7.32 Autoselect Addresses Description Manufacturer ID Word 00 Device ID, Word 01 Sector Lock/Unlock Word 02 Address (BA) + 00h Read Data 0001h (BA) + 01h 227Eh 0001h = Locked, 0000h = Unlocked DQ15 - DQ8 = reserved DQ7 - Factory Lock Bit; 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit; 1 = Locked, 0 = Not Locked (SA) + 02h Indicator Bits Word 03 (BA) + 03h DQ5 - Handshake Bit; 1 = Reserved, 0 = Standard Handshake DQ4 & DQ3 - WP# Protection Boot Code; 00 = WP# Protects both Top Boot and Bottom Boot Sectors, DQ2 - DQ0 = reserved Device ID, Word 0E Device ID, Word 0F 223Dh (WS512P)-1CE# (BA) + 0Eh 2242h (WS256P) 2244h (WS128P) (BA) + 0Fh 2200h 32 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Software Functions and Sample Code Table 7.33 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Byte Address BA+AAAh BA+555h BA+AAAh Word Address BA+555h BA+2AAh BA+555h Data 0x00AAh 0x0055h 0x0090h Table 7.34 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Cycle Unlock Cycle 1 Notes: 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. Operation Write Byte Address xxxxh Word Address xxxxh Data 0x00F0h The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User’s Guide for general information on Spansion Flash memory software development guidelines. /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef volatile unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ September 28, 2007 S29WS-P_00_A11 S29WS-P 33 Data Sheet 7.7 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the configuration register (Table 7.31 on page 31). During synchronous write operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. Addresses are latched on the rising edge of AVD# pulse or rising edge of CLK or falling edge of WE#, whichever occurs first. During asynchronous write operations, addresses are latched on the rising edge of AVD# or falling edge of WE# while data is latched on the 1st rising edge of WE#, or CE# whichever comes first. Note the following: When the Embedded Program/Erase algorithm is complete, the device returns to the read mode. The system can determine the status of the Program/Erase operation. Refer to Write Operation Status on page 47 for further information. While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt will be ignored as only an erase operation can covert a 0 to a 1. For example: Old Data = 0011 New Data = 0101 Result = 0001 Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/Erase Suspend commands. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a Program/Erase operation is in progress. A hardware reset and/or power removal immediately terminates the Program/Erase operation and the Program/Erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Write Buffer Programming on page 36 when using the write buffer. 34 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 7.7.1 Single Word Programming Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 12.1 on page 85 for the required bus cycles and Figure 7.3 for the flowchart. When the Embedded Program algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Figure 7.3 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Data to Address: PA, PD Program Address (PA), Program Data (PD) Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Busy? No Yes Polling Status = completed No Yes Error condition (Exceeded Timing Limits) Operation successfully completed Operation failed September 28, 2007 S29WS-P_00_A11 S29WS-P 35 Data Sheet Software Functions and Sample Code Table 7.35 Single Word Program (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note: Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */ 7.7.2 Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the system writes the number of word locations minus 1 that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address must be the least significant address. All subsequent addresses and write buffer data must be in sequential order. The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/data pairs do no match the word count, the program buffer to flash command is ignored. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command will be programmed into the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then go busy. The Data Bar polling techniques 36 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence is ABORTED in the following ways: Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this condition). Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. Software Functions and Sample Code Table 7.36 Write Buffer Program (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N–1)h Program Address Program Address Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h Notes: 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. September 28, 2007 S29WS-P_00_A11 S29WS-P 37 Data Sheet The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* A write buffer begins at addresses evenly divisible */ /* by 0x20. UINT16 i; */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i For WS128 = 2244h, WS256 = 2242h, WS512 = 223Dh. (BA) + 0Fh ----> For WS064/128/256/512 = 2200h 11. The data is 0000h for an unlocked sector and 0001h for a locked sector 12. See Table 7.32, Autoselect Addresses on page 32. 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address. 16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address. 17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 18. Write Buffer Programming can be initiated after Unlock Bypass Entry. 19. Data is always output at the rising edge of clock. 20. Must be the lowest address. 21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings 86 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 12.2 Sector Protection Commands (Sheet 1 of 2) Bus Cycles (Note 1 - 6) Cycles First Addr 3 4 1 4 3 2 1 2 3 555 555 SA 555 555 XX 00 XX 555 Data (10) AA AA data AA AA A0 data 90 AA XX 2AA 00/ Program (9) Password 2 XX A0 01/ 02/ 03 Read Password (10) Unlock (9) Protection Command Set Exit Non-Volatile Sector Protection Command Set Entry (5) Program PPB All Erase (8) Status Read Non-Volatile Sector Protection Command Set Exit (7) Global Volatile Sector Protection Freeze Command Set Entry (5) Set PPB Lock Bit Status Read Global Volatile Sector Protection Freeze Command Set Exit (7) Volatile Sector Protection Command Set Entry (5) Set DYB Clear Status Read Volatile Sector Protection Command Set Exit (7) 1 2 XX XX RD(0) 90 XX 00 (BA) 555 4 7 2 00 00 XX PWD 0 25 90 01 00 XX 00 55 PWD 0/ 1/ 2/ 3/ PWD 1 03 00 (BA) 555 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 00 29 555 60 2AA 2AA 00 55 55 data 555 555 90 40 XX 00 Second Addr 2AA 2AA Data( (10) 55 55 Third Addr 555 555 Data( (10) 88 A0 PA PD Fourth Addr Data( (10) Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10) Command Sequence (Notes) Entry (5) Program Secured Silicon Sector Read Exit (7) Register Command Set Entry (5) Register Bits Program (6) Lock Register Register Bits Read Register Command Set Exit (7) Protection Command Set Entry 3 555 AA 2AA (BA) SA XX 55 C0 2 2 1 XX XX (BA) SA XX A0 80 RD(0) 00 30 2 90 XX 00 3 2 555 XX AA A0 2AA XX 55 00 555 50 3 2 2 1 2 555 XX XX (BA) SA XX AA A0 A0 RD(0) 90 2AA (BA) SA (BA) SA 55 00 01 E0 XX 00 September 28, 2007 S29WS-P_00_A11 S29WS-P 87 Data Sheet Table 12.2 Sector Protection Commands (Sheet 2 of 2) Bus Cycles (Note 1 - 6) Cycles First Addr 2 2 2 1 4 1 555 555 555 RA SA SA Data (10) A0 80 80 RD 25 29 SA WC PA PD WBL PD Second Addr PA SA 555 Data( (10) Data 30 10 Third Addr Data( (10) Fourth Addr Data( (10) Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10) Command Sequence (Notes) Program Sector Erase Chip Erase Accelerated Asynchronous Read Write to Buffer Program Buffer to Flash Legend X = Don’t care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address: WS128P = A22–A14, WS256P = 23–A14 BA = Bank Address: WS128P = A22-A20, and A19; WS256P = A23-A20 CR = Configuration Register data bits D15–D0 PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password. PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See Table 7.1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS512P only. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure. 9. Entire two bus-cycle sequence must be entered for each portion of the password. 10. Full address range is required for reading password. 88 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 12.1 Common Flash Memory Interface The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12.3–12.6 within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write CFI entry command */ /* write cfi exit command */ For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01). Please contact your sales office for copies of these documents. Table 12.3 CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string QRY Description Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 12.4 System Interface String Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0005h 0009h 000Ah 0000h 0003h 0003h 0003h 0000h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical Program Time per single word write 2N µs (e.g. 30us) Typical Program Time using buffer 2N µs (e.g. 300us) (00h = not supported) Typical time for sector erase 2N ms Typical time for full chip erase 2N ms (00h = not supported) Max. Program Time per single word [2N times typical value] Max. Program Time using buffer [2N times typical value] Max. time for sector erase [2N times typical value] Max. time for full chip erase [2N times typical value] (00h = not supported) Description September 28, 2007 S29WS-P_00_A11 S29WS-P 89 Data Sheet Table 12.5 Device Geometry Definition Addresses 27h 28h 29h 2Ah 2Bh 2Ch Data 0018h (WS128P) 0019h (WS256P) 001Ah (WS512P) 0001h 0000h 0006h 0000h 0003h Device Size = 2N byte Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] [upper byte] (00h = not supported) Max. number of bytes in multi-byte buffer write = 2N [lower byte] [upper byte] (00h = not supported) Number of Erase Block Regions within device 01h = Uniform Sector; 02h = Boot + Uniform; 03h = Boot + Uniform + Boot Erase Block Region 1 Information (Small Sector Section) 2Dh 2Eh 2Fh 30h 0003h 0000h 0080h 0000h [lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 2 Information (Large Sector Section) 31h 007Dh (WS128P) 00FDh (WS256P) 00FDh (WS512P) 0001h 0000h 0002h [lower byte] - Number of sectors. Description 32h 33h 34h [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 3 Information (Small Sector Section) 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 0003h 0000h 0080h 0000h 0000h 0000h 0000h 0000h [lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors ... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 4 Information 90 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet Table 12.6 Primary Vendor-Specific Extended Query (Sheet 1 of 2) Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0034h Query-unique ASCII string PRI Major CFI version number, ASCII Minor CFI version number, ASCII Address Sensitive Unlock (Bits 1-0) 00b = Required, 01b = Not Required Silicon Technology (Bits 5-2) 0011b = 130nm; 0100b = 110nm; 0101b = 90nm 001010b = 000Ah Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protection per Group 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08h = Advanced Sector Protection; 07h = New Sector Protection Scheme Simultaneous Operation Number of Sectors in all banks except boot bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Write Protect Function 00h = No Boot, 01h = Dual Boot, 02h = Bottom Boot, 03h = Top Boot Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns (e.g. 10us => n=14) Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns (e.g. 10us => n=14) Erase Suspend Time-out Maximum 2N µs Program Suspend Time-out Maximum 2N µs Bank Organization: X = Number of banks Description 45h 0101b 46h 47h 48h 49h 0002h 0001h 0000h 0008h 07Bh (WS128P) 0F3h (WS256P) 1E3h (WS512P) 0001h 0002h 0085h 4Ah 4Bh 4Ch 4Dh 4Eh 0095h 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 0001h 0001h 0001h 0008h 0014h 0014h 0005h 0005h 0010h 0007h (WS064P) 000Bh (WS128P) 0013h (WS256P) 0023h (WS512P) 0004h (WS064P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0004h (WS064P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 58h Bank 0 Region Information. X = Number of sectors in bank 59h Bank 1 Region Information. X = Number of sectors in bank 5Ah Bank 2 Region Information. X = Number of sectors in bank 5Bh Bank 3 Region Information. X = Number of sectors in bank September 28, 2007 S29WS-P_00_A11 S29WS-P 91 Data Sheet Table 12.6 Primary Vendor-Specific Extended Query (Sheet 2 of 2) Addresses 5Ch Data 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 64h 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) 0020h (WS512P) 000Bh (WS128P) 0013h (WS256P) 0023h (WS512P) Bank 12 Region Information. X = Number of sectors in bank Description Bank 4 Region Information. X = Number of sectors in bank 5Dh Bank 5 Region Information. X = Number of sectors in bank 5Eh Bank 6 Region Information. X = Number of sectors in bank 5Fh Bank 7 Region Information. X = Number of sectors in bank 60h Bank 8 Region Information. X = Number of sectors in bank 61h Bank 9 Region Information. X = Number of sectors in bank 62h Bank 10 Region Information. X = Number of sectors in bank 63h Bank 11 Region Information. X = Number of sectors in bank 65h Bank 13 Region Information. X = Number of sectors in bank 66h Bank 14 Region Information. X = Number of sectors in bank 67h Bank 15 Region Information. X = Number of sectors in bank 92 S29WS-P S29WS-P_00_A11 September 28, 2007 Data Sheet 13. Revision History Section Revision A6 (November 3, 2006) Features Switching Waveforms Timing Diagrams Revision A7 (November 8, 2006) Features Erase/Program Timing CMOS Compatible Revision A8 (March 9, 2007) Asynchronous Mode Read Changed tCR to tRDY in figures 11.9 through 11.12 Revised Device Geometry table: • Changed WS512P data to 00FDh • Address 32h - Data changed to 001h • Address 33h - Data changed to 000h • Address 34h - Data changed to 002h Description Removed Zero Hold mode Revised VCC Power-up diagram Changed tCR to tRDY in figure 11.7 and figure 11.8 Updated Effective Write Buffer Programming Per Word tESL changed to Max tPSL changed to Max Removed Note 2 from table. Common Flash Memory Interface Revised CFI table: removed Uniform Bottom, Uniform Top, and All sectors for Address 4Fh DC Characteristics Revision A9 (March 28, 2007) DC Characteristics Synchronous/Burst Read Asynchronous Mode Read Revision A10 (April 20, 2007) Removed wait state below 14 MHz, wait state 2 AC Characteristics Added additional wait state to all wait state frequency in table 11.4 Added Continuous Burst Mode Synchronous Wait State Requirement table Revised Burst Access Time to (WS-1) * tCK + (tBACC) Revision A11 (September 28, 2007) Data Sheet Status Global Latency Configuration Registers AC Characteristics DC Characteristics Changed to Production Changed all 108 MHz to 104 MHz Added 10 wait state and 11 wait state latency tables Added two more configurations to CR0.11 for 10th and 11th rising CLK edge Revised tCES to 6 ns Revised tAVD to tCLK Changed description of ICC2 to VCC Active Program/Erase Current Change descritpion of ICC5 to VCC Active Current (Read while Program/Erase) Revised: tERS to 40 ns Erase/Program Timing and Performance tESL to 40 ns tPSL to 40 ns tPRS to 40 ns Output Slew Rate Deleted Programmable Outuput Slew Rate Control section Revised ICCB for 108 MHz frequencies to TBA Revised tRACC to 7.6 ns Revised tAAVDH to 4 ns Revised ICCB Burst table September 28, 2007 S29WS-P_00_A11 S29WS-P 93 Data Sheet Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006-2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 94 S29WS-P S29WS-P_00_A11 September 28, 2007