S30MS01GP25TAW513

S30MS-P ORNANDTMFlash Family S30MS01GP, S30MS512P 1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBit™ Technology Data Sheet (Preliminary) S30MS-P ORNANDTMFlash Family Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S30MS-P_00 Revision A Amendment 7 Issue Date August 4, 2006 Data Sheet (Preliminary) Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. ii S30MS-P ORNANDTMFlash Family S30MS-P_00_A7 August 4, 2006 S30MS-P ORNANDTM Flash Family S30MS01GP, S30MS512P 1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBit™ Technology Data Sheet (Preliminary) Distinctive Characteristics Single Power Supply Operation – 1.8 volt read, erase, and program operations – VCC = 1.7 to 1.95V Compatibility with NAND Flash I/O – Provides pinout and command set compatibility with single-power supply NAND flash Manufactured on 90 nm MirrorBitTM Process Technology Bus widths - x8 and x16 Page Size – Full Page Read 2K + 64 Byte – Partial Page Read 512 + 16 Byte High-Performance Cache Register – Cache Register matches page size to improve programming throughput 100,000 Program/Erase Cycles per Sector Typical 10-Year Data Retention Typical Operating Temperature Ranges – Wireless (-25°C to +85°C) Block (erase unit) Architecture – Number of Blocks 1Gb: 1K blocks 512Mb: 512 blocks – Block Size 128K + 4K Byte Package options – 48-pin TSOP – 137-ball FBGA MCP Compatible 100% Valid Blocks Performance Characteristics Read Access Times (Maximum) Full Page Random Access Partial Page Random Access Serial Read 25 µs 8 µs 25ns Read Current Erase Current Program Current Standby Current Current Consumption (typical) 40 mA 60 mA 60 mA 10 uA Read, Program and Erase Performance (typical) x8 Program Erase Full Page Read Partial Page Read Legend: b = bit, B = Byte, K = 1024, M = 1048576 2.3 MB/s 2.7 MB/s 26.7 MB/s 24.3 MB/s x16 2.4 MB/s 2.7 MB/s 40.1 MB/s 34.9 MB/s Publication Number S30MS-P_00 Revision A Amendment 7 Issue Date August 4, 2006 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Data Sheet (Preliminary) Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. 2. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 137-Ball MS01GP MCP-Compatible FBGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 MS01GP and MS512P 48-Pin TSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 VBP137—137-Ball Fine Pitch Ball Grid Array (FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 48-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Names and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 13 13 14 14 15 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 ID Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Schematic Cell Layout and Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operation Mode: Logic and Command Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Page Duplicate Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 28 29 30 30 30 32 13. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13.1 Power On/Off Sequence and Power-On Read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13.2 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14. Tables Table 9.1 Table 9.2 Table 9.3 ID Byte Settings Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2 S30MS-P ORNANDTM Flash Family S30MS-P_00_A7 August 4, 2006 Data Sheet (Preliminary) Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 11.1 Table 11.2 Table 11.3 Table 12.1 Table 12.2 Memory Addressing Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 (1Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 (512Mb) x8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 (1Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 (512) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read Mode Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Page Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Status Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figures Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 10.1 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Command Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Column Address Change in Read Cycle Timing Diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . Column Address Change in Read Cycle Timing Diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Program Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Read Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Column Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Input Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read Timing Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command During Operations Other Than Program, Erase, or Read . . . . . . . . Status Read Command (70h) Input After a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Auto-read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RY/BY#: Termination for the Ready/Busy Pin (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . WP# Signal—Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 17 17 18 18 19 19 20 20 21 21 23 26 27 28 28 29 30 30 30 31 31 32 32 32 32 33 33 34 34 35 36 August 4, 2006 S30MS-P_00_A7 S30MS-P ORNANDTM Flash Family 3 Data Sheet (Preliminary) 1. General Description The S30MS-P is a 1.8V single voltage flash memory product manufactured using 90 nm MirrorBit™ technology. The S30MS01GP is a 1Gb device, organized as 64M Words or 128MB. The S30MS512P is a 512Mb device, organized as 32M Words or 64MB. The S30MS-P family of devices offer advantages such as: Fast write and sustained write speed suitable for data storage applications Fast read speed and reliability suitable for demanding code storage applications Proven MirrorBit™ technology The devices are offered in a 48-pin TSOP, or FBGA MCP-compatible packages. Each device has separate chip enable (CE#) controls for the FBGA package. The S30MS-P is a byte/word serial-type memory device that utilizes the I/O pins for both address and data input/output, as well as for command input. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state disks, pictures storage for still cameras, cellular phones, and other systems that require high-density non-volatile data storage. Typical application requirements are shown in the table below with reference to the ORNAND capabilities. Application 2G Network 3G Network 3.5G Network (HSPDA) Full Speed USB MP3 Playback MPEG2 (H.262) MPEG4 (H.264) WiMax Minimum Requirements 14.4 Kbps (1.8 KB/sec) 2 Mbps (250 KB/sec) 2.5 MB/sec 1.5 MB/sec 320 Kbps (40 KB/sec) 3 MB/sec 1 MB/sec 0.25 MB/sec Spansion ORNAND The devices include the following features: Automatic page 0 read, allows access of the data in page 0 without command and address input of read command after power-up Chip Enable Don't Care support for direct connection with microcontrollers Compatible with NAND Flash command set. Commands are written to the device using standard microprocessor write timing. Write cycles provide commands, addresses and data Initiation of program and erase functions through command sequences. Once a program or erase operation begins, the host system should only poll for status or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete Manufactured using MirrorBit™ flash technology resulting in the highest levels of quality, reliability, and cost effectiveness 4 S30MS-P ORNANDTM Flash Family S30MS-P_00_A7 August 4, 2006 Data Sheet (Preliminary) 2. 2.1 Connection Diagrams 137-Ball MS01GP MCP-Compatible FBGA Pinout A1 RFU A2 RFU A3 RFU A4 RFU A5 RFU A6 RFU A7 RFU A8 RFU A9 RFU A10 RFU B1 RFU B2 RFU B3 RFU B4 RFU B5 RFU B6 RFU B7 RFU B8 RFU B9 DNU B10 RFU C1 RFU C2 RFU C3 VSS C4 RFU C5 RFU C6 RFU C7 N-PRE C8 N-ALE C9 N-CLE C10 RFU Legend D1 RFU D2 RFU D3 RFU D4 RFU D5 RFU D6 RFU D7 RFU D8 RFU D9 N1-CE# D10 RFU RFU E1 RFU E2 RFU E3 RFU E4 RFU E5 RFU E6 DNU E7 RFU E8 RFU E9 RFU E10 RFU Flash Shared F1 RFU F2 RFU F3 RFU F4 RFU F5 RY/BY# F6 RFU F7 RFU F8 RFU F9 RFU F10 RFU ORNAND Flash G1 RFU G2 RFU G3 RFU G4 RFU G6 RFU G7 RFU G8 RFU G9 RFU G10 RFU Do Not Use H1 RFU H2 RFU H3 VSS H4 DQ1 H7 DQ6 H8 RFU H9 RFU H10 RFU J1 RFU J2 RFU J3 RFU J4 DQ9 J5 DQ3 J6 DQ4 J7 DQ13 J8 DQ15 J9 DNU J10 RFU K1 RFU L1 RFU K2 DNU L2 N-VCC K3 DQ0 L3 DQ8 K4 DQ10 L4 DQ2 K5 RFU L5 DQ11 K6 N-VCC L6 RFU K7 DQ12 L7 DQ5 K8 DQ7 L8 DQ14 K9 VSS L9 N-WP# K10 RFU L10 RFU M1 RFU N1 N-WE# P1 RFU M2 RFU N2 RFU P2 RFU M3 RFU N3 RFU P3 RFU M4 VSS N4 RFU P4 RFU M5 RFU N5 RFU P5 RFU M6 N2-CE# N6 RFU P6 RFU M7 DNU N7 RFU P7 RFU M8 RFU N8 RFU P8 RFU M9 RFU N9 RFU P9 DNU M10 RFU N10 N-RE# P10 RFU August 4, 2006 S30MS-P_00_A7 S30MS-P ORNANDTM Flash Family 5 Data Sheet (Preliminary) 2.2 MS01GP and MS512P 48-Pin TSOP Pinout TSOP-48 X16 N.C N.C N.C N.C N.C N.C RY/BY# RE# CE# N.C N.C VCC VSS N.C N.C CLE ALE WE# WP# N.C N.C N.C N.C N.C X8 N.C N.C N.C N.C N.C N.C RY/BY# RE# CE# N.C N.C VCC VSS N.C N.C CLE ALE WE# WP# N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 X8 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C PRE VCC VSS N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C X16 VSS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 N.C PRE VCC N.C N.C N.C I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 VSS 6 S30MS-P ORNANDTM Flash Family S30MS-P_00_A7 August 4, 2006 Data Sheet (Preliminary) 3. 3.1 Physical Dimensions VBP137—137-Ball Fine Pitch Ball Grid Array (FBGA) D 0.15 C (2X) 10 9 8 7 6 5 4 3 2 1 A e D1 SE 7 E1 E e P NM LK J HGF E DCB A PIN A1 CORNER 9 INDEX MARK B 7 PIN A1 CORNER TOP VIEW 0.15 C (2X) SD BOTTOM VIEW A A2 A1 6 0.10 C SIDE VIEW b M CAB MC C 0.08 C 137X 0.15 0.08 NOTES: PACKAGE JEDEC VBP 137 N/A 13.00 mm x 11.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N φb e SD / SE 0.35 MIN --0.17 0.60 NOM ------13.00 BSC. 11.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.40 BSC. G5,H5,H6 0.45 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3549 \ 16-038.25 \ 2.16.6 August 4, 2006 S30MS-P_00_A7 S30MS-P ORNANDTM Flash Family 7 Data Sheet (Preliminary) 3.2 48-Pin TSOP 2X STANDARD PIN OUT (TOP VIEW) 2 1 N 0.10 2X (N/2 TIPS) 2X 0.10 A2 0.10 REVERSE PIN OUT (TOP VIEW) 3 1 N A SEE DETAIL B B E5 N 2 N +1 2 e 9 A1 C SEATING PLANE 0.08MM (0.0031") M C A-B S N 2 N +1 2 D1 D 0.25 2X (N/2 TIPS) 5 4 B A B SEE DETAIL A b 6 7 WITH PLATING 7 (c) c1 b1 SECTION B-B R (c) GAUGE PLANE BASE METAL e/2 PARALLEL TO SEATING PLANE θ° C 0.25MM (0.0098") BSC X X = A OR B L DETAIL A DETAIL B Package Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MIN TS/TSR 048 MO-142 (D) DD MAX 1.20 0.15 0.05 1.00 0.95 1.05 0.20 0.23 0.17 0.22 0.17 0.27 0.10 0.16 0.10 0.21 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.50 0.70 0.60 0˚ 8˚ 0.08 0.20 48 NOM NOTES: 1 2 3 4 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3355 \ 16-038.10c 5 6 7 8 9 8 S30MS-P ORNANDTM Flash Family S30MS-P_00_A7 August 4, 2006 Data Sheet (Preliminary) 4. 4.1 Pin Names and Descriptions Pin Names and Functions Pin Name I/O0 to I/O15 CLE ALE CE#, CE1#, CE2# RE# WE# WP# PRE RY/BY# VCC VSS N.C. Pin Function Data Input/Output Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Power on Read Enable Ready/Busy Output Power Ground No Connection 4.2 Pin Descriptions The device is a byte/word serial access memory that utilizes time-sharing input of address information. The device pin-outs are configured as shown in 137-Ball MS01GP MCP-Compatible FBGA Pinout on page 5. Pin CLE Description Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE# signal while CE# is low and CLE is High. Address Latch Enable: The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low and ALE is High. Input data is latched if CE# is low and ALE is Low. Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE# signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive during the Page Buffer write and Page Buffer load of the array data. The 2Gb device has two chip enable pins: CE1# and CE2# (one per die). Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#. The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O Port: The I/O0 to I/O7 pins are used as a port for transferring address, command, and input/output data to and from the device. I/O Port: The I/O8 to I/O15 pins are used as a port for transferring input/output data to and from the device in x16 mode only. I/O8 to I/O15 pins must be low level during address and command input. Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy:The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY# signal is in Busy state (RY/BY# = L) during the Program, Erase, and Read operations and return to Ready state (RY/BY# = H) after completion of the operation. The output buffer for this signal is an open drain. Power-on Read Enable: The PRE controls auto read operation executed during power-on. The power-on autoread is enabled when PRE pin in tied to VCC. Ground: VSS is the Ground. No Connection: Lead is not internally connected. ALE CE#, CE1#, CE2# WE# RE# I/O0 to I/O7 I/O8 to I/O15 WP# RY/BY# PRE VSS N.C August 4, 2006 S30MS-P_00_A7 S30MS-P ORNANDTM Flash Family 9 Data Sheet (Preliminary) 5. Block Diagram VCC VSS X-Decoder RY/BY# 2Gb: (2048M + 64M) bit 1Gb: (1024M + 32M) bit 512 Mb: (512M + 16M) bit Flash Array Address Register & Decoders Data Register & S/A Cache Register Y-Decoder Command Command Register I/O Buffers & Latches VCC VSS I/00 CE# RE# WE# Control Logic & High Voltage Generator Global Buffers Output Driver I/O7 or I/O15 CLE ALE PRE WP# 6. Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Storage Temperature Operating Temperature Temperature under bias Short circuit current Symbol VIN/OUT VCC TSTG TOPR TBIAS IOS Rating -0.5 to Vcc + 0.5 V -0.5 to + 2.5 -65 to +150 0 to +70 (Commercial) -40 to +85 (Industrial) -25 to +85 (Wireless) -65 to 125 5 o o Unit C C C o mA Notes: 1. Minimum DC voltage is -0.6v on input/output pins. During transitions, this level may undershoot to -2.0v for periods