S71PL127J40BAW0Z2

S71PL-J Based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static RAM/Pseudo Static RAM Data Sheet ADVANCE INFORMATION Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Publication Number S71PL-J_00 Revision B Amendment 3 Issue Date March 17, 2006 Advance Information Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 S71PL-J Based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static RAM/Pseudo Static RAM Data Sheet ADVANCE INFORMATION Distinctive Characteristics MCP Features Power supply voltage of 2.7 V to 3.1 V High performance — 65 ns (65 ns Flash, 70 ns pSRAM) Packages — 7 x 9 x 1.2mm 56 ball FBGA — 8 x 11.6 x 1.2mm 64 ball FBGA — 8 x 11.6 x 1.4mm 84 ball FBGA Operating Temperature — –25°C to +85°C — –40°C to +85°C General Description The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or more S29PL (Simultaneous Read/Write) Flash memory die pSRAM or SRAM (See “Referenced Data Sheets” on page 2) The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2 is used to access the second Flash and no extra address lines are required. The products covered by this document are listed in the table below: Flash Memory Density 32Mb 4 Mb 8 Mb pSRAM Density 16 Mb 32 Mb 64 Mb S71PL032J40 S71PL032J80 S71PL032JA0 S71PL064J80 S71PL064JA0 S71PL064JB0 S71PL127JB0 S71PL127JC0 Flash Memory Density 32Mb 4 Mb SRAM Density (Note 1) 8 Mb 16 Mb S71PL032J04 S71PL032J08 S71PL064J08 S71PL064J0A 64Mb S71PL254JC0 64Mb 128Mb (Note 2) 256Mb (Note 2) Notes: 1. Not recommended for new designs; use pSRAM based MCPs instead. 2. Not recommended for new designs: use S71PL127N and S71PL256N instead. Publication Number S71PL-J_00 Revision B Amendment 3 Issue Date March 17, 2006 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Advance Information For detailed specifications, please refer to the individual data sheets listed in the following table. Referenced Data Sheets Document S29PL-J pSRAM Type 1 pSRAM Type 2 8 Mb pSRAM Type 3 16 Mb pSRAM Type 3 pSRAM Type 4 pSRAM Type 5 pSRAM Type 6 pSRAM Type 7 4 Mb/8 Mb SRAM Type 1 16 Mb SRAM Type 1 SRAM Type 4 Publication Identification Number (PID) S29PL-J_M0 psram_12 psram_15 psram_25 psram_06 psram_18 psram_21 psram_14 psram_13 sram_02 sram_06 sram_07 2 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information Product Selector Guide 32Mb Flash Memory Device-Model# S71PL032J04-0B S71PL032J04-0K S71PL032J40-0K S71PL032J08-0B S71PL032J80-0F S71PL032J80-Q7 S71PL032J80-QF S71PL032JA0-0K S71PL032JA0-QF S71PL032JA0-0Z Flash Access time (ns) 65 65 65 65 65 65 65 65 65 65 (p)SRAM density 4M SRAM 4M SRAM 4M pSRAM 8M SRAM 8M pSRAM 8M pSRAM 8M pSRAM 16Mb pSRAM 16Mb pSRAM 16M pSRAM (p)SRAM Access time (ns) pSRAM type 70 70 70 70 70 70 70 70 70 70 SRAM1 SRAM4 pSRAM4 SRAM1 pSRAM5 pSRAM1 pSRAM3 pSRAM1 pSRAM3 pSRAM7 Package TSC056 TSC056 TLC056 TSC056 TSC056 TSC056 TSC056 TSC056 TSC056 TLC056 64Mb Flash Memory Device-Model# S71PL064J08-0B S71PL064J80-0K S71PL064J0A-0S S71PL064JA0-0Z S71PL064JA0-0B S71PL064JA0-07 S71PL064JA0-0P S71PL064JB0-QB S71PL064JB0-0U Flash Access time (ns) 65 65 65 65 65 65 65 65 65 (p)SRAM density 8M SRAM 8M pSRAM 16M SRAM 16M pSRAM 16M pSRAM 16M pSRAM 16M pSRAM 32M pSRAM 32M pSRAM (p)SRAM Access time (ns) 70 70 70 70 70 70 70 70 70 (p)SRAM type SRAM1 pSRAM1 SRAM1 pSRAM7 pSRAM3 pSRAM1 pSRAM7 pSRAM2 pSRAM6 Package TLC056 TSC056 TLC056 TLC056 TLC056 TLC056 TLC056 TLC056 TLC056 March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 3 Advance Information 128Mb Flash Memory (Not recommended for new designs; use S71PL127N instead) Device-Model# S71PL127JB0-9Z S71PL127JB0-9U S71PL127JB0-9B S71PL127JC0-9B S71PL127JC0-9Z S71PL127JC0-9U Flash Access time (ns) 65 65 65 65 65 65 pSRAM density 32M pSRAM 32M pSRAM 32M pSRAM 64M pSRAM 64M pSRAM 64M pSRAM pSRAM Access time (ns) 70 70 70 70 70 70 pSRAM type pSRAM7 pSRAM6 pSRAM2 pSRAM2 pSRAM7 pSRAM6 Package TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 256Mb Flash Memory (2xS29PL127J) (Not recommended for new designs: use S71PL256N instead) Device-Model# S71PL254JC0-TB S71PL254JC0-TZ Flash Access time (ns) 65 65 pSRAM density 64M pSRAM 64M pSRAM pSRAM Access time (ns) 70 70 pSRAM type pSRAM2 pSRAM7 Package FTA084 FTA084 4 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information MCP Block Diagram VCCf VCC CE#f1 WP#/ACC RESET# Flash-only Address Shared Address OE# WE# VSS RY/BY# Flash 2 (Note 2) Flash 1 CE#f2 (Note 1) VCCS DQ15 to DQ0 VCC pSRAM/SRAM IO15-IO0 CE#s UB#s LB#s CE2 CE# UB# LB# Notes: 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J. March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 5 Advance Information Connection Diagram (S71PL032J) 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A7 B1 A3 C1 A2 D1 A1 E1 A0 F1 CE1#f G1 CE1#s B2 A6 C2 A5 D2 A4 E2 VSS F2 OE# G2 DQ0 H2 DQ8 A3 LB# B3 UB# C3 A18 D3 A17 E3 DQ1 F3 DQ9 G3 DQ10 H3 DQ2 A4 WP/ACC B4 RST#f C4 RY/BY# A5 WE# B5 CE2s C5 A20 A6 A8 B6 A19 C6 A9 D6 A10 E6 DQ6 A7 A11 B7 A12 C7 A13 D7 A14 E7 RFU F7 DQ15 G7 DQ7 H7 DQ14 B8 A15 C8 RFU D8 RFU E8 A16 F8 RFU G8 VSS Legend Shared (Note 1) Flash only RAM only F4 DQ3 G4 VCCf H4 DQ11 F5 DQ4 G5 VCCs H5 RFU F6 DQ13 G6 DQ12 H6 DQ5 Reserved for Future Use Notes: 1. May be shared depending on density. — A19 is shared for the 16M pSRAM configuration. — A18 is shared for the 8M pSRAM and above configurations. 2. Connecting all VCC and VSS balls to VCC and VSS is recommended. MCP S71PL032JA0 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J04 Flash-only Addresses A20 A20-A19 A20-A19 A20-A18 A20-A18 Shared Addresses A19-A0 A18-A0 A18-A0 A17-A0 A17-A0 6 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information Connection Diagram (S71PL064J) 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A7 B1 A3 C1 A2 D1 A1 E1 A0 F1 CE1#f G1 CE1#s B2 A6 C2 A5 D2 A4 E2 VSS F2 OE# G2 DQ0 H2 DQ8 A3 LB# B3 UB# C3 A18 D3 A17 E3 DQ1 F3 DQ9 G3 DQ10 H3 DQ2 A4 WP/ACC B4 RST#f C4 RY/BY# A5 WE# B5 CE2s C5 A20 A6 A8 B6 A19 C6 A9 D6 A10 E6 DQ6 A7 A11 B7 A12 C7 A13 D7 A14 E7 RFU F7 DQ15 G7 DQ7 H7 DQ14 B8 A15 C8 A21 D8 RFU E8 A16 F8 RFU G8 VSS Legend Shared (Note 1) Flash only RAM only F4 DQ3 G4 VCCf H4 DQ11 F5 DQ4 G5 VCCs H5 RFU F6 DQ13 G6 DQ12 H6 DQ5 Reserved for Future Use Notes: 1. May be shared depending on density. — A20 is shared for the 32M pSRAM configuration. — A19 is shared for the 16M pSRAM and above configurations. — A18 is shared for the 8M pSRAM and above configurations. 2. Connecting all VCC and VSS balls to VCC and VSS is recommended. MCP S71PL064JB0 S71PL064JA0 S71PL064J0A S71PL064J80 S71PL064J08 Flash-only Addresses A21 A21-A20 A21-A20 A21-A19 A21-A19 Shared Addresses A20-A0 A19-A0 A19-A0 A18-A0 A18-A0 March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 7 Advance Information Connection Diagram (S71PL127J) 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 NC B5 RFU C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 B6 RFU C6 WE# C7 A8 C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 D9 A15 A10 NC C4 LB# C5 WP/ACC D5 RST#f E5 RY/BY# Legend D4 UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 D6 CE2s D7 A19 E7 A9 F7 A10 G7 DQ6 Shared (Note 1) E6 A20 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS Flash only RAM only H5 DQ3 J5 VCCf K5 DQ11 L5 RFU* H6 DQ4 H7 DQ13 J7 DQ12 K7 DQ5 Reserved for Future Use J2 CE1#s J6 VCCs K6 RFU L6 RFU M1 NC *See notes below M10 NC Notes: 1. May be shared depending on density. — A21 is shared for the 64M pSRAM configuration. — A20 is shared for the 32M pSRAM and above configurations. 2. A19 is shared for the 16M pSRAM and above configurations. MCP S71PL127JC0 S71PL127JB0 Flash-only Addresses A22 A22-A21 Shared Addresses A21-A0 A20-A0 3. Connecting all VCC and VSS balls to Vcc & Vss is recommended. 4. Ball L5 will be VCCF in the 84-ball density upgrades. Do not connect to VSS or any other signal. 8 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information Connection Diagram (S71PL254J) 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 NC B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f1 B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 RFU B5 CE#F2 C5 WP/ACC D5 RST#f E5 RY/BY# H5 RFU H5 RFU H5 DQ3 J5 VCCf K5 DQ11 L5 VCCf B6 RFU C6 WE# B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15 A10 NC C4 LB# Legend D4 UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU D6 CE2s Shared (Note 1) E6 A20 H6 RFU H6 RFU H6 DQ4 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU M10 NC 2nd Flash Only Flash only RAM only Reserved for Future Use J2 CE1#s K2 RFU L2 RFU M1 NC J6 VCCs K6 RFU L6 RFU Notes: 1. May be shared depending on density. — A21 is shared for the 64M pSRAM configuration. — A20 is shared for the 32M pSRAM configuration. MCP S71PL254JC0 Flash-only Addresses A22 Shared Addresses A21-A0 2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 9 Advance Information Pin Description A21–A0 DQ15–DQ0 CE1#f CE#f2 CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf = = = = = = = = = = = = = = 22 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 2 (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash 1) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low (Flash 1) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally VCCps VSS NC = = = Logic Symbol 22 A21–A0 16 CE1#f CE2#f CE1#ps CE2ps OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15–DQ0 10 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information Ordering Information The order number is formed by a valid combinations of the following: S71PL 127 J B0 BA W 9 Z 0 PACKING TYPE 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER See the Valid Combinations table. PACKAGE MODIFIER 0 = 7 x 9mm, 1.2mm height, 56 balls (TLC056 or TSC065) 9 = 8 x 11.6mm, 1.2mm height, 64 balls (TLA064 or TSB064) T = 8 x 11.6mm, 1.4mm height, 84 balls (FTA084) TEMPERATURE RANGE W = Wireless (-25°C to +85°C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM C0 = B0 = A0 = 80 = 40 = 0A = 08 = 04 = DENSITY 64Mb pSRAM 32Mb pSRAM 16Mb pSRAM 8Mb pSRAM 4Mb pSRAM 16Mb pSRAM 8Mb SRAM 4Mb SRAM PROCESS TECHNOLOGY J = 110 nm, Floating Gate Technology FLASH DENSITY 254 = 256Mb 127 = 128Mb 064 = 64Mb 032 = 32Mb PRODUCT FAMILY S71PL Multi-chip Product (MCP) 3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 11 Advance Information S71PL032J Valid Combinations Base Ordering Part Number S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J80 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J80 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 BFW BAW Package & Temperature Package Modifier/ Model Number 0B 0K 0K 0F 0B Q7 QF 07 QF 0Z 0B 0K 0K 0F 0B Q7 QF 07 QF 0Z S71PL064J Valid Combinations Base Ordering Part Number S71PL064J08 S71PL064J80 S71PL064J0A S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 S71PL064J08 S71PL064J80 S71Pl064J0A S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 BFW BAW Package & Temperature Package Modifier/ Model Number 0B 0K 0S 0B 07 0P QB 0U 0B 0K 0S 0B 07 0P QB 0U 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns) 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) SRAM2 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70 SRAM2 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70 (p)SRAM Type/ Access Time (ns) SRAM1 / 70 pSRAM1 /70 SRAM1 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM2 / 70 pSRAM6 / 70 SRAM1 / 70 pSRAM1 /70 SRAM1 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM2 / 70 pSRAM6 / 70 Package Marking (Note 2) (Note 2) Package Marking (Note 2) (Note 2) Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 12 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information S71PL127J Valid Combinations Base Ordering Part Number S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 S71PL127JB0 BFW BAW Package & Temperature Package Modifier/Model Number 9Z 9U 9B 9Z 9U 9B 9Z 9U 9B 9Z 9U 9B 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns) (p)SRAM Type/ Access Time Package Marking (ns) pSRAM7 / 70 pSRAM6 /70 pSRAM2 /70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 /70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70 (Note 2) (Note 2) Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S71PL254J Valid Combinations Base Ordering Part Number S71PL254JC0 S71PL254JC0 S71PL254JC0 S71PL254JC0 Package & Temperature BAW Model Number TB TZ TB TZ Packing Type 0, 2, 3 (Note1) Speed Options (ns) 65 (p)SRAM Type/Access Time (ns) pSRAM2 / 70 pSRAM7 / 70 pSRAM2 / 70 pSRAM7 / 70 Package Marking (Note 2) BFW 0, 2, 3 (Note1) 65 (Note 2) Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 13 Advance Information Physical Dimensions TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package D 0.15 C (2X) 8 7 6 A D1 eD SE 7 E eE 5 4 3 2 1 E1 INDEX MARK PIN A1 CORNER 10 H G F E D CB A B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 6 C 0.08 C SIDE VIEW b 56X 0.15 M C A B 0.08 M C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TLC 056 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.20 0.81 NOM ------9.00 BSC. 7.00 BSC. 5.60 BSC. 5.60 BSC. 8 8 56 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A1,A8,D4,D5,E4,E5,H1,H8 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3348 \ 16-038.22a 14 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package D 0.15 C (2X) 8 7 6 A D1 eD SE 7 E eE 5 4 3 2 1 E1 INDEX MARK PIN A1 CORNER 10 H G F E D CB A B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 6 0.20 C C 0.08 C SIDE VIEW b MCAB MC 56X 0.15 0.08 NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TSC 056 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.17 0.81 NOM ------9.00 BSC. 7.00 BSC. 5.60 BSC. 5.60 BSC. 8 8 56 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A1,A8,D4,D5,E4,E5,H1,H8 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3427 \ 16-038.22 March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 15 Advance Information TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E1 E eE 6 5 4 3 2 1 L J H G F E D CB A INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 64X 0.15 0.08 0.20 C 6 SIDE VIEW b M C AB MC C 0.08 C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TLA 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3352 \ 16-038.22a 16 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 L J H G F E D CB A E1 INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 64X 0.15 0.08 0.20 C 6 SIDE VIEW b M C AB MC C 0.08 C PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TSB 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --017 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT NOTE NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 7 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10 F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3351 \ 16-038.22a March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 17 Advance Information FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package D 0.15 C (2X) 10 9 8 7 6 5 4 A D1 eD SE 7 E eE INDEX MARK PIN A1 CORNER 10 E1 3 2 1 MLKJ HG F EDC BA B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 6 C 0.08 C SIDE VIEW b 84X 0.15 M C A B 0.08 M C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 FTA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 1.02 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.40 --1.17 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3388 \ 16-038.21a 18 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information MCP Revision Summary Revision A (May 3, 2004) Initial release. Revision A1 (May 6, 2004) MCP Features Corrected the high performance access times. Connection Diagrams Added reference points on all diagrams. Ordering Information Corrected package types. Corrected the description of product family to Page Mode Flash memory. pSRAM Type 1 Corrected the description of the 8Mb device to 512Kb Word x 16-bit. pSRAM Type 6 Corrected the description of the 2Mb device to 128Kb Word x 16-bit. Corrected the description of the 4Mb device to 256Kb Word x 16-bit. Revision A2 (May 11, 2004) General Description Corrected the tables to reflect accurate device configurations. Revision A3 (June 16, 2004) Ordering Information Corrected the Valid Combinations tables to reflect accurate device configurations. SRAM New section added. Revision A4 (July 16, 2004) Global Changes Global Change of FASL to Spansion. Global change to remove space between M and Mb callouts. “32Mb Flash Memory” on page 3 Replaced “S71PL032J08-07” with “S71PL032J08-0B”. Replaced “S71PL032JA0” with “S71PL032JA0-07”. Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056. “64Mb Flash Memory” on page 3 Replaced “S71PL064J08-0K” with “S71PL064J08-0B”. Replaced “S71PL064J08-0P” with “S71PL064J08-0U”. Deleted “S71PL064J80-05” row. Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”. March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 19 Advance Information Replaced “S71PL064JA0-0Z” with Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056. “32Mb Flash Memory” on page 3 Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”. “64Mb Flash Memory” on page 3 Replaced “S71PL032JA0-07” with “S71PL032JA0-0K”. “128Mb Flash Memory” on page 4 Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064. Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”. Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064. Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”. In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”. “256Mb Flash Memory (2xS29PL127J)” on page 4 Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084. Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084. “Connection Diagram (S71PL127J)” on page 12 Updated pins D8, D9, and L5. Added notes 2 and 3 to drawing. “Connection Diagram (S71PL254J)” on page 13 Updated pins D8 and D9. Added Note 2 to drawing. “S71PL032J Valid Combinations” on page 16 Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to “SRAM2” (4 changes made in table). Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to pSRAM3 /70”. Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”. Merged previous place holder with cell above. “S71PL064J Valid Combinations” on page 17 In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/ 70”. In Package Modifier/Model Number changed all instances of “stet” to “07”. Added row to BAW Package and Temperature sections with the following content: S71PL064JB0; 07; 65 (previously inclusive); pSRAM1/70. “S71PL127J Valid Combinations” on page 18 Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4 instances). 20 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006 Advance Information Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70. “S71PL254J Valid Combinations” on page 20 Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70. Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70. “S71PL-J based MCPs” on page 1 Added 254M to Megabit indicator. Added 16 to CMOS indicator. Revision A5 (September 14, 2004) Product Selector Guide Updated the 128Mb Flash Memory table. Valid Combinations Table Updated the S71PL127J Valid Combinations table. Revision A6 (November 22, 2004) Product Selector Guide Updated the 32Mb and 64Mb tables. Valid Combinations Tables Updated the 32Mb and 64Mb combinations. Physical Dimensions Added the TSB064 package. Revision A7 (February 8, 2005) pSRAM Type 7 Updated all information in this section. Revision A8 (April 6, 2005) S29PL-J Flash Updated all information in this section. Revision A9 (May 12, 2005) S71PL-J MCP Added the S71PL064J0A option to cover the inclusion of the 16M SRAM pSRAM Type 2 Added the latest revision for the pSRAM Type 2 SRAM Type 2 Added this module to the S71PL-J MCP Revision A10 (June 22, 2005) S71PL-J MCP Removed 127/16 and 254/32 pSRAM and updated OPN for 64/16SRAM Revision A11 (July 29, 2005) pSRAM Type 7 Updated module March 17, 2006 S71PL-J_00_B3 S71PL-J Based MCPs 21 Advance Information Revision B0 (September 29, 2005) S29PL-J Updated module SRAM Type 1 Updated module Revision B1 (October 25, 2005) pSRAM Module Type 5 Added module Revision B2 (January 25, 2006) Added notices for devices not recommended for new designs Modified the Product Selection Guide Modified the S71PL032J, S71PL064J, S71PL127JValid Combinations tables Revision B3 (March 17, 2006) Modified the stucture of the document. Related data sheets are referenced rather than be embedded. Added data sheet reference table to that effect. Added the SRAM Type 4 option Added the 8Mb pSRAM Type 3 option Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004 – 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners. 22 S71PL-J Based MCPs S71PL-J_00_B3 March 17, 2006