S71PL129JC0BAW9Z0

S71PL129JC0/S71PL129JB0/S71PL129JA0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory with 64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM ADVANCE INFORMATION Distinctive Characteristics MCP Features Power supply voltage of 2.7 to 3.1 volt High performance — 65ns (65ns Flash, 70ns pSRAM) Package — 8 x 11.6 x 1.2 mm 64 ball FBGA Operating Temperature — –25°C to +85°C (Wireless) — –40°C to +85°C (Industrial) Dual CE# Flash memory General Description The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One S29PL129J Flash memory die One 16M, 32M, or 64M pSRAM The products covered by this document are listed in the table below. For details about their specifications, please refer to the individual constituent datasheets for further details. Flash Memory Density 128Mb 64Mb pSRAM Density 32Mb 16Mb S71PL129JC0 S71PL129JB0 S71PL129JA0 Publication Number S71PL129Jxx_00 Revision A Amendment 5 Issue Date December 23, 2004 This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice. Advance Information Product Selector Guide 128 Mb Flash Memory Device-Model# S71PL129JA0-9P S71PL129JB0-9Z S71PL129JB0-9B S71PL129JB0-9U S71PL129JC0-9Z S71PL129JC0-9U pSRAM density 16M pSRAM 32M pSRAM 32M pSRAM 32M pSRAM 64M pSRAM 64M pSRAM Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type 65 65 65 65 65 65 70 70 70 70 70 70 Type 7 Type 7 Type 2 Type 6 Type 7 Type 6 Package TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 2 S71PL129JC0/S71PL129JB0/S71PL129JA0 S71PL129Jxx_00_A5_E December 23, 2004 Advance Information S71PL129JC0/S71PL129JB0/S71PL129JA0 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1 MCP Features ........................................................................................................ 1 Write Protect (WP#) ....................................................................................... 36 Persistent Protection Bit Lock ................................................................... 37 High Voltage Sector Protection ..................................................................... 37 Figure 1. In-System Sector Protection/Sector Unprotection Algorithms........................................................................ 38 General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 128 Mb Flash Memory ..........................................................................................2 Temporary Sector Unprotect ........................................................................ 39 Figure 2. Temporary Sector Unprotect Operation ................... 39 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7 Input/Output Description . . . . . . . . . . . . . . . . . . . 8 Pin Description ......................................................................................................8 Logic Symbol ...........................................................................................................8 Secured Silicon Sector Flash Memory Region ........................................... 39 Factory-Locked Area (64 words) ..............................................................40 Customer-Lockable Area (64 words) ......................................................40 Secured Silicon Sector Protection Bits ....................................................40 Figure 3. Secured Silicon Sector Protect Verify ...................... 41 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11 TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ............................................................................................ 11 Hardware Data Protection ..............................................................................41 Low VCC Write Inhibit .................................................................................41 Write Pulse “Glitch” Protection ................................................................ 41 Logical Inhibit ....................................................................................................41 Power-Up Write Inhibit ................................................................................ 41 S29PL129J for MCP General Description . . . . . . . . . . . . . . . . . . . . . . . . 14 Simultaneous Read/Write Operation with Zero Latency ...................... 14 Page Mode Features ........................................................................................... 14 Standard Flash Memory Features ................................................................... 14 Common Flash Memory Interface (CFI) . . . . . . 42 Table 8. CFI Query Identification String ................................ 42 Table 9. System Interface String ......................................... 43 Table 10. Device Geometry Definition ................................... 43 Table 11. Primary Vendor-Specific Extended Query ................ 43 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45 Reading Array Data ........................................................................................... 45 Reset Command ................................................................................................. 45 Autoselect Command Sequence ....................................................................46 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence ....................................................................................................................46 Word Program Command Sequence ...........................................................46 Unlock Bypass Command Sequence ........................................................ 47 Figure 4. Program Operation ............................................... 48 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19 Table 1. PL129J Device Bus Operations ................................ 19 Requirements for Reading Array Data ......................................................... 19 Random Read (Non-Page Read) ............................................................... 20 Page Mode Read ............................................................................................. 20 Table 2. Page Select .......................................................... 20 Simultaneous Read/Write Operation .......................................................... 20 Writing Commands/Command Sequences ................................................. 21 Accelerated Program Operation ............................................................... 21 Autoselect Functions ..................................................................................... 21 Standby Mode ........................................................................................................21 Automatic Sleep Mode ..................................................................................... 22 RESET#: Hardware Reset Pin ........................................................................ 22 Output Disable Mode ....................................................................................... 22 Table 3. S29PL129J Sector Architecture ............................... 23 Table 4. Secured Silicon Sector Addresses ............................ 29 Chip Erase Command Sequence ...................................................................48 Sector Erase Command Sequence ................................................................49 Figure 5. Erase Operation ................................................... 50 Autoselect Mode ................................................................................................ 29 Table 5. Autoselect Codes for PL129J ................................... 30 Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/ Unprotection ..................................................................... 31 Selecting a Sector Protection Mode ..............................................................32 Table 7. Sector Protection Schemes ..................................... 32 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32 Persistent Sector Protection ...........................................................................32 Password Sector Protection ............................................................................32 WP# Hardware Protection .............................................................................32 Selecting a Sector Protection Mode ..............................................................32 Erase Suspend/Erase Resume Commands ..................................................50 Password Program Command ........................................................................ 51 Password Verify Command .............................................................................. 51 Password Protection Mode Locking Bit Program Command ............... 51 Persistent Sector Protection Mode Locking Bit Program Command 52 Secured Silicon Sector Protection Bit Program Command .................. 52 PPB Lock Bit Set Command ............................................................................ 52 DYB Write Command ...................................................................................... 52 Password Unlock Command .......................................................................... 52 PPB Program Command .................................................................................. 53 All PPB Erase Command .................................................................................. 53 DYB Write Command ...................................................................................... 53 PPB Lock Bit Set Command ............................................................................ 53 Command ............................................................................................................. 54 Command Definitions Tables ......................................................................... 54 Table 12. Memory Array Command Definitions ...................... 54 Table 13. Sector Protection Command Definitions .................. 55 Write Operation Status . . . . . . . . . . . . . . . . . . . . 56 DQ7: Data# Polling ............................................................................................ 56 Figure 6. Data# Polling Algorithm ........................................ 58 Persistent Sector Protection . . . . . . . . . . . . . . . . 33 Persistent Protection Bit (PPB) .......................................................................33 Persistent Protection Bit Lock (PPB Lock) .................................................33 Dynamic Protection Bit (DYB) .......................................................................33 Persistent Sector Protection Mode Locking Bit ........................................35 RY/BY#: Ready/Busy# ....................................................................................... 58 DQ6: Toggle Bit I ...............................................................................................58 Figure 7. Toggle Bit Algorithm ............................................. 59 Password Protection Mode . . . . . . . . . . . . . . . . . 35 Password and Password Mode Locking Bit ................................................36 64-bit Password ...................................................................................................36 DQ2: Toggle Bit II ..............................................................................................60 Reading Toggle Bits DQ6/DQ2 .....................................................................60 DQ5: Exceeded Timing Limits ........................................................................60 DQ3: Sector Erase Timer .................................................................................61 December 23, 2004 S71PL129Jxx_00_A5 3 Advance Information Table 14. Write Operation Status ......................................... 61 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62 Figure 8. Maximum Overshoot Waveforms............................. 62 Write Timings ......................................................................................................85 Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85 Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 86 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Industrial (I) Devices ..........................................................................................63 Extended (E) Devices .........................................................................................63 Supply Voltages ....................................................................................................63 Deep Power-down Timing ..............................................................................86 Figure 28. Deep Power Down Timing .................................... 86 Power-on Timing ................................................................................................86 Figure 29. Power-on Timing ................................................ 86 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64 Table 15. CMOS Compatible ................................................ 64 Provisions of Address Skew ............................................................................87 Read ....................................................................................................................87 Figure 30. Read................................................................. 87 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65 Test Conditions ...................................................................................................65 Figure 9. Test Setups......................................................... 65 Table 16. Test Specifications ............................................... 65 Write ..................................................................................................................87 Figure 31. Write ................................................................ 87 Switching Waveforms ........................................................................................65 Table 17. Key to Switching Waveforms ................................. 65 Figure 10. Input Waveforms and Measurement Levels............. 66 pSRAM Type 1 Functional Description . . . . . . . . . . . . . . . . . . . . . 88 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 89 Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94 Output Load Circuit .......................................................................................... 95 Figure 32. Output Load Circuit............................................. 95 VCC RampRate .................................................................................................. 66 Read Operations ................................................................................................ 66 Table 18. Read-Only Operations .......................................... 66 Figure 11. Read Operation Timings ....................................... 67 Figure 12. Page Read Operation Timings ............................... 67 Reset ...................................................................................................................... 68 Table 19. Hardware Reset (RESET#) .................................... 68 Figure 13. Reset Timings..................................................... 68 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107 Read Cycle ...........................................................................................................107 Figure 33. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH) .............................. 107 Figure 34. Timing Waveform of Read Cycle (WE# = ZZ# = VIH)......................................................... 108 Figure 35. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH)......................................................... 109 Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH)................................................ 110 Figure 37. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH)................................................. 110 Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH) ................................................................... 111 Erase/Program Operations ............................................................................. 69 Table 20. Erase and Program Operations .............................. 69 Timing Diagrams ................................................................................................. 70 Figure 14. Program Operation Timings .................................. 70 Figure 15. Accelerated Program Timing Diagram .................... 70 Figure 16. Chip/Sector Erase Operation Timings ..................... 71 Figure 17. Back-to-back Read/Write Cycle Timings ................. 72 Figure 18. Data# Polling Timings (During Embedded Algorithms) ............................................ 72 Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73 Figure 20. DQ2 vs. DQ6 ...................................................... 73 Write Cycle ..........................................................................................................110 Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 21. Temporary Sector Unprotect ................................. 74 Figure 21. Temporary Sector Unprotect Timing Diagram.......... 74 Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................ 75 Controlled Erase Operations ..........................................................................76 Table 22. Alternate CE# Controlled Erase and Program Operations ........................................................... 76 Table 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings ............................................................. 77 Table 24. CE1#/CE2# Timing ............................................. 77 Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control ............................................................................. 78 Table 25. Erase And Programming Performance .................... 78 Partial Array Self Refresh (PAR) .....................................................................111 Temperature Compensated Refresh (for 64Mb) .....................................112 Deep Sleep Mode ...............................................................................................112 Reduced Memory Size (for 32M and 16M) ..................................................112 Other Mode Register Settings (for 64M) ....................................................112 BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78 Figure 39. Mode Register .................................................. 113 Figure 40. Mode Register Update Timings (UB#, LB#, OE# are Don’t Care)..................................................................... 113 Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 114 Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)........................................................... 114 pSRAM Type 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . 80 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80 AC Characteristics and Operating Conditions . 81 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83 Read Timings ........................................................................................................83 Figure 24. Read Cycle ......................................................... 83 Figure 25. Page Read Cycle (8 Words Access) ........................ 84 Type 2 pSRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Information . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 118 118 118 119 119 Power Up ..............................................................................................................119 Figure 43. Power Up 1 (CS1# Controlled) ........................... 119 Figure 44. Power Up 2 (CS2 Controlled).............................. 119 Functional Description . . . . . . . . . . . . . . . . . . . . 120 Absolute Maximum Ratings . . . . . . . . . . . . . . . 120 DC Recommended Operating Conditions . . . . 120 S71PL129Jxx_00_A5 December 23, 2004 4 Advance Information DC and Operating Characteristics . . . . . . . . . . . 121 Common ............................................................................................................... 121 16M pSRAM ......................................................................................................... 122 32M pSRAM ........................................................................................................ 122 64M pSRAM ........................................................................................................ 123 128M pSRAM ....................................................................................................... 123 Power Down Parameters ............................................................................... 137 Other Timing Parameters ............................................................................... 137 AC Test Conditions .........................................................................................138 AC Measurement Output Load Circuits ...................................................138 Figure 53. AC Output Load Circuit – 16 Mb.......................... 138 Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb .......... 138 AC Operating Conditions . . . . . . . . . . . . . . . . . 124 Test Conditions (Test Load and Test Input/Output Reference) ....... 124 Figure 45. Output Load ..................................................... 124 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139 Read Timings .......................................................................................................139 Figure 55. Read Timing #1 (Basic Timing) .......................... 139 Figure 56. Read Timing #2 (OE# Address Access................. 139 Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140 Figure 58. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only) ............................... 140 Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only) ......................................................... 141 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126 Read Timings ...................................................................................................... 126 Figure 46. Timing Waveform of Read Cycle(1)...................... 126 Figure 47. Timing Waveform of Read Cycle(2)...................... 126 Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127 Write Timings .................................................................................................... 127 Figure 49. Write Cycle #1 (WE# Controlled) ........................ Figure 50. Write Cycle #2 (CS1# Controlled) ....................... Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled) .............................................................. Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) ...................................................................... 127 128 128 129 Write Timings ......................................................................................................141 Figure 60. Write Timing #1 (Basic Timing) .......................... Figure 61. Write Timing #2 (WE# Control).......................... Figure 62. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control) .................................. Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) .................................. Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) .................................. Figure 65. Read/Write Timing #1-1 (CE1# Control) ............. Figure 66. Read / Write Timing #1-2 (CE1#/WE#/OE# Control) ................................................ Figure 67. Read / Write Timing #2 (OE#, WE# Control) ....... Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) ........................................ Figure 69. Power-up Timing #1 ......................................... Figure 70. Power-up Timing #2 ......................................... Figure 71. Power Down Entry and Exit Timing ..................... Figure 72. Standby Entry Timing after Read or Write............ Figure 73. Power Down Program Timing (for 32M/64M Only). 141 142 142 143 143 144 144 145 145 146 146 146 147 147 pSRAM Type 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Functional Description . . . . . . . . . . . . . . . . . . . . . 131 Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131 Power Down ....................................................................................................... 131 Power Down Program Sequence ................................................................. 132 Address Key ....................................................................................................... 132 Read/Write Timings ..........................................................................................144 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133 Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135 Read Operation ..................................................................................................135 Write Operation ............................................................................................... 136 Revision Summary December 23, 2004 S71PL129Jxx_00_A5 5 Advance Information MCP Block Diagram VCCf VCC VCC CE1#f CE2#f WP#/ACC RESET# Flash-only Address Shared Address OE# WE# Flash 1 VSS RY/BY# VCCS DQ15 to DQ0 VCC pSRAM IO15-IO0 CE#s UB#s LB#s CE2#ps CEM1#ps CE# UB# LB# 6 S71PL129Jxx_00_A5 December 23, 2004 Advance Information Connection Diagram 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 NC B5 RFU C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 CE1#f J2 CE1#s D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 C4 LB# D4 UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 H5 DQ3 J5 VCCf K5 DQ11 L5 RFU M1 NC H6 DQ4 J6 VCCs K6 RFU L6 RFU C5 WP/ACC D5 RST#f E5 RY/BY# B6 RFU C6 WE# D6 CE2s E6 A20 C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 D9 A15 E9 A21 F9 CE2# G9 A16 H9 RFU J9 VSS A10 NC Legend Shared (Note 1) Flash only RAM only Reserved for Future Use M10 NC Note: May be shared depending on density: — A21 is shared for the 64M pSRAM configuration. — A20 is shred for the 32M pSRAM configuration. — A19 is shared for the 16M pSRAM configuration. MCP S71PL129JC0 S71PL129JB0 S71PL129JA0 Flash-only Addresses A22 A22-A21 A22-A20 Shared Addresses A21-A0 A20-A0 A19-A0 Note: It is advised to tie J5 and L5 together on the board. December 23, 2004 S71PL129Jxx_00_A5 7 Advance Information Input/Output Description Pin Description A21–A0 DQ15–DQ0 CE1#f CE2#f CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf = = = = = = = = = = = = = = 22 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 2 (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low (Flash 1) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally VCCps VSS NC = = = Logic Symbol 22 A21–A0 16 CE1#f CE2#f CE1#ps CE2ps OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15–DQ0 8 S71PL129Jxx_00_A5 December 23, 2004 Advance Information Ordering Information The order number is formed by a valid combinations of the following: S71PL 129 J B0 BA W 9 Z 0 PACKING TYPE 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER See valid combinations table. PACKAGE MODIFIER 9 = 8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064) TEMPERATURE RANGE W = Wireless (-25°C to +85°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM C0 = B0 = A0 = DENSITY 64 Mb pSRAM 32 Mb pSRAM 16 Mb pSRAM PROCESS TECHNOLOGY J = 110 nm, Floating Gate Technology FLASH DENSITY 129 = 128Mb, dual CE# PRODUCT FAMILY S71PL Multi-chip Product (MCP) 3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM December 23, 2004 S71PL129Jxx_00_A5 9 Advance Information S71PL129J Valid Combinations Base Ordering Part Number S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 S71PL129JC0 S71PL129JC0 S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 S71PL129JC0 S71PL129JC0 S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 S71PL129JC0 S71PL129JC0 S71PL129JA0 S71PL129JB0 S71PL129JB0 S71PL129JB0 S71PL129JC0 S71PL129JC0 BFI BAI BFW BAW Package & Temperature Package Modifier/ Model Number 9P 9Z 9B 9U 9Z 9U 9P 9Z 9B 9U 9Z 9U 9P 9Z 9B 9U 9Z 9U 9P 9Z 9B 9U 9Z 9U 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) pSRAM 7 / 70 pSRAM 7 / 70 pSRAM 2 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 7 / 70 pSRAM 2 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 7 / 70 pSRAM 2 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 7 / 70 pSRAM 2 / 70 pSRAM 6 / 70 pSRAM 7 / 70 pSRAM 6 / 70 Package Marking (Note 2) Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. 3. Contact factory for availability of any of the above OPNs. RAM type availability may vary over time. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 10 S71PL129Jxx_00_A5 December 23, 2004 Advance Information Physical Dimensions TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 L J H G F E D CB A E1 INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 64X 0.15 0.08 0.20 C 6 SIDE VIEW b M C AB MC C 0.08 C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TLA 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3352 \ 16-038.22a December 23, 2004 S71PL129Jxx_00_A5 11 S29PL129J for MCP 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control Datasheet Distinctive Characteristics Architectural Advantages 128 Mbit Page Mode devices — Page size of 8 words: Fast page read access from random locations within the page Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications Dual Chip Enable inputs (only in PL129J) — Two CE# inputs control selection of each half of the memory space Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — CE#1 controlled banks: Bank 1A: - 16Mbit (4Kw x 8 and 32Kw x 31) Bank 1B: - 48Mbit (32Kw x 96) — CE#2 controlled banks: Bank 2A: - 48 Mbit (32Kw x 96) Bank 2B: - 16Mbit (4Kw x 8 and 32Kw x 31) Enhanced VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin Secured Silicon Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 110 nm process technology Data Retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical ADVANCE INFORMATION Performance Characteristics High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns Power consumption (typical values at 10 MHz) — 45 mA active read current — 17 mA program/erase current — 0.2 µA typical standby mode current Software Features Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences Hardware Features Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input — At VIL, hardware level protection for the first and last two 4K word sectors. — At VIH, allows removal of sector protection — At VHH, provides accelerated programming in a factory setting Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups Publication Number S29PL129J_MCP_00 Revision A Amendment 0 Issue Date June 4, 2004 Advance Information to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at VCC level Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 13 Advance Information General Description The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#). Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank 1A 1B 2A 2B PL129J Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31) CE# Control CE1# CE1# CE2# CE2# Page Mode Features The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two 14 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 15 Advance Information Block Diagram DQ15–DQ0 RY/BY# (See Note) VCC VSS Sector Switches VIO RESET# Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator Input/Output Buffers CE# OE# Chip Enable Output Enable Logic Data Latch Y-Decoder VCC Detector Timer Address Latch Y-Gating Amax–A3 X-Decoder Cell Matrix A2–A0 Notes: 1. RY/BY# is an open drain output. 2. For PL129J there are two CE# (CE1# and CE2#) 16 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Simultaneous Read/Write Block Diagram (PL129J) VCC VSS CE1#=L CE2#=H Mux A21–A0 Bank 1A Address OE# Bank 1A Y-gate X-Decoder A21–A0 RY/BY# Bank 1B Address Bank 1B X-Decoder A21–A0 RESET# WE# CE1# CE2# WP#/ACC STATE CONTROL & COMMAND REGISTER CE1#=H CE2#=L DQ0–DQ15 X-Decoder Status DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Control Mux A21–A0 X-Decoder A21–A0 Mux Bank 2B Address Bank 2B Notes: 1. Amax = A21 (PL129J) June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP DQ15–DQ0 Bank 2A Address Bank 2A Y-gate DQ15–DQ0 17 Advance Information Pin Description Amax–A0 DQ15–DQ0 CE# OE# WE# VSS NC RY/BY# = = = = = = = = Address bus 16-bit data inputs/outputs/float Chip Enable Inputs Output Enable Input Write Enable Device Ground Pin Not Connected Internally Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. Input/Output Buffer Power Supply 2.7 V to 3.6 V Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) Hardware Reset Pin Chip Enable Inputs. CE1# controls the 64Mb in Banks 1A and 1B. CE2# controls the 64 Mb in Banks 2A and 2B. WP#/ACC = VIO VCC RESET# CE1#, CE2# = = = = Notes: 1. Amax = A21 Logic Symbol max+1 Amax–A0 DQ15–DQ0 CE# OE# WE# WP#/ACC RESET# RY/BY# 16 VIO (VCCQ) 18 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Operation Read CE1# L H L H VIO± 0.3 V L X X PL129J Device Bus Operations OE# L WE# H RESET# H WP#/ACC X X (Note 2) X X X X Addresses (A21–A0) AIN DQ15– DQ0 DOUT CE2# H L H L VIO ± 0.3 V L X X Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage) H X H X X L X H X X H VIO ± 0.3 V H L VID AIN X X X AIN DIN High-Z High-Z High-Z DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See ““High Voltage Sector Protection” on page 37.” 2. WP#/ACC must be high when writing to upper two and lower two sectors. Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE# pins to VIL. In PL129J, CE1# and CE2# are the power control and select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power control. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See Table 24 for timing specifications and Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 19 Advance Information Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE1# and CE#2 are deasserted (=VIH), the reassertion of CE1# or CE#2 for subsequent access has access time of tACC or tCE. Here again, CE1#/CE#2 selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing A2–A0 to select the specific word within that page. Table 2. Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 Page Select A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (A21–A19) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Bank Bank 1A Bank 1B CE1# 0 0 CE2# 1 1 PL129J: A21–A20 00 01, 10, 11 20 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Bank 2A Bank 2B 1 1 0 0 00, 01, 10 11 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE1# or CE#2 to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. “Word Program Command Sequence” on page 46 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the set of address space that each sector occupies. A “bank address” is the set of address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. “Command Definitions” on page 45 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing specification tables and timing diagrams in “Reset” for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. See “Secured Silicon Sector Addresses” on page 29 and “Autoselect Command Sequence” on page 46 for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 21 Advance Information The device enters the CMOS standby mode when the CE1# or CE#2 and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE1# or CE#2 and RESET# are held at VIH, but not within VIO ± 0.3 V, the device is in standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in “DC Characteristics” represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in “DC Characteristics” represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state 22 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 3. Bank Sector SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 Bank 1A SA1-18 SA1-19 SA1-20 SA1-21 SA1-22 SA1-23 SA1-24 SA1-25 SA1-26 SA1-27 SA1-28 SA1-29 SA1-30 SA1-31 SA1-32 SA1-33 SA1-34 SA1-35 SA1-36 SA1-37 SA1-38 S29PL129J Sector Architecture (Sheet 1 of 7) CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 23 Advance Information Table 3. Bank Sector SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 SA1-57 SA1-58 Bank 1B SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 SA1-67 SA1-68 SA1-69 SA1-70 SA1-71 SA1-72 SA1-73 SA1-74 SA1-75 SA1-76 SA1-77 SA1-78 SA1-79 SA1-80 SA1-81 SA1-82 S29PL129J Sector Architecture (Sheet 2 of 7) CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 24 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 3. Bank Sector SA1-83 SA1-84 SA1-85 SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95 SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 Bank 1B SA1-103 SA1-104 SA1-105 SA1-106 SA1-107 SA1-108 SA1-109 SA1-110 SA1-111 SA1-112 SA1-113 SA1-114 SA1-115 SA1-116 SA1-117 SA1-118 SA1-119 SA1-120 SA1-121 SA1-122 SA1-123 SA1-124 SA1-125 SA1-126 S29PL129J Sector Architecture (Sheet 3 of 7) CE2# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 25 Advance Information Table 3. Bank Sector SA1-127 SA1-128 Bank 1B SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 Bank 2A SA2-16 SA2-17 SA2-18 SA2-19 SA2-20 SA2-21 SA2-22 SA2-23 SA2-24 SA2-25 SA2-26 SA2-27 SA2-28 SA2-29 SA2-30 SA2-31 SA2-32 SA2-33 SA2-34 SA2-35 S29PL129J Sector Architecture (Sheet 4 of 7) CE2# 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE1# 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111XXX 0000000XXX 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3FFFFFh 000000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 26 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 3. Bank Sector SA2-36 SA2-37 Bank 2A SA2-38 SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 SA2-57 SA2-58 SA2-59 Bank 2A SA2-60 SA2-61 SA2-62 SA2-63 SA2-64 SA2-65 SA2-66 SA2-67 SA2-68 SA2-69 SA2-70 SA2-71 SA2-72 SA2-73 SA2-74 SA2-75 SA2-76 SA2-77 SA2-78 SA2-79 S29PL129J Sector Architecture (Sheet 5 of 7) CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX 0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 270000h–277FFFh 278000h–27FFFFh June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 27 Advance Information Table 3. S29PL129J Sector Architecture (Sheet 6 of 7) Bank Sector SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 Bank 2A SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 Bank 2B SA2-108 SA2-109 SA2-110 SA2-111 SA2-112 SA2-113 SA2-114 SA2-115 SA2-116 SA2-117 SA2-118 SA2-119 SA2-120 SA2-121 SA2-122 SA2-123 CE1# 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CE2# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sector Address (A21A12) 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX 1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range (x16) 280000h–287FFFh 288000h–28FFFFh 290000h–297FFFh 298000h–29FFFFh 2A0000h–2A7FFFh 2A8000h–2AFFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 390000h–397FFFh 398000h–39FFFFh 3A0000h–3A7FFFh 3A8000h–3AFFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 28 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 3. Bank Sector SA2-124 SA2-125 SA2-126 SA2-127 Bank 2B SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134 S29PL129J Sector Architecture (Sheet 7 of 7) CE2# 0 0 0 0 0 0 0 0 0 0 0 CE1# 1 1 1 1 1 1 1 1 1 1 1 Sector Address (A21A12) 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector Size (Kwords) 32 32 32 4 4 4 4 4 4 4 4 Address Range (x16) 3E0000h–3E7FFFh 3E8000h–3EFFFFh 3F0000h–3F7FFFh 3F8000h–3F8FFFh 3F9000h–3F9FFFh 3FA000h–3FAFFFh 3FB000h–3FBFFFh 3FC000h–3FCFFFh 3FD000h–3FDFFFh 3FE000h–3FEFFFh 3FF000h–3FFFFFh Table 4. Secured Silicon Sector Addresses Sector Size Address Range 000000h-00003Fh 000040h-00007Fh Factory-Locked Area Customer-Lockable Area 64 words 64 words Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Table 5 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 12. Note: If a Bank Address (BA) (on address bits A21–A19) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require VID. See “Autoselect Command Sequence” on page 46 for more information. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 29 Advance Information Table 5. Autoselect Codes for PL129J A21 to A12 X A5 to A4 X DQ15 to DQ0 0001h Description Manufacturer ID: Spansion products Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification Secured Silicon Indicator Bit (DQ7, DQ6) CE1# CE2# L H L H L H L H L H L H H L H L H L H L H L H L OE# L WE# H A10 X A9 A8 VI D A7 L A6 L A3 A2 L L A1 L A0 L X L VI D L L H 227Eh L H X X X L L L H H H L 2221h H VI D H H H 2200h 0001h (protected), 0000h (unprotected) DQ7=1 (factory locked), DQ6=1 (factory and customer locked) L H SA X X L L L L L H L L H X X VI D X X L X L L H H Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences 30 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control CE2# Control Sector/Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords Sector Group SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 - SA1-14 SA1-15 - SA1-18 SA1-19 - SA1-22 SA1-23 - SA1-26 SA1-27 - SA1-30 SA1-31 - SA1-34 SA1-35 - SA1-38 SA1-39 - SA1-42 SA1-43 - SA1-46 SA1-47 - SA1-50 SA1-51 - SA1-54 SA1-55 - SA1-58 SA1-59 - SA1-62 SA1-63 - SA1-66 SA1-67 - SA1-70 SA1-71 - SA1-74 SA1-75 - SA1-78 SA1-79 - SA1-82 SA1-83 - SA1-86 SA1-87 - SA1-90 SA1-91 - SA1-94 SA1-95 - SA1-98 SA1-99 - SA1-102 SA1-103 - SA1-106 SA1-107 - SA1-110 SA1-111 - SA1-114 SA1-115 - SA1-118 SA1-119 - SA1-122 SA1-123 - SA1-126 SA1-127 - SA1-130 SA1-131 - SA1-134 A21-12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 11111XXXXX Sector Group SA2-0–SA2-3 SA2-4–SA2-7 SA2-8–SA2-11 SA2-12–SA2-15 SA2-16–SA2-19 SA2-20–SA2-23 SA2-24–SA2-27 SA2-28–SA2-31 SA2-32–SA2-35 SA2-36–SA2-39 SA2-40–SA2-43 SA2-44–SA2-47 SA2-48–SA2-51 SA2-52–SA2-55 SA2-56–SA2-59 SA2-60–SA2-63 SA2-64–SA2-67 SA2-68–SA2-71 SA2-72–SA2-75 SA2-76–SA2-79 SA2-80–SA2-83 SA2-84–SA2-87 SA2-88–SA2-91 SA2-92–SA2-95 SA2-96–SA2-99 SA2-100–SA2-103 SA2-104–SA2-107 SA2-108–SA2-111 SA2-112–SA2-115 SA2-116–SA2-119 SA2-120–SA2-123 SA2-124 SA2-125 SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134 A21-12 00000XXXXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector/Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 31 Advance Information Selecting a Sector Protection Mode The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See “Secured Silicon Sector Addresses” on page 29 for details. Table 7. Sector Protection Schemes DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 PPB Lock 0 1 0 0 0 1 1 1 Protected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable Sector Protection The PL129J features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors SA1133, SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method is used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first 32 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Persistent Sector Protection The Persistent Sector Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different sector protection states: Persistently Locked—The sector is protected and cannot be changed. Dynamically Locked—The sector is protected and can be changed by a simple command. Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Sector Protection Mode Locking Bit Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after powerup or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 33 Advance Information the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs are set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. These states are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because the PPBs are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to “1”. Once all PPBs are programmed to the desired settings, the PPB Lock should be set to “1”. Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. 34 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. There is an alternative means of reading the protection status. Take RESET# to VIL and hold WE# at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) produces a logical ‘1” code at device output DQ0 for a protected sector or a “0” for an unprotected sector. In this mode, the other addresses are don’t cares. Address location with A1 = VIL are reserved for autoselect manufacturer and device codes. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 35 Advance Information Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is not any way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors(PL127J: 0, 1, 268, and 269, PL064J: 0, 1, 140, and 141, PL032J: 0, 1, 76, and 77, PL129J: SA1-133, SA1-134,SA2-0 and SA2-1) without using VID. This function is provided by the WP# pin and overrides the previously discussed method, “High Voltage Sector Protection” on page 37. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “High Voltage Sector Protection” on page 37. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 36 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 37 Advance Information START PLSCNT = 1 RESET# = VID Wait 4 µs Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 4 µs Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address No Temporary Sector Unprotect Mode Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Reset PLSCNT = 1 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A7-A0 = 00000010 Set up next sector address Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Remove VID from RESET# Data = 00h? Yes Write reset command Sector Protect complete Write reset command Device failed Last sector verified? Yes Remove VID from RESET# No Write reset command Sector Unprotect complete Sector Protect complete Sector Protect Algorithm Write reset command Device failed Sector Unprotect complete Sector Unprotect Algorithm Figure 1. In-System Sector Protection/Sector Unprotection Algorithms 38 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected a gain. Figure 2 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors are unprotected (If WP#/ACC = VIL, upper two and lower two sectors remain protected). 2. All previously protected sectors are protected once again Figure 2. Temporary Sector Unprotect Operation Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word Secured Silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The Secured Silicon sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the factory-locked and customer locked status of the part. The system accesses the Secured Silicon Sector through a command sequence (see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence” on page 46). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 39 Advance Information Factory-Locked Area (64 words) The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Optional Spansion programming services can program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only FASL can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact your local sales office for details on using Spansion’s programming services. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon sector is enabled. Customer-Lockable Area (64 words) The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The Secured Silicon Sector Customerlocked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1” by issuing the Secured Silicon Protection Bit Program Command. The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. The Customer-lockable Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 3. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Secured Silicon Sector Protection Bits The Secured Silicon Sector Protection Bits prevent programming of the Secured Silicon Sector memory area. Once set, the Secured Silicon Sector memory area contents are non-modifiable. 40 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information START RESET# = VIH or VID Wait 1 µs Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Write reset command SecSi Sector Protect Verify complete Figure 3. Secured Silicon Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE1# = CE2# = VIH or WE# = VIH. To initiate a write cycle, CE1# / CE2# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 41 Advance Information Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 8, Table 9, Table 10, and Table 11. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 8, Table 9, Table 10, and Table 11. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents. Table 8. CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string “QRY” Description Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 42 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Table 9. System Interface String Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0000h 0009h 0000h 0004h 0000h 0004h 0000h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Description Table 10. Device Geometry Definition Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h (PL129J) 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh (PL129J) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Device Size = 2 byte N Description Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Table 11. Primary Vendor-Specific Extended Query Addresses 40h 41h 42h Data 0050h 0052h 0049h Query-unique ASCII string “PRI” Description June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 43 Advance Information Table 11. Addresses 43h 44h 45h Data 0031h 0033h TBD Primary Vendor-Specific Extended Query (Continued) Description Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = Both top and bottom boot with write protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 0002h 0001h 0001h 0007h (PLxxxJ) 00E7h (PL129J) 0000h 0002h (PLxxxJ) 0085h 0095h 4Fh 0001h 50h 57h 58h 59h 5Ah 5Bh 0001h 0004h 0027h (PL129J) 0060h (PL129J) 0060h (PL129J) 0027h (PL129J) 44 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in PL129J), whichever happens later. All data is latched on the rising edge of WE# or CE# (CE1# / CE2# in PL129J), whichever happens first. See AC Characteristics for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” on page 50 for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See “Reset Command,” for more information. See “Requirements for Reading Array Data” on page 19 in “Device Bus Operations” for more information. The AC Characteristics table provides the read parameters, and Figure 12 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 45 Advance Information If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 12 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend). Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 12 shows the address and data requirements for both command sequences. Also see, “Secured Silicon Sector Flash Memory Region” on page 39 for further information. Note: The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the program command sequence. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/ erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” on page 56 for information on these status bits. 46 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (Table 13) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program operation. See the Erase/Program Operations table in AC Characteristics for parameters, and Figure 14 for timing diagrams. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 47 Advance Information START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 12 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 56 for information on these status bits. Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and Figure 16 for timing diagrams. 48 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 12 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal operation cannot be guaranteed. The system must rewrite the command sequence and any additional addresses and commands. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/ erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” on page 61). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See “Write Operation Status” on page 56 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and Figure 16 for timing diagrams. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 49 Advance Information START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 12 for erase command sequence. 2. See “DQ3: Sector Erase Timer” on page 61 for information on the sector erase timer. Figure 5. Erase Operation Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” on page 56 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program 50 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. See “Write Operation Status” on page 56 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Secured Silicon Sector Addresses” on page 29 and “Autoselect Command Sequence” on page 46 for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Four Password Program commands are required to program the password. The system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F’s onto the DQ data bus. The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 51 Advance Information command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. Secured Silicon Sector Protection Bit Program Command The Secured Silicon Sector Protection Bit Program Command programs the Secured Silicon Sector Protection Bit, which prevents the Secured Silicon sector memory from being cleared. If the Secured Silicon Sector Protection Bit is verified as programmed without margin, the Secured Silicon Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCClevel Secured Silicon Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode). DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (Amax–A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt 52 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approximately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A22–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The PPB Program command does not follow the Embedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. PPB Lock Bit Set Command The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 53 Advance Information DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Command Definitions Tables Table 12. Memory Array Command Definitions Command (Notes) Read (Note 5) Reset (Note 6) Manufacturer ID Device ID (Note 10) Autoselect (Note 7) Secured Silicon Sector Factory Protect (Note 8) Sector Group Protect Verify (Note 9) Program Chip Erase Sector Erase Program/Erase Suspend (Note 11) Program/Erase Resume (Note 12) CFI Query (Note 13) Accelerated Program (Note 15) Unlock Bypass Entry (Note 15) Unlock Bypass Program (Note 15) Unlock Bypass Erase (Note 15) Unlock Bypass CFI (Notes 13, 15) Unlock Bypass Reset (Note 15) Cycles Bus Cycles (Notes 1–4) Addr RA XXX 555 555 555 555 555 555 555 BA BA 55 XX 555 XX XX XX XXX Data RD F0 AA AA AA AAA AA AA AA B0 30 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 (BA) 555 (BA) 555 (BA) 555 (BA) 555 555 555 555 90 90 90 90 A0 80 80 (BA) X00 (BA) X01 X03 (SA) X02 PA 555 555 01 227E (Note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA) X0E (Note 10) (BA) X0F (Note 10) Addr Data Addr Data Addr Data Addr Data Addr Data 1 1 4 6 4 4 4 6 6 1 1 1 2 3 2 2 1 2 Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by Amax:A19. PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse, whichever happens first. RA = Read Address (Amax:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 54 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See “Autoselect Command Sequence” on page 46 for more information. 8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked. 9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. PL129J (X0Eh = 2221h, X0Fh = 2200h). 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Table 13. Sector Protection Command Definitions Command (Notes) Reset Secured Silicon Sector Entry Secured Silicon Sector Exit Secured Silicon Protection Bit Program (Notes 5, 6) Secured Silicon Protection Bit Status Password Program (Notes 5, 7, 8) Password Verify (Notes 6, 8, 9) Password Unlock (Notes 7, 10, 11) PPB Program (Notes 5, 6, 12) PPB Status All PPB Erase (Notes 5, 6, 13, 14) PPB Lock Bit Set PPB Lock Bit Status (Note 15) DYB Write (Note 7) DYB Erase (Note 7) DYB Status (Note 6) PPMLB Program (Notes 5, 6, 12) PPMLB Status (Note 5) SPMLB Program (Notes 5, 6, 12) SPMLB Status (Note 5) Cycles Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 88 90 60 60 38 C8 28 60 90 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD (1) X1 X0 RD (0) 68 48 68 48 PL PL SL SL 48 RD (0) 48 RD (0) SL RD (0) PL RD (0) XX OW OW 00 68 48 OW OW 48 RD (0) OW RD (0) 1 3 4 6 5 4 4 7 6 4 6 3 4 4 4 4 6 5 6 5 XX PD [0-3] [0-3] PWA PWD [0-3] [0-3] PWA [0] (SA) WP (SA) WP WP PWD [0] 68 RD (0) 60 (SA) 40 (SA) WP RD (0) PWA [1] (SA) WP PWD [1] 48 PWA [2] (SA) WP PWD [2] RD (0) PWA [3] PWD [3] Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 55 Advance Information PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password. 9. Command sequence returns FFh if PPMLB is set. 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. 56 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 appears on successive read cycles. Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling algorithm. Figure 1 8 in AC Characteristics shows the Data# Polling timing diagram. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 57 Advance Information START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 14 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. 58 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see “DQ7: Data# Polling” on page 56). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also “DQ2: Toggle Bit II”. START Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ7–DQ0) Address = VA Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Figure 7. Toggle Bit Algorithm S29PL129J for MCP 59 June 4, 2004 S29PL129J_MCP_00_A0 Advance Information Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See “DQ6: Toggle Bit I” and “DQ2: Toggle Bit II” for more information. Figure 7. Toggle Bit Algorithm DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE1# / CE2# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. See Table 14 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the “DQ2: Toggle Bit II” explains the algorithm. See also “DQ6: Toggle Bit I.” Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see “DQ5: Exceeded Timing Limits”). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can 60 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also “Sector Erase Command Sequence” on page 49. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 14 shows the status of DQ3 relative to the other status bits. Table 14. Write Operation Status Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Erase Suspend Mode Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.“DQ5: Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 61 Advance Information Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V WP#/ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V –0.5 V –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform Figure 8. Maximum Overshoot Waveforms 62 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Operating Ranges Operating ranges define those limits between which the functionality of the device is guaranteed. Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V VIO or 2.7–3.6 V Notes: For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO options. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 63 Advance Information DC Characteristics Table 15. CMOS Compatible Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 VIL VIH VHH VID VOL VOH VLKO Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes 1, 2) VCC Active Write Current (Notes 2, 3) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-EraseSuspended Current (Notes 2, 5) VCC Active Page Read Current (Note 2) Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE#, RESET#, WP#/ACC = VIO ± 0.3 V RESET# = VSS ± 0.3 V VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V OE# = VIH, OE# = VIH, OE# = VIH OE# = VIH, 8 word Page Read VIO = 2.7–3.6 V VIO = 2.7–3.6 V VCC = 3.0 V ± 10% VCC = 3.0 V ± 10% IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V IOH = –2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 2.4 2.3 2.5 –0.5 2.0 8.5 11.5 5 MHz 10 MHz 5 MHz 10 MHz 5 MHz 10 MHz 20 45 15 0.2 0.2 0.2 21 46 21 46 17 10 Min Typ Max ±1.0 35 35 ±1.0 30 55 25 5 5 5 45 70 45 70 25 15 0.8 VCC+0.3 9.5 12.5 0.4 Unit µA µA µA µA mA mA µA µA µA mA mA mA mA V V V V V V V Output High Voltage Low VCC Lock-Out Voltage (Note 5) Notes: 1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 1 mA. 5. Not 100% tested. 6. In S29PL129J there are two CE# (CE1#, CE2#). 7. Valid CE1#/CE2# conditions: (CE1# = VIL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH) 64 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information AC Characteristics Test Conditions 3.6 V Device Under Test CL 6.2 kΩ 2.7 kΩ Note: Diodes are IN3064 or equivalent VIO = 3.0 V Figure 9. Test Setups Table 16. Test Specifications Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels VIO = 3.0 V VIO = 3.0 V All Speeds 1 TTL gate 30 5 0.0–3.0 VIO/2 VIO/2 pF ns V V V Unit Switching Waveforms Table 17. Key to Switching Waveforms Waveform Inputs Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 65 Advance Information VIO 0.0 V In VIO/2 Measurement Level VIO/2 Output Figure 10. Input Waveforms and Measurement Levels VCC RampRate All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC >=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 µs, a hardware reset required.+ Read Operations Table 18. Read-Only Operations Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 55 55 55 55 20 20 Speed Options 60 60 60 60 25 25 16 16 5 0 10 65 65 65 65 25 30 70 70 70 70 30 Unit ns ns ns ns ns ns ns ns ns ns tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 3) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling tOEH Notes: 1. Not 100% tested. 2. See Figure 9 and Table 16 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. 4. S29PL129J has two CE# (CE1#, CE2#). 5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH) 6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH) 7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) 8. For 70pF Output Load Capacitance, 2 ns is added to the above tACC,tCE,tPACC,tOE values for all speed grades 66 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Notes: 1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 11. Read Operation Timings Amax-A3 Same Page A2-A0 Aa tACC Ab tPACC Ac tPACC tPACC Ad Data CE# OE# Qa Qb Qc Qd Notes: 1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 12. Page Read Operation Timings June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 67 Advance Information Reset Table 19. Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit µs ns ns ns µs ns Hardware Reset (RESET#) Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Notes: 1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2# Figure 13. Reset Timings 68 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Erase/Program Operations Table 20. Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE1#, CE#2 or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE1# or CE#2 Setup Time CE1# or CE#2 Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 4) Accelerated Programming Operation (Note 4) Sector Erase Operation (Note 4) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max Min 20 0 6 4 0.5 50 0 90 35 25 0 10 0 0 0 35 25 30 0 30 55 55 Speed Options 60 60 0 15 35 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs sec µs ns ns ns Notes: 1. Not 100% tested. 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). 4. See Table 25, “Erase And Programming Performance,” on page 78 for more information. June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 69 Advance Information Timing Diagrams Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 14. Program Operation Timings VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 15. Accelerated Program Timing Diagram 70 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase Status DOUT tBUSY RY/BY# tVCS VCC tRB Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on page 56 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 16. Chip/Sector Erase Operation Timings June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 71 Advance Information tWC Addresses tAS CE# Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tAS tCPH tAH tCP tGHWL tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles Figure 17. Back-to-back Read/Write Cycle Timings tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ6–DQ0 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Figure 18. Data# Polling Timings (During Embedded Algorithms) 72 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information tAHT Addresses tAS tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Notes: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 19. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 20. DQ2 vs. DQ6 June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 73 Advance Information Protect/Unprotect Table 21. Temporary Sector Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns µs µs Note: Not 100% tested. VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR VIL or VIH VID WE# tRSP RY/BY# tRRB Figure 21. Temporary Sector Unprotect Timing Diagram 74 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information VID VIH RESET# SA, A6, A1, A0 Valid* Sector Group Protect/Unprotect Valid* Verify 40h Valid* Data 1 µs CE# 60h 60h Status Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms WE# OE# Notes: 1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. 2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 75 Advance Information Controlled Erase Operations Table 22. Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE1# or CE#2 Pulse Width CE1# or CE#2 Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 20 6 4 0.5 30 25 0 0 0 0 40 25 55 55 Alternate CE# Controlled Erase and Program Operations Speed Options 60 60 0 35 30 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns µs µs sec Notes: 1. Not 100% tested. 2. See the Table 25, “Erase And Programming Performance,” on page 78 for more information. 76 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device 4. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH 5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Table 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings Table 24. CE1#/CE2# Timing Parameter JEDEC Std tCCR Description CE1#/CE2# Recover Time Min All Speed Options 30 Unit ns June 4, 2004 S29PL129J_MCP_00_A0 S29PL129J for MCP 77 Advance Information CE1# tCCR CE2# tCCR Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control Table 25. Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) PL129J PL129J Erase And Programming Performance Typ (Note 1) 0.5 135 6 4 50.4 Max (Note 2) 2 216 100 60 200 Unit sec sec µs µs sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles. BGA Pin Capacitance Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 6.3 7.0 5.5 11 Max 7 8 8 12 Unit pF pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 78 S29PL129J for MCP S29PL129J_MCP_00_A0 June 4, 2004 Advance Information pSRAM Type 6 2M Word by 16-bit Cmos Pseudo Static RAM (32M Density) 4M Word by 16-bit Cmos Pseudo Static RAM (64M Density) Features Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: — Page read operation by 8 words Logic compatible with SRAM R/W pin Standby current — Standby = 70 µA (32M) — Standby = 100 µA (64M) — Deep power-down Standby = 5 µA Access Times 32M 64M Access Time CE1# Access Time OE# Access Time Page Access Time 70 ns 70 ns 25 ns 30 ns Pin Description Pin Name A0 to A21 A0 to A2 I/O1 to I/O16 CE1# CE2 WE# OE# LB#,UB# VDD GND NC Address Inputs Page Address Inputs Data Inputs/Outputs Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Supply Ground Not Connection Description Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 79 Advance Information Functional Description Mode Read (Word) Read (Lower Byte) Read (Upper Byte) Write (Word) Write (Lower Byte) Write (Upper Byte) Outputs Disabled Standby Deep Power-down Standby CE1# L L L L L L L H H CE2 H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X LB# L L H L L H X X X UB# L H L L H L X X X Address X X X X X X X X X I/O1-8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z I/O9-16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z Power IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDSD Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedance. Absolute Maximum Ratings Symbol VDD VIN VOUT Topr Tstrg PD IOUT Rating Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Value -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -40 to 85 -55 to 150 0.6 50 Unit V V V °C °C W mA Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are developed by Spansion and component devices that are developed by a third party (third-party components). Spansion components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. However, ESD test results for third-party components may be available from the component manufacturer. Component manufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash memory Qualification Database and Spansion MCP Qualification Report are available from Spansion sales offices. DC Recommended Operating Conditions (Ta = -40°C to 85°C) Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.6 2.0 -0.3 (Note) Typ 2.75 — — Max 3.3 VDD + 0.3 (Note) 0.4 V Unit Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width. 80 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004 Advance Information DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4) Symbol IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current Page Access Operating Current Standby Current (MOS) Deep Power-down Standby Current VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = - 0.5 mA IOL = 1.0 mA CE1#= VIL, CE2 = VIH, IOUT = 0 mA, tRC = min. ET5UZ8A-43DS ET5VB5A-43DS Test Condition Min -1.0 -1.0 2.0 — — — — — — — Typ. — — ¾ — — — — — — — Max +1.0 +1.0 V 0.4 40 50 25 70 100 5 Unit µA µA V V mA mA mA µA µA CE1#= VIL, CE2 = VIH, IOUT = 0 mA Page add. cycling, tRC = min. CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V CE2 = 0.2 V ET5UZ8A-43DS ET5VB5A-43DS Capacitance (Ta = 25°C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = GND VOUT = GND Max 10 10 Unit pF pF Note: This parameter is sampled periodically and is not 100% tested. AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD Read Cycle Time Address Access Time Chip Enable (CE1#) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Parameter Min 70 — — — — 10 0 0 — — — Max 10000 70 70 25 25 — — — 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 81 Advance Information Symbol tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP Output Data Hold Time Page Mode Time Page Mode Cycle Time Parameter Min 10 70 30 — 10 70 50 70 60 60 0 0 10 6 — 0 30 0 0 300 10 0 30 Max — 10000 — 30 — 10000 — — — — — — — — 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE# Low to Output High-Z WE# High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1# CE2 Hold from Power On — — — — — — — ns ns ns µs ms ns µs AC Test Conditions Parameter Output load Input pulse level Timing measurements Reference level tR, tF Condition 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 5 ns 82 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004 Advance Information Timing Diagrams Read Timings tRC Address A0 to A20(32M) A0 to A21(64M) tACC tCO tOH CE1# CE2 tOE OE# tODO WE# Fix-H tOD tBA UB#, LB# tBE DOUT I/O1 to I/O16 tOEE Hi-Z tCOE INDETERMINATE VALID DATA OUT Hi-Z tBD Figure 24. Read Cycle Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 83 Advance Information tPM Address A0 to A2 Address A3 to A20(32M) A3 to A21(64M) tRC tPC tPC tPC CE1# CE2 Fix-H OE# WE# UB#, LB# tBA tOEE DOUT I/O1 to I/O16 tBE Hi-Z tCOE tCO tACC DOUT tAA DOUT tAA DOUT DOUT Hi-Z tOE tAOH tAOH tAOH tBD tOH tOD tAA tODO * Maximum 8 words Figure 25. Page Read Cycle (8 Words Access) 84 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004 Advance Information Write Timings tWC Address A0 to A20(32M) A0 to A21(64M) tAS WE# tAW tWP tWR tWEH tCW CE1# tWR tCH CE2 tBW UB#, LB# tODW DOUT I/O1 to I/O16 DIN I/O1 to I/O16 (See Note 10) Hi-Z tDS (See Note 9) tDH (See Note 9) tOEW (See Note 11) tWR VALID DATA IN Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8) Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 85 Advance Information tWC Address A0 to A20(32M) A0 to A21(64M) tAS WE# tAW tWP tWR tCEH tCW CE1# tWR tCH CE2 tBW UB#, LB# tBE DOUT I/O1 to I/O16 Hi-Z tCOE tDS DIN I/O1 to I/O16 (See Note 9) tDH tODW Hi-Z tWR VALID DATA IN Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) Deep Power-down Timing CE1# tDPD CE2 tCS tCH Figure 28. Deep Power Down Timing Power-on Timing VDD VDD min CE1# tCHC CE2 tCHP tCH Figure 29. Power-on Timing 86 pSRAM Type 6 pSRAM_Type06_14_A1 Ocotober 16, 2004 Advance Information Provisions of Address Skew Read In case multiple invalid address cycles shorter than tRC min. sustain over 10 µs in an active status, at least one valid address cycle over tRC min. is required during 10µs. over 10µs CE1# WE# Address tRCmin Figure 30. Write Read In case multiple invalid address cycles shorter than tWC min. sustain over 10 µs in an active status, at least one valid address cycle over tWC min. is required during 10 µs. CE1# tWPmin WE# Address tWCmin Figure 31. Write Notes: 1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. 2. All voltages are reference to GND. 3. IDDO depends on the cycle time. 4. IDDO depends on output loading. Specified values are defined with the output open condition. 5. AC measurements are assumed tR, tF = 5 ns. 6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 7. Data cannot be retained at deep power-down stand-by mode. 8. If OE# is high during the write cycle, the outputs will remain at high impedance. 9. During the output state of I/O signals, input signals of reverse polarity must not be applied. 10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. 11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 87 Advance Information pSRAM Type 1 4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Functional Description Mode Read (word) Read (lower byte) Read (upper byte) Write (word) Write (lower byte) Write (upper byte) Outputs disabled Standby Deep power down CE# L L L L L L L H H CE2/ZZ# H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X UB# L H L L H L X X X LB# L L H L L H X X X Addresses X X X X X X X X X I/O 1-8 Dout Dout High-Z Din Din Invalid High-Z High-Z High-Z I/O 9-16 Dout High-Z Dout Din Invalid Din High-Z High-Z High-Z Power IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE ISTANDBY IDEEP SLEEP Absolute Maximum Ratings Item Voltage on any pin relative to VSS Voltage on VCC relative to VSS Power dissipation Storage temperature Operating temperature Symbol Vin, Vout VCC PD TSTG TA Ratings -0.2 to VCC +0.3 -0.2 to 3.6 1 -55 to 150 -25 to 85 Units V V W °C °C 88 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information DC Characteristics (4Mb pSRAM Asynchronous) Asynchronous Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 70 mA 0.2 V 0.8 Vccq V Conditions Min 2.7 0.8 Vccq -0.3 -70 4Mb pSRAM Max 3.3 VCC + 0.3 0.4 0.5 0.5 Units V V V µA µA ISTANDBY IDEEP SLEEP µA µA µA µA IPAR 1/4 IPAR 1/2 August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 89 Advance Information DC Characteristics (8Mb pSRAM Asynchronous) Asynchronous Version Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VCC-0.4 VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 60 mA µA 23 60 mA µA 25 70 mA µA 0.4 V 0.4 V 0.2 V V Conditions Min 2.7 2.2 -0.3 -55 8Mb pSRAM Max 3.3 VCC + 0.3 0.6 0.5 0.5 Units V V V µA µA VCC-0.4 V 0.8 VCCQ V Min 2.7 2.2 -0.3 B -70 8Mb pSRAM Max 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V µA µA Min 2.7 0.8 -0.3 C -70 8Mb pSRAM Max 3.3 VCC+0.3 0.4 0.5 0.5 Units V V V µA µA ISTANDBY Standby Current IDEEP SLEEP Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current µA µA µA x x x µA µA µA x x x µA µA µA IPAR 1/4 IPAR 1/2 90 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information DC Characteristics (16Mb pSRAM Asynchronous) Asynchronous Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE ISTANDBY IDEEP SLEEP IPAR 1/4 IPAR 1/2 Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 100 mA µA µA µA µA 25 100 mA µA µA µA µA 0.4 V 0.4 V VCC-0.4 V Conditions -55 16Mb pSRAM Minimum 2.7 2.2 -0.3 Maximum 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V µA µA VCC-0.4 V -70 16Mb pSRAM Minimum 2.7 2.2 -0.3 Maximum 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V µA µA x x x August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 91 Advance Information DC Characteristics (16Mb pSRAM Page Mode) Page Mode Performance Grade Density Symbol VCC VIH VIL IIL Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA 0.8 Vccq IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V 100 10 65 80 0.2 Vccq 25 mA V 0.2 Vccq 25 mA V 0.2 Vccq 25 mA V V 0.8 Vccq V 0.8 Vccq V Conditions Min 2.7 0.8 Vccq -0.2 -60 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V µA Min 2.7 0.8 Vccq -0.2 -65 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V µA Min 2.7 0.8 Vccq -0.2 -70 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V µA ILO 1 µA 1 µA 1 µA ISTANDBY IDEEP SLEEP µA 100 10 65 80 µA 100 10 65 80 µA µA µA µA µA µA µA µA µA µA IPAR 1/4 IPAR 1/2 92 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information DC Characteristics (32Mb pSRAM Page Mode) Page Mode Version Performance Grade Density Symbol VCC Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC Conditions C -65 32Mb pSRAM Min 2.7 Max 3.6 VCC + 0.2 0.4 Units V -60 32Mb pSRAM Min 2.7 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V E -65 32Mb pSRAM Min 2.7 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V -70 32Mb pSRAM Min 2.7 0.8 Vccq -0.2 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V VIH 1.4 V 0.8 Vccq V 0.8 Vccq V V VIL -0.2 V -0.2 V -0.2 V V IIL 0.5 µA µA µA µA ILO OE = VIH or Chip Disabled IOH = -1.0 mA 0.5 µA 1 µA 1 µA 1 µA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA 0.8 Vccq V 0.8 Vccq V 0.8 Vccq V 0.8 Vccq V VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA 0.2 V 0.2 Vccq V 0.2 Vccq mA 25 V 0.2 Vccq mA 25 V IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V 25 mA 25 mA ISTANDBY 100 10 µA 120 10 µA 120 10 µA 120 10 µA IDEEP SLEEP µA µA µA µA IPAR 1/4 IPAR 1/2 65 80 µA µA 75 90 µA µA 75 90 µA µA 75 90 µA µA August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 93 Advance Information DC Characteristics (64Mb pSRAM Page Mode) Page Mode Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V 120 10 65 80 0.2 Vccq 25 mA V 0.8 Vccq V Conditions Min 2.7 0.8 Vccq -0.2 -70 64Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 1 Units V V V µA µA ISTANDBY IDEEP SLEEP µA µA µA µA IPAR 1/4 IPAR 1/2 Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Operating Temperature 0.1 VCC to 0.9 VCC 5ns 0.5 VCC -25°C to +85°C 94 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Output Load Circuit VCC 14.5K I/O 14.5K 30 pF Output Load Figure 32. Output Load Circuit Power Up Sequence After applying power, maintain a stable power supply for a minimum of 200 µs after CE# > VIH. August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 95 Advance Information AC Characteristics (4Mb pSRAM Page Mode) Asynchronous Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 20 Min 70 70 70 20 70 -70 4Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 20 ns tohz toh 0 10 20 ns ns 96 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Asynchronous Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 7.5 ns Min 70 70 0 70 70 55 0 20 -70 4Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width x x x x Other tpa twpc tcp August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 97 Advance Information AC Characteristics (8Mb pSRAM Asynchronous) Asynchronous Version Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 5 5 5 0 20 Min 55 55 55 30 55 -55 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 5 5 5 0 25 Min 70 70 70 35 70 B -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 10 10 5 0 20 Min 70 70 70 20 70 C -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 20 ns 0 25 ns 0 20 ns tohz toh 0 10 20 ns ns 0 10 25 ns ns 0 10 20 ns ns 98 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Asynchronous Version Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chip select to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 40 0 5 x x ns Min 55 45 0 45 45 45 0 25 -55 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns 40 0 5 x x ns Min 70 55 0 55 55 55 0 25 ns ns 25 0 5 x x ns B -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns Min 70 70 0 70 70 55 0 20 C -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width x x x x x x x x x x x x Other tpa twpc tcp August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 99 Advance Information AC Characteristics (16Mb pSRAM Asynchronous) Asynchronous Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 5 5 5 0 25 Min 55 55 55 30 55 -55 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 5 5 5 0 25 Min 70 70 70 35 70 -70 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 25 ns 0 25 ns tohz toh 0 10 25 ns ns 0 10 25 ns ns 100 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Asynchronous Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 x x ns Min 55 50 0 50 50 50 0 25 -55 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns 25 0 5 x x ns Min 70 55 0 55 55 55 0 25 -70 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width x x x x x x x x Other tpa twpc tcp August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 101 Advance Information AC Characteristics (16Mb pSRAM Page Mode) Page Mode Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 5 Min 60 -60 16Mb pSRAM Max 20k 60 60 25 60 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 Min 65 -65 16Mb pSRAM Max 20k 65 65 25 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 Min 70 -70 16Mb pSRAM Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 5 ns 0 5 ns 0 5 ns tohz toh 0 5 5 ns ns 0 5 5 ns ns 0 5 5 ns ns 102 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Page Mode Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 20 0 5 7.5 ns Min 60 50 0 50 50 50 0 5 -60 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns Min 65 60 0 60 60 50 0 5 -65 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns Min 70 60 0 60 60 50 0 5 -70 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width 25 20k 25 ns ns ns ns 25 20k 25 ns ns ns ns 25 20k 25 ns ns ns ns Other tpa twpc tcp 25 10 20k 25 10 20k 25 10 20k August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 103 Advance Information AC Characteristics (32Mb pSRAM Page Mode) Page Mode Version Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 20 C -65 32Mb pSRAM Min 65 Max 20k 65 65 20 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 -60 32Mb pSRAM Min 60 Max 20k 60 60 25 60 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 E -65 32Mb pSRAM Min 65 Max 20k 65 65 25 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 -70 32Mb pSRAM Min 70 Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 20 ns 0 5 ns 0 5 ns 0 5 ns tohz toh 0 5 20 ns ns 0 5 5 ns ns 0 5 5 ns ns 0 5 5 ns ns 104 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Page Mode Version Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 7.5 ns C -65 32Mb pSRAM Min 65 55 0 55 55 55 0 5 20k Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns -60 32Mb pSRAM Min 60 50 0 50 50 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns E -65 32Mb pSRAM Min 65 60 0 60 60 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns -70 32Mb pSRAM Min 70 60 0 60 60 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width 25 20k 25 ns ns ns ns 25 20k 25 ns ns ns ns 25 20k 25 ns ns ns ns 25 20k 25 ns ns ns ns Other tpa twpc tcp 25 10 20k 25 10 20k 25 10 20k 25 10 20k August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 105 Advance Information AC Characteristics (64Mb pSRAM Page Mode) Page Mode Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 5 Min 70 -70 64Mb pSRAM Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns Read tblz tolz thz tbhz 0 5 ns tohz toh 0 5 5 ns ns 106 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Page Mode Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 20 0 5 7.5 ns Min 70 60 0 60 60 50 0 5 20k -70 64Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns Write twr twhz tdw tdh tow tow tpc Page read cycle Page address access time Page write cycle Chip select high pulse width 20 20k 20 ns ns ns ns Other tpa twpc tcp 20 10 20k Timing Diagrams Read Cycle tRC Address tAA tOH Data Out Previous Data Valid Data Valid Figure 33. August 30, 2004 pSRAM_Type01_12_A1 Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH) pSRAM Type 1 107 Advance Information tRC Address tAA CE# tCO tLZ tOE OE# tOLZ tLB, tUB LB#, UB# tBLZ High-Z Data Out tBHZ Data Valid tOHZ tHZ Figure 34. Timing Waveform of Read Cycle (WE# = ZZ# = VIH) 108 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information tPGMAX Page Address (A4 - A20) tRC tPC Word Address (A0 - A3) tAA CE# tPA tHZ tCO tOE OE# tOLZ LB#, UB# tLB, tUB tOHZ tBHZ High-Z Data Out tBLZ, Figure 35. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH) August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 109 Advance Information Write Cycle tWC Addr es s tAW CE# tWR tCW tBW LB#, UB# tAS WE# tWP tDW High-Z Dat a In tDH Data Valid tWHZ High-Z tOW Da ta Out Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH) tWC Ad dres s tAW tWR CE# tAS tBW LB#, UB# tCW tWP WE# tDW Dat a In tDH Data Valid tWHZ Da ta O ut High-Z Figure 37. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH) 110 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information tPGMAX Page A ddr es s (A4 - A 20) tWC Wor d A ddr es s (A0 - A3 ) tPWC tAS tCW CE# tWP WE# tLBW, tUBW LB#, UB# tDW High-Z Dat a Out tDH tPDW tPDH tPDW tPDH Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH) Power Savings Modes (For 16M Page Mode, 32M and 64M Only) There are several power savings modes. Partial Array Self Refresh Temperature Compensated Refresh (64M) Deep Sleep Mode Reduced Memory Size (32M, 16M) The operation of the power saving modes ins controlled by the settings of bits contained in the Mode Register. This definition of the Mode Register is shown in Figure 39 and the various bits are used to enable and disable the various low power modes as well as enabling Page Mode operation. The Mode Register is set by using the timings defined in Figure xxx. Partial Array Self Refresh (PAR) In this mode of operation, the internal refresh operation can be restricted to a 16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is determined by the respective bit settings in the Mode Register. The register settings for the PASR operation are defined in Table xxx. In this PASR mode, when ZZ# is active low, only the portion of the array that is set in the register is re- August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 111 Advance Information freshed. The data in the remainder of the array will be lost. The PASR operation mode is only available during standby time (ZZ# low) and once ZZ# is returned high, the device resumes full array refresh. All future PASR cycles will use the contents of the Mode Register that has been previously set. To change the address space of the PASR mode, the Mode Register must be reset using the previously defined procedures. For PASR to be activated, the register bit, A4 must be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be activated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero (0), PASR will not be activated. Temperature Compensated Refresh (for 64Mb) In this mode of operation, the internal refresh rate can be optimized for the operation temperature used and this can then lower standby current. The DRAM array in the PSRAM must be refreshed internally on a regular basis. At higher temperatures, the DRAM cell must be refreshed more often than at lower temperatures. By setting the temperature of operation in the Mode Register, this refresh rate can be optimized to yield the lowest standby current at the given operating temperature. There are four different temperature settings that can be programmed in to the PSRAM. These are defined in Figure 39. Deep Sleep Mode In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 register bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep will be entered 10 µs after ZZ# is brought low. The device will remain in this mode as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep Sleep will not be activated. Reduced Memory Size (for 32M and 16M) In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the following timings and the bit settings in the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ transitioning high and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA register must be reset using the previously defined procedures. While operating in the RMS mode, the unselected portion of the array may not be used. Other Mode Register Settings (for 64M) The Page Mode operation can also be enabled and disabled using the Mode Register. Register bit A7 controls the operation of Page Mode and setting this bit to a one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode operation is disabled. 112 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information 64 Mb 32 Mb / 16 Mb A21 - A8 A7 A6 A5 A4 A3 A2 A1 A0 Reserved Must set to all 0 Temp Compensated Refresh 1 0 0 1 0 = 15oC 1 = 45oC 0 = 70oC 1 = 85oC (default) Array Mode for ZZ# 0 = PAR (default) 1 = RMS 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 PAR Section 1 = Top 1/4 array 0 = Top 1/2 array 1 = Top 3/4 array 0 = No PAR 1 = Bottom 1/4 array 0 = Bottom 1/2 array 1 = Bottom 3/4 array 0 = Full array (default) Page Mode 0 = Page Mode Disabled (default) 1 = Page Mode Enabled Deep Sleep Enable/Disable 0 = Deep Sleep Enabled 1 = Deep Sleep Disabled (default) Figure 39. Mode Register tWC Address tAS CE# tWP WE# tCDZZ ZZ# tZZWE tAW tWR Figure 40. Mode Register Update Timings (UB#, LB#, OE# are Don’t Care) August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 113 Advance Information tZZMIN ZZ# tCDZZ tR CE# Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M) tWC A4 tAS CE# tWP WE# tBW tZZMIN tAW tWR LB#, UB# ZZ# tZZWE tR Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M) Mode Register Update and Deep Sleep Timings Item Chip deselect to ZZ# low ZZ# low to WE# low Write register cycle time Chip enable to end of write Address valid to end of write Write recovery time Address setup time Write pulse width Deep Sleep Pulse Width Deep Sleep Recovery Notes: 1. Minimum cycle time for writing register is equal to speed grade of product. Symbol tCDZZ tZZWE tWC tCW tAW tWR tAS tWR tZZMIN tR Min 5 10 70/85 70/85 70/85 0 0 40 10 200 Max Unit ns Note 500 ns ns ns ns ns ns ns µs µs 1 1 1 114 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Address Patterns for PASR (A4=1) (64M) A2 1 1 1 1 0 0 0 0 A1 1 1 0 0 1 1 0 0 A0 1 0 1 0 1 0 1 0 Active Section Top quarter of die Top half of die Reserved No PASR Bottom quarter of die Bottom half of die Reserved Full array 000000h-3FFFFFh 4Mb x 16 64Mb None 000000h-0FFFFFh 000000h-1FFFFFh 0 1Mb x 16 2Mb x 16 0 16Mb 32Mb Address Space 300000h-3FFFFFh 200000h-3FFFFFh Size 1Mb x 16 2Mb x 16 Density 16Mb 32Mb August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 115 Advance Information Deep ICC Characteristics (for 64Mb) Item Symbol Test Array Partition None PASR Mode Standby Current IPASR VIN = VCC or 0V, Chip Disabled, tA = 85°C 1/4 Array 1/2 Array Full Array Typ Max 10 60 80 120 µA Unit Item Symbol Max Temperature 15°C Typ Max 50 60 80 120 Unit Temperature Compensated Refresh Current ITCR 45°C 70°C 85°C µA Item Deep Sleep Current Symbol IZZ Test VIN = VCC or 0V, Chip in ZZ# mode, tA = 25°C Typ Max 10 Unit µA Address Patterns for PAR (A3= 0, A4=1) (32M) A2 0 0 x 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full die One-quarter of die One-half of die Address Space 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh Size 512Kb x 16 1Mb x 16 2Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 32Mb 8Mb 16Mb Address Patterns for RMS (A3 = 1, A4 = 1) (32M) A2 0 0 1 1 A1 1 1 1 1 A0 1 0 1 0 Active Section One-quarter of die One-half of die One-quarter of die One-half of die Address Space 000000h - 07FFFFh 000000h - 0FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh Size 512Kb x 16 1Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 8Mb 16Mb 116 pSRAM Type 1 pSRAM_Type01_12_A1 August 30, 2004 Advance Information Low Power ICC Characteristics (32M) Item Symbol Test VIN = VCC or 0V, Chip Disabled, tA= 85 C o Array Partition 1/4 Array 1/2 Array 8Mb Device o Typ Max 75 90 75 90 10 Unit µA µA µA µA µA PAR Mode Standby Current IPAR RMS Mode Standby Current IRMSSB Deep Sleep Current IZZ VIN = VCC or 0V, Chip Disabled, tA= 85 C VIN = VCC or 0V, Chip in ZZ mode, tA= 85oC 16Mb Device Address Patterns for PAR (A3= 0, A4=1) (16M) A2 0 0 x 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full die One-quarter of die One-half of die Address Space 00000h - 0FFFFh 00000h - 7FFFFh 00000h - FFFFFh C0000h - FFFFh 80000h - 1FFFFFh Size 256Kb x 16 512Kb x 16 1Mb x 16 256Kb x 16 512Kb x 16 Density 4Mb 8Mb 16Mb 4Mb 8Mb Address Patterns for RMS (A3 = 1, A4 = 1) (16M) A2 0 0 1 1 A1 1 1 1 1 A0 1 0 1 0 Active Section One-quarter of die One-half of die One-quarter of die One-half of die Address Space 00000h - 0FFFFh 00000h - 7FFFFh C0000h - FFFFFh 80000h - FFFFFh Size 256Kb x 16 512Kb x 16 256Kb x 16 512Kb x 16 Density 4Mb 8Mb 4Mb 8Mb Low Power ICC Characteristics (16M) Item PAR Mode Standby Current Symbol IPAR Test VIN = VCC or 0V, Chip Disabled, tA= 85 C o Array Partition 1/4 Array 1/2 Array 4Mb Device o Typ Max 65 80 65 80 10 Unit µA RMS Mode Standby Current IRMSSB IZZ VIN = VCC or 0V, Chip Disabled, tA= 85 C VIN = VCC or 0V, Chip in ZZ# mode, tA= 85oC 8Mb Device µA Deep Sleep Current µA August 30, 2004 pSRAM_Type01_12_A1 pSRAM Type 1 117 Advance Information Type 2 pSRAM 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) 128Mbit (8M Word x 16-bit) Features Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM Product Information Density 16Mb 16Mb 32Mb 32Mb 64Mb 64Mb 128Mb VCC Range 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V Standby (ISB1, Max.) 80 µA 80 µA 100 µA 100 µA TBD TBD TBD Operating (ICC2, Max.) 30 mA 35 mA 35 mA 40 mA TBD TBD TBD Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS and Page Mode Pin Description Pin Name CS1#, CS2 OE# WE# LB#, UB# A0-A19 (16M) A0-A20 (32M) A0-A21 (64M) A0-A22 (128M) I/O0-I/O15 VCC/VCCQ VSS/VSSQ NC DNU Chip Select Output Enable Write Enable Lower/Upper Byte Enable Description I/O I I I I Address Inputs I Data Inputs/Outputs Power Supply Ground Not Connection Do Not Use I/O — — — — 118 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information Power Up Sequence 1. 2. Apply power. Maintain stable power (VCC min.=2.7V) for a minimum 200 µs with CS1#=high or CS2=low. Timing Diagrams Power Up Min. 200 s VCC(Min) VCC CS1# CS2 Power Up Mode Normal Operation Figure 43. Notes: Power Up 1 (CS1# Controlled) 1. After VCC reaches VCC(Min.), wait 200 µs with CS1# high. Then the device gets into the normal operation. VCC CS1# Power Up Mode ~ ~ CS2 ~~ ~~ ~ ~ n VCC(Mi ) Min. 200 µs Normal Operation Figure 44. Notes: Power Up 2 (CS2 Controlled) 1. After VCC reaches VCC(Min.), wait 200 µs with CS2 low. Then the device gets into the normal operation. June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 119 Advance Information Functional Description Mode Deselected Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Standby Active Active Active Active Active Active Active Active Legend:X = Don’t care (must be low or high state). Absolute Maximum Ratings Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than one second may affect reliability. Symbol VIN , VOUT VCC PD TA Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -40 to 85 Unit V V W °C DC Recommended Operating Conditions Symbol VCC VSS VIH VIL Notes: 1. TA=-40 to 85°C, unless otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width ≤ 20ns. 3. Undershoot: -1.0V in case of pulse width ≤ 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min 2.7 0 2.2 -0.2 (Note 3) Typ 2.9 0 — — Max 3.1 0 VCC + 0.3 (Note 2) 0.6 Unit V 120 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information Capacitance (Ta = 25°C, f = 1 MHz) Symbol CIN CIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min — — Max 8 10 Unit pF pF Note: This parameter is sampled periodically and is not 100% tested. DC and Operating Characteristics Common Item Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Symbol ILI ILO VOL VOH Test Conditions VIN=VSS to VCC CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC IOL=2.1mA IOH=-1.0mA Min -1 -1 — 2.4 Typ — — — — Max 1 1 0.4 — Unit µA µA V V June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 121 Advance Information 16M pSRAM Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up. Min Typ Max Unit — — 7 mA Async — — 30 mA 35 mA Standby Current (CMOS) ISB1 (Note 1) — — 80 mA 32M pSRAM Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up. Min Typ Max Unit — — 7 mA Async — — 35 mA 40 mA Standby Current (CMOS) ISB1 (Note 1) — — 100 mA 122 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information 64M pSRAM Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) Notes: 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up. Min Typ Max Unit — — TBD mA Async — — TBD mA TBD mA Standby Current (CMOS) ISB1 (Note 1) — — TBD mA 128M pSRAM Item Symbol ICC1 ICC2 Test Conditions Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Min Typ Max Unit — — TBD mA Average Operating Current — — TBD mA Other inputs=0-VCC Standby Current (CMOS) ISB1 (Note 1) 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or 2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled) Notes: — — TBD mA 1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms from the time when standby mode is set up. June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 123 Advance Information AC Operating Conditions Test Conditions (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See Figure 45): CL=50pF Dout CL Figure 45. Note: Including scope and jig capacitance. Output Load 124 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information AC Characteristics (Ta = -40°C to 85°C, VCC = 2.7 to 3.1 V) Speed Bins 70ns Symbol tRC tAA tCO tOE tBA tLZ Read tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW Write tBW tWP tWR tWHZ tDW tDH tOW Notes: 1. tWP (min)=70ns for continuous write operation over 50 times. Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Time Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Min 70 — — — — 10 10 5 0 0 0 5 25 — 70 60 0 60 60 55 (Note 1) 0 0 30 0 5 Max — 70 70 35 70 — — — 25 25 25 — — 20 — — — — — — — 25 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 125 Advance Information Timing Diagrams Read Timings tRC Address tOH Data Out Previous Data Valid tAA Data Valid Figure 46. Timing Waveform of Read Cycle(1) Notes: 1. Address Controlled, CS1#=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL. tRC Address tAA tOH CS1# tCO CS2 tHZ tBA UB#, LB# tBHZ tOE OE# tLZ tOLZ tBLZ Data Valid tOHZ Data out High-Z Figure 47. Notes: 1. WE#=VIH. Timing Waveform of Read Cycle(2) 126 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information Address1) Valid Address A1~A0 Valid Address Valid Address Valid Address Valid Address tAA tPC CS1# CS2 tCO OE# tOE DQ15~DQ0 High Z tPA Data Valid Data Valid Data Valid Data Valid tOHZ Figure 48. Timing Waveform of Page Cycle (Page Mode Only) Notes: 1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. tOE(max) is met only when OE# becomes enabled after tAA(max). If invalid address signals shorter than min. tRC are continuously repeated for over 4µs, the device needs a normal read timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4µs. Write Timings tWC Address tCW tWR CS1# CS2 tAW tBW tWP WE# tAS Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z UB#, LB# Figure 49. Write Cycle #1 (WE# Controlled) June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 127 Advance Information tWC Address tAS tCW tWR CS1# tAW CS2 tBW UB#, LB# tWP WE# tDW Data in Data Valid tDH Data out High-Z Figure 50. Write Cycle #2 (CS1# Controlled) tWC Address tAS tCW tWR CS1# tAW CS2 tBW UB#, LB# tWP(1) WE# tDW Data in Data Valid tDH Data out High-Z Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled) 128 Type 2 pSRAM pSRAM_Type02_15A1 June 25, 2004 Advance Information tWC Address tCW tWR CS1# tAW CS2 tBW UB#, LB# tAS WE# tDW Data in Data Valid tDH tWP Data out High-Z Figure 52. Notes: Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) 1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1# or WE# going high. June 25, 2004 pSRAM_Type02_15A1 Type 2 pSRAM 129 Advance Information pSRAM Type 7 16Mb (1M word x 16-bit) 32Mb (2M word x 16-bit) 64Mb (4M word x 16-bit) CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low Power SRAM Interface Features Asynchronous SRAM Interface Fast Access Time — tCE = tAA = 60ns max (16M) — tCE = tAA = 65ns max (32M/64M) 8 words Page Access Capability — tPAA = 20ns max (32M/64M) Low Voltage Operating Condition — VDD = +2.7V to +3.1V Wide Operating Temperature — TA = -30°C to +85°C Byte Control by LB and UB Various Power Down modes — Sleep (16M) — Sleep, 4M-bit Partial, or 8M-bit Partial (32M) — Sleep, 8M-bit Partial, or 16M-bit Partial (64M) Pin Description Pin Name A21 to A0 CE1# CE2# WE# OE# UB# LB# DQ16-9 DQ8-1 VDD VSS Description Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Upper Byte Control (Low Active) Lower Byte Control (Low Active) Upper Byte Data Input/Output Lower Byte Data Input/Output Power Supply Ground 130 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information Functional Description Mode Standby (Deselect) Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down L X X X L H H L H L CE2# H CE1# H WE# X H OE# X H LB# X X H H L L H H L L X UB# X X H L H L H L H L X A21-0 X Note 3 Valid Valid Valid Valid Valid Valid Valid Valid X DQ8-1 High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid Input Valid Input Valid High-Z DQ16-9 High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid Invalid Input Valid High-Z Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. Notes: 1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of 1ms limitation. 2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for details. 3. Can be either VIL or VIH but must be valid before Read or Write. Power Down (for 32M, 64M Only) Power Down The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the device in power-down mode and maintains the low-power idle state as long as CE2 is kept Low. CE2 High resumes the device from power-down mode. These devices have three power-down modes. These can be programmed by series of read/write operation. Each mode has following features. 32M Mode Sleep (default) 4M Partial 8M Partial Retention Data No 4M bit 8M bit Retention Address N/A 00000h to 3FFFFh 00000h to 7FFFFh Mode Sleep (default) 8M Partial 16M Partial 64M Retention Data No 8M bit 16M bit Retention Address N/A 00000h to 7FFFFh 00000h to FFFFFh The default state is Sleep and it is the lowest power consumption but all data is lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 131 Advance Information Power Down Program Sequence The program requires 6 read/write operations with a unique address. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 3FFFFFh (MSB) 3FFFFFh 3FFFFFh 3FFFFFh 3FFFFFh Address Key Data Read Data (RDa) RDa RDa Don’t Care (X) X Read Data (RDb) The first cycle reads from the most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the program is cancelled, and the data written by the second or third cycle is valid as a normal write operation. The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles is “don’t care.” If the fourth or fifth cycles are written into different address, the program is also cancelled but write data might not be written as normal write operation. The last cycle is to read from specific address key for mode selection. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array can be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used. Address Key The address key has following format. Mode 32M Sleep (default) 4M Partial 8M Partial N/A 64M Sleep (default) N/A 8M Partial 16M Partial A21 1 1 1 1 A20 1 1 0 0 Address A19 1 0 1 0 A18 - A0 1 1 1 1 Binary 3FFFFFh 37FFFFh 2FFFFFh 27FFFFh 132 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information Absolute Maximum Ratings Item Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage temperature Symbol VDD VIN, VOUT IOUT TSTG Value -0.5 to +3.6 -0.5 to +3.6 ±50 -55 to +125 Unit V V mA °C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions (See Warning Below) Parameter Supply Voltage High Level Input Voltage (Note 1) High Level Input Voltage (Note 1) Ambient Temperature Notes: 1. Maximum DC voltage on input and I/O pins is VDD+0.2V. During voltage transitions, inputs can positive overshoot to VDD+1.0V for periods of up to 5 ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot VSS to -1.0V for periods of up to 5ns. Symbol VDD VSS VIH VIL TA Min 2.7 0 VDD 0.8 -0.3 -30 Max 3.1 0 VDD+0.2 VDD 0.2 85 Unit V V V V °C WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. Package Capacitance Test conditions: TA = 25°C, f = 1.0 MHz Symbol CIN1 CIN2 CIO Description Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Test Setup VIN = 0V VIN = 0V VIO = 0V Typ — — — Max 5 5 8 Unit pF pF pF November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 133 Advance Information DC Characteristics (Under Recommended Conditions Unless Otherwise Noted) 16M Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS VDD Power Down Current IDDP4 IDDP8 IDDP16 IDDS VDD Standby Current IDDS1 IDDA1 IDDA2 VDD = VDD max., VIN = VIH or VIL CE1 = CE2 = VIH VDD = VDD max., VIN ≤ 0.2V or VIN ≥ VDD – 0.2V, CE1 = CE2 ≥ VDD – 0.2V VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA VDD = VDD max., VIN = VIH or VIL, CE2 ≤ 0.2 V Test Conditions VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD(min), IOH = –0.5mA IOL = 1mA SLEEP 4M Partial 8M Partial 16M Partial — Min. Max. 32M Min. Max. 64M Min. Max. Unit µA µA V V µA µA µA µA mA -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 2.2 — — 0.4 10 N/A N/A N/A 1 — 2.4 — — — — — 0.4 10 40 50 N/A 1.5 — — — 2.4 — — — 0.4 10 N/A 80 100 1.5 TA< +85°C TA< +40°C tRC / tWC = min. tRC / tWC = 1µs — 100 — 80 — 170 90 — — 20 3 — — 30 3 — — 40 5 µA µA mA mA VDD Active Current VDD Page Read Current Notes: IDDA3 VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA, tPRC = min. N/A — 10 — 10 mA 1. All voltages are referenced to VSS. 2. DC Characteristics are measured after following POWER-UP timing. 3. IOUT depends on the output load conditions. 134 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information AC Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation Parameter Read Cycle Time CE1# Access Time OE# Access Time Address Access Time LB# / UB# Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1# Low to Output Low-Z OE# Low to Output Low-Z LB# / UB# Low to Output Low-Z CE1# High to Output High-Z OE# High to Output High-Z LB# / UB# High to Output High-Z Address Setup Time to CE1# Low Address Setup Time to OE# Low Address Invalid Time Address Hold Time from CE1# High Address Hold Time from OE# High WE# High to OE# Low Time for Read CE1# High Pulse Width Symbol tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP 5 5 0 0 — — — −6 10 — -6 -6 10 10 16M Min. 70 — — — — N/A N/A — — — — 20 20 20 — — 10 — — 1000 — Max. 1000 60 40 60 30 Min. 65 — — — — — 20 5 5 0 0 — — — –6 10 — –6 –6 12 12 32M Max. 1000 65 40 65 30 20 1000 — — — — 20 14 20 — — 10 — — — — Min. 65 — — — — — 20 5 5 0 0 — — — –6 10 — –6 –6 25 12 64M Max. 1000 65 40 65 30 20 1000 — — — — 20 14 20 — — 10 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 5, 8 9 Notes 1, 2 3 3 3, 5 3 3,6 1, 6, 7 3 4 4 4 3 3 3 Notes: 1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system operation, please contact local Spansion representative for the relaxation of 1µs limitation. 2. Address should not be changed within minimum tRC. 3. The output load 50 pF with 50 ohm termination to VDD x 0.5 (16M), The output load 50 pF (32M and 64M). The output load 5pF. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. tRC(min) and tPRC(min) must be satisfied. 10. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read can become longer by the amount of subtracting the actual value from the specified minimum value. 4. 5. 6. 7. November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 135 Advance Information AC Characteristics Write Operation 16M Parameter Write Cycle Time Address Setup Time CE1# Write Pulse Width WE# Write Pulse Width LB#/UB# Write Pulse Width LB#/UB# Byte Mask Setup Time LB#/UB# Byte Mask Hold Time Write Recovery Time CE1# High Pulse Width WE# High Pulse Width LB#/UB# High Pulse Width Data Setup Time Data Hold Time OE# High to CE1# Low Setup Time for Write OE# High to Address Setup Time for Write LB# and UB# Write Pulse Overlap Notes: 1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please contact local Spansion representative for the relaxation of 1µs limitation. 2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. 7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level. 8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. 9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z. 32M Max. Min. 65 0 40 40 40 –5 –5 0 12 7.5 12 12 0 –5 0 30 Max. 1000 — — — — — — — — 1000 1000 — — — — — Min. 65 0 40 40 40 –5 –5 0 12 7.5 12 12 0 –5 0 30 64M Max. 1000 — — — — — — — — 1000 1000 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 9 7 Notes 1,2 3 3 3 3 4 5 6 Symbol tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO Min. 70 0 45 45 45 -5 -5 0 10 7.5 10 15 0 -5 0 30 1000 — — — — — — — — 1000 1000 — — — — — 136 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information AC Characteristics Power Down Parameters 16M Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE1# High Hold Time following CE2 High after Power Down Exit [not in SLEEP mode] CE1# High Setup Time following CE2 High after Power Down Exit Notes: 1. Applicable also to power-up. 2. Applicable when 4Mb and 8Mb Partial modes are programmed. 32M Min. 10 65 300 1 — 0 Max. — — — — — 64M Min. 10 65 300 1 0 Max. — — — — — Unit ns ns µs µs ns 1 2 1 Note Symbol tCSP tC2LP tCHH tCHHP tCHS Min. 10 80 300 Max. — — — N/A 0 Other Timing Parameters 16M Parameter CE1# High to OE# Invalid Time for Standby Entry CE1# High to WE# Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1# High Hold Time following CE2 High after Power-up Input Transition Time Notes: 1. Some data might be written into any address location if tCHWX(min) is not satisfied. 2. The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC specification of some of the timing parameters. 32M Min. 10 10 50 300 1 Max. — — — — 25 64M Min. 10 10 50 300 1 Max. — — — — 25 Unit ns ns µs µs ns 2 1 Note Symbol tCHOX tCHWX tC2LH tCHH tT Min. 10 10 50 300 1 Max. — — — — 25 November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 137 Advance Information AC Characteristics AC Test Conditions Symbol VIH VIL VREF tT Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Between VIL and VIH Description Test Setup Value VDD * 0.8 VDD * 0.2 VDD * 0.5 5 Unit V V V ns Note AC Measurement Output Load Circuits VDD *0.5 V VDD 0.1 µF VSS DEVICE UNDER TEST 50 pF 50 ohm OUT Figure 53. AC Output Load Circuit – 16 Mb VDD 0.1µF VSS DEVICE UNDER TEST 50pF OUT Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb 138 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information Timing Diagrams Read Timings tRC ADDRESS tASC CE1# tOE OE# tOHZ tBA LB#/UB# tBLZ DQ (Output) tOLZ tCLZ Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS VALID tCE tCHAH tCP tCHZ tASC tBHZ VALID DATA OUTPUT tOH Figure 55. Read Timing #1 (Basic Timing) tRC ADDRESS ADDRESS VALID tAA CE1# Low tASO OE# tOE tAx tRC ADDRESS VALID tAA tOHAH LB#/UB# tOLZ DQ (Output) VALID DATA OUTPUT Note: This timing diagram assumes CE2=H and WE#=H. tOH tOH tOHZ VALID DATA OUTPUT Figure 56. Read Timing #2 (OE# Address Access November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 139 Advance Information tAX ADDRESS tAA CE1#, OE# Low tBA LB# tRC ADDRESS VALID tAx tBA tBA UB# tBLZ DQ1-8 (Output) DQ9-16 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH VALID DATA OUTPUT Note: This timing diagram assumes CE2=H and WE#=H. Figure 57. Read Timing #3 (LB#/UB# Byte Access) tRC ADDRESS (A21-A3) tRC ADDRESS (A2-A0) tASC CE1# OE# LB#/UB# tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access) Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS VALID tPRC ADDRESS VALID tPRC ADDRESS VALID tPRC ADDRESS VALID ADDRESS VALID tPAA tPAA tPAA tCHAH tCHZ tCE tOH tOH tOH tOH VALID DATA OUTPUT (Page Access) Figure 58. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only) 140 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information tRC ADDRESS (A21-A3) ADDRESS (A2-A0) CE1# ADDRESS VALID tRC ADDRESS VALID tAX tRC ADDRESS VALID tAx tPRC ADDRESS VALID tRC ADDRESS VALID tPRC ADDRESS VALID tAA Low tASO OE# tBA LB#/UB# DQ (Output) tOLZ tBLZ tOH tOE tPAA tAA tPAA tOH tOH tOH VALID DATA OUTPUT (Normal Access) Notes: 1. This timing diagram assumes CE2=H and WE#=H. 2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low. VALID DATA OUTPUT (Page Access) Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only) Write Timings tWC ADDRESS tAS CE1# tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT Note: This timing diagram assumes CE2=H. ADDRESS VALID tCW tWR tCP tWP tWR tWHP tBW tWR tBHP tAS tAS tAS tDS tDH Figure 60. Write Timing #1 (Basic Timing) November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 141 Advance Information tWC ADDRESS tOHAH CE1# Low tAS WE# tWHP LB#, UB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT Note:This timing diagram assumes CE2=H. tWC ADDRESS VALID ADDRESS VALID tWP tWR tAS tWP tWR tDS tDH tDS tDH VALID DATA INPUT Figure 61. Write Timing #2 (WE# Control) tWC ADDRESS CE1# Low tAS WE# tWR LB# tBS UB# tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input) Note: This timing diagram assumes CE2=H and OE#=H. tWC ADDRESS VALID ADDRESS VALID tWP tWHP tAS tWP tBH tBS tBH tDH tWR tDS tDH Figure 62. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control) 142 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information tWC ADDRESS CE1# Low tWR WE# tAS LB# tBS UB# tDS DQ1-8 (Input) DQ9-16 (Input) tDH tBH tAS tBW tWHP tBS ADDRESS VALID tWC ADDRESS VALID tWR tBH tBW VALID DATA INPUT tDS tDH VALID DATA INPUT Note: This timing diagram assumes CE2=H and OE#=H. Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) tWC ADDRESS CE1# Low ADDRESS VALID tWC ADDRESS VALID WE# tAS LB# tBWO DQ1-8 (Input) tAS UB# tDS DQ9-16 (Input) tDH tDS tDH tBW tWR tBHP tDS tDH tAS tBW tWR VALID DATA INPUT VALID DATA INPUT tBW tWR tBHP tAS tBWO tBW tDS tWR tDH VALID DATA INPUT VALID DATA INPUT Note: This timing diagram assumes CE2=H and OE#=H. Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 143 Advance Information Read/Write Timings tWC ADDRESS tCHAH CE1# tCP WE# tCP tAS WRITE ADDRESS tCW tWR tASC tRC READ ADDRESS tCE tCHAH UB#, LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. Write address is valid from either CE1# or WE# of last falling edge. tDS tDH tCLZ tOH WRITE DATA INPUT Figure 65. Read/Write Timing #1-1 (CE1# Control) tWC ADDRESS tCHAH CE1# tCP tWP WE# tCP tAS WRITE ADDRESS tWR tASC tRC READ ADDRESS tCE tCHAH UB#, LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence. tOE tDS tDH tOLZ tOH WRITE DATA INPUT READ DATA OUTPUT Figure 66. 144 Read / Write Timing #1-2 (CE1#/WE#/OE# Control) pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information tWC ADDRESS tOHAH CE1# Low tAS WE# tOES tWP tWR WRITE ADDRESS tRC READ ADDRESS tAA tOHAH UB#, LB# tASO OE# tOHZ tOH DQ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. CE1# can be tied to Low for WE# and OE# controlled operation. tOE tOHZ tOH tWHOL tDS tDH tOLZ WRITE DATA INPUT READ DATA OUTPUT Figure 67. Read / Write Timing #2 (OE#, WE# Control) tWC ADDRESS WRITE ADDRESS tRC READ ADDRESS tAA CE1# Low tOHAH tOHAH WE# tOES UB#, LB# tBHZ OE# tOH DQ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. CE1# can be tied to Low for WE# and OE# controlled operation. tAS tBW tWR tBA tASO tWHOL tDS tDH tBLZ tBHZ tOH WRITE DATA INPUT READ DATA OUTPUT Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 145 Advance Information CE1# tCHS tC2LH CE2 tCHH VDD 0V VDD min Note: The tC2LH specifies after VDD reaches specified minimum level. Figure 69. Power-up Timing #1 CE1# tCHH CE2 VDD 0V VDD min Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2. Figure 70. Power-up Timing #2 CE1# tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP) Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset. Figure 71. Power Down Entry and Exit Timing 146 pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004 Advance information CE1# tCHOX OE# tCHWX WE# Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for Standby mode from CE1# Low to High transition. Figure 72. Standby Entry Timing after Read or Write tRC ADDRESS MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Key*2 tCP CE1# tCP tCP tCP tCP tCP*3 OE# WE# LB#, UB# DQ*3 RDa Cycle #1 RDa Cycle #2 RDa Cycle #3 X Cycle #4 X Cycle #5 RDb Cycle #6 Notes: 1. The all address inputs must be High from Cycle #1 to #5. 2. The address key must confirm the format specified in page 132. If not, the operation and data are not guaranteed. 3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation. Figure 73. Power Down Program Timing (for 32M/64M Only) November 2, 2004 pSRAM_Type07_13_A1 pSRAM Type 7 147 Advance Information Revision Summary Revision A0 (June 9, 2004) Initial release. Revision A1 (July 19, 2004) Global Change Change all instances of FASL to Spansion Added Colophon text. “Product Selector Guide” on page 2 Replaced “S71PL129JA0-9Z” with “S71PL129JA0-9P”. “Ordering Information” on page 9 In Model Number section replaced pSRAM part number with “See valid combinations table”. Revision A2 (July 21, 2004) “Connection Diagram” on page 7 Changed Row D of pinout for accuracy. Added the following note: “May be shared depending on density:A21 is shared for the 64M pSRAM configuration;A20 is shred for the 32M pSRAM configuration; A19 is shared for the 16M pSRAM configuration. Revision A3 (October 18, 2004) Core Flash Module Replaced core flash module from S29PL127J_064J_032J_MCP_00_A1_E to S29PL129J_MCP_00_A0 Revision A4 (November 30, 2004) Product Selector Guide Added a new model number. Valid Combinations Table Whole table updated with new OPNs. Revision A5 (December 23, 2004) Connection Diagram Updated pin L5. Valid Combinations Table Added a note to the bottom of the table. 148 Revision Summary S71PL129Jxx_00_A5_E December 23, 2004 Advance Information Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright ©2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. December 23, 2004 S71PL129Jxx_00_A5_E Revision Summary 149