S71PL256NB0HAW5B3

S71PL-N MirrorBitTM MCPs S71PL256N, S71PL127N, S71PL129N 256/128/128 Megabit (16/8/8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory S71PL-N MirrorBitTM MCPs Cover Sheet Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S71PL-N_00 Revision A Amendment 9 Issue Date December 8, 2006 Data Sheet Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office. ii S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 S71PL-N MirrorBitTM MCPs S71PL256N, S71PL127N, S71PL129N 256/128/128 Megabit (16/8/8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory Data Sheet Features Speed – Flash: 70 ns – pSRAM: 70 ns S71PL129NC0 S71PL127NB0 S71PL127NC0 8.0 x 11.6 x 1.2 mm Packages – 84-Ball Fine-Pitch Ball Grid Array (FBGA) S71PL256NC0 S71PL256ND0 – 64 Ball Fine-Pitch Ball Grid Array (FBGA) S71PL129NB0 Speed – Flash: 70 ns – pSRAM: 70 ns Operating Temperature Range – Temperature Range of –25°C to +85°C General Description This document contains information for the S71PL-N MirrorBit MCP product. For detailed specifications, please refer to the individual data sheets: Document S29PL-N 32M pSRAM Type 8 32M pSRAM Type 7 32M pSRAM Type 2 64M pSRAM Type 2 64M pSRAM Type 8 128M pSRAM Type 2 Publication Identification Number (PID) S29PL-N_00 pSRAM_31 pSRAM_29 pSRAM_19 pSRAM_20 pSRAM_32 pSRAM_15 Publication Number S71PL-N_00 Revision A Amendment 9 Issue Date December 8, 2006 Data Sheet 1. Flash/RAM Combinations Table pSRAM Density 32 Mb PL127N Flash Density PL129N PL256N S71PL127NB0 S71PL129NB0 64 Mb S71PL127NC0 S71PL129NC0 S71PL256NC0 S71PL256ND0 128 Mb 2. Product Selector Guide Device S71PL127NB0 S71PL127NB0 S71PL127NB0 S71PL127NC0 S71PL127NC0 S71PL129NB0 S71PL129NB0 S71PL129NB0 S71PL129NC0 S71PL129NC0 S71PL256NC0 S71PL256NC0 S71PL256ND0 pSRAM Density 32 Mb 32 Mb 32 Mb 64 Mb 64 Mb 32 Mb 32 Mb 32 Mb 64 Mb 64 Mb 64 Mb 64 Mb 128 Mb pSRAM Type pSRAM Type 2 pSRAM Type 7 pSRAM Type 8 pSRAM Type 2 pSRAM Type 8 pSRAM Type 2 pSRAM Type 7 pSRAM Type 8 pSRAM Type 2 pSRAM Type 8 pSRAM Type 2 pSRAM Type 8 pSRAM Type 2 2 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 Data Sheet 3. Ordering Information The order number is formed by a valid combinations of the following: S71PL 256 N C0 HF W 5B 0 Packing Type 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel Model Number (VIO Range, Package Type) Refer to the Valid Combinations table below Temperature Range W = Wireless (–25°C to +85°C) Package Type & Material Set HA = MCP BGA, 1.2 mm height, 0.8 mm pitch, Lead (Pb)-free Compliant package HF = MCP BGA, 1.2 mm height, 0.8 mm pitch, Lead (Pb)-free package pSRAM Density B0 = 32 Mb pSRAM C0 = 64 Mb pSRAM D0 = 128 Mb pSRAM Process Technology N = 110 nm MirrorBit™ Technology Flash Density 256= 256 Mb 129= 128 Mb (Dual CE#) 127= 128 Mb (Single CE#) Product Family S71PL =3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory 3.1 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table 3.1 Valid Combinations Base Ordering Part Number (2) Package & Temperature Model Number 4B S71PL127NB0 4U 4Z 4B S71PL127NC0 4U 4B S71PL129NB0 HAW, HFW 4U 4Z 4B S71PL129NC0 4U 5B S71PL256NC0 5U S71PL256ND0 5B Type 8 Type 2 Type 8 Type 2 TLA0848 x 11.6 x 1.2 mm, 84-ball TSB084 8 x 11.6 x 1.2, 84-ball 0, 2, 3 (1), (2) Type 8 Type 2 Type 8 Type 7 Type 2 70 ns 70 ns TLA064 8 x 11.6 x 1.2 mm, 64-ball Packing Type pSRAM Type Type 2 Type 8 Type 7 Type 2 TLA064 8 x 11.6 x 1.2 mm, 64-ball Flash Speed Option pSRAM Speed Options Package Name Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. 3. Contact factory for availability for any of the OPNs listed since RAM type availability may vary over time. December 8, 2006 S71PL-N_00_A9 S71PL-N MirrorBitTM MCPs 3 Data Sheet 4. Block Diagram VCCf VCC F1-CE# WP#/ACC RESET# Flash-only Address Shared Address OE# WE# VSS RY/BY# Flash 1 VCCS DQ15 to DQ0 VCC pSRAM/SRAM IO15-IO0 CE#s UB#s LB#s CE2 CE# UB# LB# Notes: 1. RY/BY# is an open drain output. 2. AMAX = A23 (PL256N), A22 (PL127N), A21 (PL129N). 4 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 Data Sheet 5. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S71PL-N. 5.1 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 5.2 S71PL256N TLA084/TSB084 Figure 5.1 84-ball Fine-Pitch Ball Grid Array (S71PL256N) A1 DNU B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 F-CE# J2 R-CE1# K2 RFU L2 RFU M1 DNU B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 RFU C4 B5 RFU C5 B6 RFU C6 WE# D6 R-CE2 E6 A20 F6 A23 G6 RFU H6 DQ4 J6 R-VCC K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU A10 DNU Legend: R-LB# WP#/ACC D4 R-UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU D5 F-RST# E5 RY/BY# F5 RFU G5 RFU H5 DQ3 J5 F-VCC K5 DQ11 L5 F-VCC X All Shared X Flash Only X DNU (Do Not Use) X pSRAM Only M10 DNU Note: Top view—balls facing down. The addresses that are shared vary by MCP combination as shown in the table below: Flash-only Addresses S71PL256NC0 S71PL256ND0 A23-A22 A23 Shared Addresses A21:A0 A22:A0 December 8, 2006 S71PL-N_00_A9 S71PL-N MirrorBitTM MCPs 5 Data Sheet Figure 5.2 TSB084 Physical Dimensions D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 L J H G F E D CB A E1 INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 84X 0.15 0.08 0.20 C 6 SIDE VIEW b M M CAB C C 0.08 C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TSB 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC 0.80 BSC 0.40 BSC 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10 E1,E10,F1,F10,G1,G10 H1,H10,J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3439 \ 16-038.22 \ 01.04.05 6 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 Data Sheet Figure 5.3 TLA084 Physical Dimensions D 0.15 C (2X) 10 9 8 7 6 5 4 A D1 eD SE 7 E1 E eE 3 2 1 INDEX MARK PIN A1 CORNER 10 MLKJ HG F EDC BA B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 6 0.20 C C 0.08 C SIDE VIEW b M CAB MC 84X 0.15 0.08 NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Øb eE eD SD / SE 0.35 TLA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10, E1,E10,F1,F10,G1,G10, H1,H10,J1,J10,K1,K10,L1,L10, M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3372-2 \ 16-038.22a December 8, 2006 S71PL-N_00_A9 S71PL-N MirrorBitTM MCPs 7 Data Sheet 5.3 S71PL127N—TLA064 Figure 5.4 64-ball Fine-Pitch Ball Grid Array (S71PL127N) A1 DNU B5 RFU C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 F-CE# J2 R-CE1# D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 C4 R-LB# D4 R-UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 H5 DQ3 J5 F-VCC K5 DQ11 L5 RFU M1 DNU H6 DQ4 J6 R-VCC K6 RFU L6 RFU C5 F-WP#/ ACC A10 DNU B6 RFU C6 WE# D6 R-CE2 E6 A20 C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 D9 A15 E9 A21 F9 A22 pSRAM Only G9 A16 H9 RFU J9 VSS Do Not Use/ Reserved for Future Use Flash Only Shared Legend D5 F-RST E5 F-RY/BY# M10 DNU Note: Top view—balls facing down. The addresses that are shared vary by MCP combination as shown in the table below: Flash-only Addresses S71PL127NB0 S71PL127NC0 A22-A21 A22 Shared Addresses A20:A0 A21:A0 8 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 Data Sheet 5.4 S71PL129N—TLA064 Figure 5.5 64-ball Fine-Pitch Ball Grid Array (S71PL129N) A1 DNU B5 RFU C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 F-CE1# J2 R-CE1# D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 C4 R-LB# D4 R-UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 H5 DQ3 J5 F-VCC K5 DQ11 L5 RFU M1 DNU H6 DQ4 J6 R-VCC K6 RFU L6 RFU C5 F-WP#/ ACC A10 DNU B6 RFU C6 WE# D6 R-CE2 E6 A20 C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 D9 A15 E9 A21 F9 F-CE2# pSRAM Only G9 A16 H9 RFU J9 VSS Do Not Use/ Reserved for Future Use Flash Only Shared Legend D5 F-RST E5 F-RY/BY# M10 DNU Note: Top view—balls facing down. The addresses that are shared vary by MCP combination as shown in the table below: Flash-only Addresses S71PL129NB0 S71PL129NC0 A21 — Shared Addresses A20:A0 A21:A0 December 8, 2006 S71PL-N_00_A9 S71PL-N MirrorBitTM MCPs 9 Data Sheet Figure 5.6 TLA064 Physical Dimensions D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 L J H G F E D CB A E1 INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 64X 0.15 0.08 0.20 C 6 SIDE VIEW b M C AB MC C 0.08 C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n φb eE eD SD / SE 0.35 TLA 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3352 \ 16-038.22a 10 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006 Data Sheet 6. Revision History Section Description Revision A (March 11, 2005) Initial release Revision A1 (April 27, 2005) Performance Characteristics pSRAM Density table Ordering Information and Valid Combination tables Block Diagram Physcial Dimensions/Connection Diagrams VCC Power Up DC Characteristics Revision A2 (August 18, 2005) Global Performance Characteristis Ordering Information Valid Combinations table Connection Diagram Revision A3 (October 21, 2005) Performance Characteristics Revision A4 (November 29, 2005) Global Revision A5 (January 3, 2006) Changed the name of in F3 from A14 to A4 in pinout figure of section 3.2 Removed all references to Type 6 pSRAMs from the Product Selector Guide Global Added a document reference table Modified the Package Type and Material options Removed the VSA084 package option Removed the datasheet from the MCP wrapper Revision A6 (April 12, 2006) Global Revision A7 (September 6, 2006) Global Revision A8 (October 6, 2006) Global Revision A9 (December 8, 2006) Global Added 64 Mb pSRAM Type 8 to the valid combinations. Added 32 Mb pSRAM Type 8 to the valid combinations Updated document to new template. Added pSRAM Type 7 as an option to S71PL127NB0 and S71PL129NB0 Added the 1.2 mm option to S71PL256ND0 Updated the S29PL-N Flash data sheet Updated the Typical Sector Erase times Removed all references to 56-ball package Updated the product selector tables Updated model number Added new ordering options Updated the PL127N connection diagram Updated the PL12xN connection diagram Added 128 Mb pSRAM device Updated options to include 128 Mb pSRAM device Changed chip enable pin from CE#f1 to F1-CE# Replaced VBH084 with TLA084 and VSA084 Replaced VBU056 with TLC056 Changed tVCS speed from 30 µs to 50 µs Changed ICC4 Max. to 50 µA December 8, 2006 S71PL-N_00_A9 S71PL-N MirrorBitTM MCPs 11 Data Sheet Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2005-2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 12 S71PL-N MirrorBitTM MCPs S71PL-N_00_A9 December 8, 2006