S71WS128JA0BAWTY2

S71WS-J Based MCPs Stacked Multi-Chip Product (MCP) 128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with CosmoRAM Data Sheet PRELIMINARY 1RWLFH WR 5HDGHUV 7KLV GRFXPHQW LQGLFDWHV VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV UHJDUGLQJ WKH 6SDQVLRQ SURGXFWV GHVFULEHG KHUHLQ 7KH 3UHOLPLQDU\ VWDWXV RI WKLV GRFXPHQW LQGLFDWHV WKDW D SURGXFW TXDOLILFDWLRQ KDV EHHQ FRPSOHWHG DQG WKDW LQLWLDO SURGXFWLRQ KDV EHJXQ 'XH WR WKH SKDVHV RI WKH PDQXIDFWXULQJ SURFHVV WKDW UHTXLUH PDLQWDLQLQJ HIILFLHQF\ DQG TXDOLW\ WKLV GRFXPHQW PD\ EH UHYLVHG E\ VXEVHTXHQW YHUVLRQV RU PRGLILFDWLRQV GXH WR FKDQJHV LQ WHFKQLFDO VSHFLILFDWLRQV Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005 Preliminary Notice On Data Sheet Designations 6SDQVLRQ //& LVVXHV GDWD VKHHWV ZLWK $GYDQFH ,QIRUPDWLRQ RU 3UHOLPLQDU\ GHVLJQDWLRQV WR DGYLVH UHDGHUV RI SURGXFW LQIRUPDWLRQ RU LQWHQGHG VSHFLILFDWLRQV WKURXJKRXW WKH SURGXFW OLIH F\FOH LQ FOXGLQJ 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)%*$ ²  [ PP EDOO )%*$ „ 2SHUDWLQJ 7HPSHUDWXUH ² ±ƒ& WR ƒ& General Description 7KH 6:6 VHULHV LV D SURGXFW OLQH RI VWDFNHG 0XOWL&KLS 3URGXFW 0&3 SDFNDJHV DQG FRQVLVWV RI „ 2QH RU PRUH IODVK PHPRU\ GLH „ S65$0 7KH SURGXFWV FRYHUHG E\ WKLV GRFXPHQW DUH OLVWHG LQ WKH WDEOH EHORZ )RU GHWDLOV DERXW WKHLU VSHFLILFDWLRQV SOHDVH UHIHU WR WKH LQGLYLGXDO FRQVWLWXHQW GDWDVKHHWV IRU IXUWKHU GHWDLOV Flash Memory Density 256Mb 128Mb 64Mb 0E S65$0 'HQVLW\ 0E 0E 6:6-& 6:6-& 6:6-% 6:6-$ 6:6-% 6:6-$ Publication Number S71WS-J_04 Revision A Amendment 2 Issue Date August 19, 2005 Preliminary Product Selector Guide Device-Model# 6:6-$< 6:6-%< 6:6-$$< 6:6-%$< 6:6-&$< 6:6-&7< 0E 0E 0E Flash Density pSRAM Density 0E Flash Speed (MHz) pSRAM Speed (MHz/ns) Supplier &RVPR 5$0 &RVPR 5$0 0E   &RVPR 5$0 &RVPR 5$0 &RVPR 5$0 &RVPR 5$0 [[ PP EDOO [[ PP EDOO Package Availability Status 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 3UHOLPLQDU\ 0E [[PP EDOO 2 S71WS-J Based MCPs S71WS-J_04_A2 August 19, 2005 Preliminary S71WS-J Based MCPs Notice On Data Sheet Designations . . . . . . . . . . . ii Advance Information .......................................................................................ii Preliminary ..........................................................................................................ii Combination .......................................................................................................ii Full Production (No Designation on Document) ...................................ii MCP Features ........................................................................................................ 1 Persistent Protection Bit Lock ....................................................................... 38 Standby Mode ...................................................................................................... 39 Automatic Sleep Mode ..................................................................................... 39 RESET#: Hardware Reset Input ................................................................ 39 Output Disable Mode ...................................................................................40 )LJXUH  7HPSRUDU\ 6HFWRU 8QSURWHFW 2SHUDWLRQ   )LJXUH  ,Q6\VWHP 6HFWRU 3URWHFWLRQ6HFWRU 8QSURWHFWLRQ $OJRULWKPV  7DEOH  6HFXUHG 6LOLFRQ 6HFWRU $GGUHVVHV   Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2 MCP Block Diagram .............................................................................................6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Lookahead Connection Diagram . . . . . . . . . . . . 10 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 14 TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ........................................................................................... 14 FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ............................................................................15 TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package ............................................................................... 16 TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package .........17 Secured Silicon Sector Protection Bit ...................................................... 43 Hardware Data Protection ......................................................................... 43 Write Protect (WP#) .......................................................................................44 Low VCC Write Inhibit .................................................................................44 Write Pulse “Glitch” Protection ...............................................................44 Logical Inhibit ...................................................................................................44 Power-Up Write Inhibit ...............................................................................44 Common Flash Memory Interface (CFI) . . . . . . . 45 7DEOH  &), 4XHU\ ,GHQWLILFDWLRQ 6WULQJ   7DEOH  6\VWHP ,QWHUIDFH 6WULQJ   7DEOH  'HYLFH *HRPHWU\ 'HILQLWLRQ  7DEOH  3ULPDU\ 9HQGRU6SHFLILF ([WHQGHG 4XHU\   7DEOH  :6- 6HFWRU $GGUHVV 7DEOH   7DEOH  :6- 6HFWRU $GGUHVV 7DEOH   Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62 S29WS128/064J General Description . . . . . . . . . . . . . . . . . . . . . . . .20 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 22 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input/Output Descriptions . . . . . . . . . . . . . . . . . . .24 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 25 7DEOH  'HYLFH %XV 2SHUDWLRQV   Reading Array Data ........................................................................................... 62 Set Configuration Register Command Sequence ..................................... 62 )LJXUH  6\QFKURQRXV$V\QFKURQRXV 6WDWH 'LDJUDP  Read Mode Setting ......................................................................................... 63 Programmable Wait State Configuration ............................................... 63 7DEOH  3URJUDPPDEOH :DLW 6WDWH 6HWWLQJV   Standard wait-state Handshaking Option ...............................................64 7DEOH  :DLW 6WDWHV IRU 6WDQGDUG ZDLWVWDWH +DQGVKDNLQJ   Read Mode Configuration ...........................................................................64 7DEOH  5HDG 0RGH 6HWWLQJV   VersatileIO™ (VIO) Control .............................................................................25 Requirements for Asynchronous Read Operation (Non-Burst) ..........25 Requirements for Synchronous (Burst) Read Operation ...................... 26 8-, 16-, and 32-Word Linear Burst with Wrap Around ......................27 7DEOH  %XUVW $GGUHVV *URXSV   Burst Active Clock Edge Configuration .................................................. 65 RDY Configuration ........................................................................................ 65 7DEOH  &RQILJXUDWLRQ 5HJLVWHU   Configuration Register ......................................................................................27 Handshaking ..........................................................................................................27 Simultaneous Read/Write Operations with Zero Latency ................... 28 Writing Commands/Command Sequences ................................................ 28 Accelerated Program Operation .................................................................. 28 Autoselect Mode ................................................................................................ 29 7DEOH  $XWRVHOHFW &RGHV +LJK 9ROWDJH 0HWKRG   Reset Command .................................................................................................66 Autoselect Command Sequence .................................................................... 67 Enter/Exit Secured Silicon Sector Command Sequence ......................... 67 Program Command Sequence ........................................................................68 Unlock Bypass Command Sequence ........................................................68 )LJXUH  3URJUDP 2SHUDWLRQ   Chip Erase Command Sequence ...................................................................69 Sector Erase Command Sequence ................................................................70 Erase Suspend/Erase Resume Commands ................................................... 71 )LJXUH  (UDVH 2SHUDWLRQ   Sector/Sector Block Protection and Unprotection ................................. 30 7DEOH  6:6-B0&3 %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSURWHFWLRQ   7DEOH  6:6- %RRW 6HFWRU6HFWRU %ORFN $GGUHVVHV IRU 3URWHFWLRQ8QSURWHFWLRQ   Sector Protection ...........................................................................................34 Persistent Sector Protection ...........................................................................34 Persistent Protection Bit (PPB) ..................................................................35 Persistent Protection Bit Lock (PPB Lock) .............................................35 Dynamic Protection Bit (DYB) ...................................................................35 7DEOH  6HFWRU 3URWHFWLRQ 6FKHPHV   Persistent Sector Protection Mode Locking Bit ........................................37 Password Protection Mode .............................................................................37 Password and Password Mode Locking Bit ................................................37 64-bit Password ...................................................................................................38 Password Program Command ....................................................................... 72 Password Verify Command ............................................................................. 73 Password Protection Mode Locking Bit Program Command .............. 73 Persistent Sector Protection Mode Locking Bit Program Command ........................................................................................... 73 Secured Silicon Sector Protection Bit Program Command .................. 73 PPB Lock Bit Set Command ............................................................................ 74 DPB Write/Erase/Status Command ............................................................. 74 Password Unlock Command .......................................................................... 74 PPB Program Command .................................................................................. 75 All PPB Erase Command .................................................................................. 75 PPB Status Command ....................................................................................... 75 PPB Lock Bit Status Command ...................................................................... 75 Command Definitions ....................................................................................... 76 7DEOH  &RPPDQG 'HILQLWLRQV   August 19, 2005 S71WS-J_04_A2 S71WS-J Based MCPs 3 Preliminary Write Operation Status . . . . . . . . . . . . . . . . . . . . .79 DQ7: Data# Polling ............................................................................................79 )LJXUH  'DWD 3ROOLQJ $OJRULWKP  %DQN  )LJXUH  ([DPSOH RI :DLW 6WDWHV ,QVHUWLRQ  )LJXUH  %DFNWR%DFN 5HDG:ULWH &\FOH 7LPLQJV   DQ6: Toggle Bit I ................................................................................................ 81 )LJXUH  7RJJOH %LW $OJRULWKP  CosmoRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . 114 Functional Description . . . . . . . . . . . . . . . . . . . . . 115 Asynchronous Operation (Page Mode) .......................................................115 DQ2: Toggle Bit II .............................................................................................. 82 7DEOH  '4 DQG '4 ,QGLFDWLRQV   Reading Toggle Bits DQ6/DQ2 ......................................................................83 DQ5: Exceeded Timing Limits ....................................................................... 84 DQ3: Sector Erase Timer ................................................................................ 84 7DEOH  :ULWH 2SHUDWLRQ 6WDWXV   Functional Description . . . . . . . . . . . . . . . . . . . . . 116 Synchronous Operation (Burst Mode) ........................................................116 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 85 )LJXUH  0D[LPXP 1HJDWLYH 2YHUVKRRW :DYHIRUP   )LJXUH  0D[LPXP 3RVLWLYH 2YHUVKRRW :DYHIRUP   State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Initial/Standby State ............................................................................................117 )LJXUH  ,QLWLDO 6WDQGE\ 6WDWH 'LDJUDP   Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 )LJXUH  7HVW 6HWXS   7DEOH  7HVW 6SHFLILFDWLRQV   Asynchronous Operation State .....................................................................117 )LJXUH  $V\QFKURQRXV 2SHUDWLRQ 6WDWH 'LDJUDP  Synchronous Operation State ........................................................................118 )LJXUH  6\QFKURQRXV 2SHUDWLRQ 'LDJUDP   Key to Switching Waveforms . . . . . . . . . . . . . . . 88 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 89 )LJXUH  ,QSXW :DYHIRUPV DQG 0HDVXUHPHQW /HYHOV  Functional Description . . . . . . . . . . . . . . . . . . . . . 118 Power-up ...............................................................................................................118 Configuration Register ......................................................................................118 CR Set Sequence ................................................................................................118 Power Down ........................................................................................................121 Burst Read/Write Operation ..........................................................................121 )LJXUH  %XUVW 5HDG 2SHUDWLRQ  )LJXUH  %XUVW :ULWH 2SHUDWLRQ   AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89 VCC Power-up ..................................................................................................... 89 )LJXUH  9&& 3RZHUXS 'LDJUDP   )LJXUH  &/. &KDUDFWHUL]DWLRQ   CLK Characterization ....................................................................................... 90 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91 Synchronous/Burst Read @ VIO = 1.8 V ...................................................... 91 )LJXUH  &/. 6\QFKURQRXV %XUVW 0RGH 5HDG ULVLQJ DFWLYH &/.  )LJXUH  &/. 6\QFKURQRXV %XUVW 0RGH 5HDG )DOOLQJ $FWLYH &ORFN   )LJXUH  6\QFKURQRXV %XUVW 0RGH 5HDG  )LJXUH  ZRUG /LQHDU %XUVW ZLWK :UDS $URXQG  )LJXUH  /LQHDU %XUVW ZLWK 5'< 6HW 2QH &\FOH %HIRUH 'DWD   )LJXUH  $V\QFKURQRXV 0RGH 5HDG ZLWK /DWFKHG $GGUHVVHV   )LJXUH  $V\QFKURQRXV 0RGH 5HDG  )LJXUH  5HVHW 7LPLQJV  )LJXUH  $V\QFKURQRXV 3URJUDP 2SHUDWLRQ 7LPLQJV $9' /DWFKHG $GGUHVVHV   )LJXUH  $V\QFKURQRXV 3URJUDP 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................................................................................123 )LJXUH  5HDG /DWHQF\ 'LDJUDP   Address Latch by ADV# .................................................................................125 Burst Length ........................................................................................................125 Single Write .........................................................................................................125 Write Control ....................................................................................................126 )LJXUH  :ULWH &RQWUROV  Asynchronous Mode Read @ VIO = 1.8 V ..................................................95 Burst Read Suspend ..........................................................................................126 )LJXUH  %XUVW 5HDG 6XVSHQG 'LDJUDP  Burst Write Suspend ........................................................................................127 )LJXUH  %XUVW :ULWH 6XVSHQG 'LDJUDP   Erase/Program Operations @ VIO = 1.8 V ................................................. 98 Burst Read Termination ..................................................................................127 )LJXUH  %XUVW 5HDG 7HUPLQDWLRQ 'LDJUDP   Burst Write Termination ................................................................................128 )LJXUH  %XUVW :ULWH 7HUPLQDWLRQ 'LDJUDP  Absolute Maximum Ratings . . . . . . . . . . . . . . . . 129 Recommended Operating Conditions (See Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 129 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 131 Read Operation ..................................................................................................131 Write Operation ............................................................................................... 133 Synchronous Operation - Clock Input (Burst Mode) ............................134 Synchronous Operation - Address Latch (Burst Mode) .......................134 Synchronous Read Operation (Burst Mode) ............................................ 135 Synchronous Write Operation (Burst Mode) ..........................................136 Power Down Parameters ............................................................................... 137 Other Timing Parameters ............................................................................... 137 AC Test Conditions ......................................................................................... 137 AC Measurement Output Load Circuit .....................................................138 )LJXUH  2XWSXW /RDG &LUFXLW  Temporary Sector Unprotect ....................................................................... 107 4 S71WS-J Based MCPs S71WS-J_04_A2 August 19, 2005 Preliminary Timing Diagrams . . . . . . . . . . . . . . . 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)LJXUH  6\QFKURQRXV :ULWH WR 5HDG 7LPLQJ  $'9 &RQWURO   )LJXUH  3RZHUXS 7LPLQJ    )LJXUH  3RZHUXS 7LPLQJ    )LJXUH  3RZHU 'RZQ (QWU\ DQG ([LW 7LPLQJ   )LJXUH  6WDQGE\ (QWU\ 7LPLQJ DIWHU 5HDG RU :ULWH  )LJXUH  &RQILJXUDWLRQ 5HJLVWHU 6HW 7LPLQJ  $V\QFKURQRXV 2SHUDWLRQ  )LJXUH  &RQILJXUDWLRQ 5HJLVWHU 6HW 7LPLQJ  6\QFKURQRXV 2SHUDWLRQ  COSMORAM Type 1 – 1.8 V, 16 Mb Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 General Description . . . . . . . . . . . . . . . . . . . . . . . 169 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 171 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 171 Recommended Operating Conditions . . . . . . . . 171 Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 172 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172 Read Operation .................................................................................................172 Write Operation .............................................................................................. 173 Power Down Parameters ...............................................................................174 Other Timing Parameters ...............................................................................174 AC Test Conditions .........................................................................................174 AC Measurement Output Load Circuit .....................................................174 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 175 )LJXUH  5HDG 7LPLQJ  %DVLF 7LPLQJ   )LJXUH  5HDG 7LPLQJ  2( DQG $GGUHVV $FFHVV   )LJXUH  5HDG 7LPLQJ  /%  8% %\WH $FFHVV   )LJXUH  :ULWH 7LPLQJ  %DVLF 7LPLQJ   )LJXUH  :ULWH 7LPLQJ  :( &RQWURO  )LJXUH  :ULWH 7LPLQJ  ±  :(  /%  8% %\WH :ULWH &RQWURO   )LJXUH  :ULWH 7LPLQJ  ±  :(  /%  8% %\WH :ULWH &RQWURO   )LJXUH  :ULWH 7LPLQJ  ±  :(  /%  8% %\WH :ULWH &RQWURO   )LJXUH  :ULWH 7LPLQJ  ±  :(  /%  8% %\WH :ULWH &RQWURO   )LJXUH  5HDG  :ULWH 7LPLQJ  ±  &(  &RQWURO   )LJXUH  5HDG  :ULWH 7LPLQJ  ±  &(   :(  2( &RQWURO   )LJXUH  5HDG  :ULWH 7LPLQJ  2(  :( &RQWURO  )LJXUH  5HDG  :ULWH 7LPLQJ  2( :( /% 8% &RQWURO  )LJXUH  3RZHU8S 7LPLQJ   )LJXUH  3RZHU'RZQ (QWU\ DQG ([LW 7LPLQJ   )LJXUH  6WDQGE\ (QWU\ 7LPLQJ DIWHU 5HDG RU :ULWH   Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 183 Revision Summary August 19, 2005 S71WS-J_04_A2 S71WS-J Based MCPs 5 Preliminary MCP Block Diagram F-VCC Flash-only Address Shared Address CLK F-WP# F-ACC (Note 3) F1-CE# OE# WE# F-RST# AVD# (Note 3) F2-CE# R-VCC A22 VCC VCCQ 16 VID 16 DQ15 to DQ0 CLK WP# ACC Flash 1 CE# Flash 2 OE# (Note 4) WE# RESET# RDY AVD# VCC A22 DQ15 to DQ0 RDY VSS R-CE1# R-UB# R-LB# (Note 1) R-CE2 (Note 2) R-CRE CLK (Note 5) WAIT# CE# I/O15 to I/O0 WE# OE# pSRAM UB# VSSQ LB# AVD# (Note 5) 1RWHV      5&5( LV RQO\ SUHVHQW LQ &HOOXODU5$0FRPSDWLEOH S65$0 5&( LV RQO\ SUHVHQW LQ &RVPR5$0FRPSDWLEOH S65$0 )RU  )ODVK S65$0 )&( &(  )RU  )ODVK  S65$0 &( 2QO\ QHHGHG IRU 6:6-& DQG 6:6- &/. DQG $9' QRW DSSOLFDEOH IRU 0E S65$0 )&( DQG )&( LV WKH FKLSHQDEOH SLQ IRU WKH VHFRQG )ODVK 6 S71WS-J Based MCPs S71WS-J_04_A2 August 19, 2005 Preliminary Connection Diagrams (CosmoRAM Type-based) EDOO )LQH3LWFK %DOO *ULG $UUD\ &RVPR5$0EDVHG 3LQRXW 7RS 9LHZ %DOOV )DFLQJ 'RZQ A1 NC B2 AVD# C2 WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 CE1#f J2 CE1#s K2 RFU L2 RFU M1 NC B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 LB#s D4 UB#s E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU B5 F2-CE# C5 ACC D5 RESET# E5 RDY F5 RFU G5 RFU H5 DQ3 J5 VCCf K5 DQ11 L5 VCCf B6 RFU C6 WE# D6 CE2s E6 A20 F6 A23 G6 RFU H6 DQ4 J6 VCCs K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D9 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D10 A15 E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU A10 NC Legend Shared 1st Flash only 2nd Flash only 1st RAM only Reserved for Future Use M10 NC 1RWHV   ,Q 0&3¶V EDVHG RQ D VLQJOH 6:6[[[- 6:6[[[- EDOO % LV 5)8 ,Q 0&3¶V EDVHG RQ WZR 6:6[[[- 6:6- EDOO % LV &( I RU )&(  $GGUHVVHV DUH VKDUHG EWZHHQ )ODVK DQG 5$0 GHSHQGLQJ RQ WKH GHQVLW\ RI WKH S65$0 MCP 6:6-$ 6:6-% 6:6-$ 6:6-% 6:6-& Flash-only Addresses $$ $ $$ $$ $ Shared Addresses $$ $$ $$ $$ $$ August 19, 2005 S71WS-J_04_A2 S71WS-J Based MCPs 7 Preliminary MCP 6:6-& Flash-only Addresses $ Shared Addresses $$ 6SHFLDO +DQGOLQJ ,QVWUXFWLRQV )RU )%*$ 3DFNDJH 6SHFLDO KDQGOLQJ LV UHTXLUHG IRU )ODVK 0HPRU\ SURGXFWV LQ )%*$ SDFNDJHV )ODVK PHPRU\ GHYLFHV LQ )%*$ SDFNDJHV PD\ EH GDPDJHG LI H[SRVHG WR XOWUDVRQLF FOHDQLQJ PHWK RGV 7KH SDFNDJH DQGRU GDWD LQWHJULW\ PD\ EH FRPSURPLVHG LI WKH SDFNDJH ERG\ LV H[SRVHG WR WHPSHUDWXUHV DERYH °& IRU SURORQJHG SHULRGV RI WLPH (CosmoRAM Type-based) EDOO )LQH3LWFK %DOO *ULG $UUD\ &RVPR5$0EDVHG 3LQRXW 7RS 9LHZ %DOOV Legend A1 AVD# B1 WP# C1 A3 D1 A2 E1 A1 F1 A0 G1 CE1#f H1 CE1#s J1 RFU K1 RFU A2 RFU B2 A7 C2 A6 D2 A5 E2 A4 F2 VSS G2 OE# H2 DQ0 J2 DQ8 K2 RFU A3 CLK B3 LB#s C3 UB#s D3 A18 E3 A17 F3 DQ1 G3 DQ9 H3 DQ10 J3 DQ2 K3 RFU A4 F2-CE# B4 ACC C4 RESET# D4 RDY E4 RFU F4 RFU G4 DQ3 H4 VCCf J4 DQ11 K4 VCCf A5 RFU B5 WE# C5 CE2s D5 A20 E5 A23 F5 RFU G5 DQ4 H5 VCCs J5 RFU K5 RFU A6 RFU B6 A8 C6 A19 D6 A9 E6 A10 F6 DQ6 G6 DQ13 H6 DQ12 J6 DQ5 K6 RFU A7 RFU B7 A11 C7 A12 D7 A13 E7 A14 F7 RFU G7 DQ15 H7 DQ7 J7 DQ14 K7 RFU A8 RFU B8 RFU C8 A15 D8 A21 E8 A22 F8 A16 G8 RFU H8 VSS J8 RFU K8 RFU Shared 1st Flash only 2nd Flash only 1st RAM only Reserved for Future Use 1RWHV    ,Q 0&3¶V EDVHG RQ D VLQJOH 6:6[[[- 6:6[[[- EDOO % LV 5)8 ,Q 0&3¶V EDVHG RQ WZR 6:6[[[- 6:6- EDOO % LV &( I RU )&(  $GGUHVVHV DUH VKDUHG EWZHHQ )ODVK DQG 5$0 GHSHQGLQJ RQ WKH GHQVLW\ RI WKH S65$0 7KH EDOO SLQRXW LV DSSOLFDEOH RQO\ WR WKRVH 0&3V ZLWK )ODVK GHQVLW\ RI 0E RU 0E )RU DOO WKH RWKHU 0&3V LQFOXGHG LQ WKLV GDWDVKHHW SOHDVH XVH WKH EDOO SLQRXW IRU GHVLJQ MCP 6:6-$ 6:6-% Flash-only Addresses $$ $ Shared Addresses $$ $$ 8 S71WS-J Based MCPs S71WS-J_04_A2 August 19, 2005 Preliminary MCP 6:6-$ 6:6-% 6:6-& 6:6-& Flash-only Addresses $$ $$ $ $ Shared Addresses $$ $$ $$ $$ 6SHFLDO +DQGOLQJ ,QVWUXFWLRQV )RU )%*$ 3DFNDJH 6SHFLDO KDQGOLQJ LV UHTXLUHG IRU )ODVK 0HPRU\ SURGXFWV LQ )%*$ SDFNDJHV )ODVK PHPRU\ GHYLFHV LQ )%*$ SDFNDJHV PD\ EH GDPDJHG LI H[SRVHG WR XOWUDVRQLF FOHDQLQJ PHWK RGV 7KH SDFNDJH DQGRU GDWD LQWHJULW\ PD\ EH FRPSURPLVHG LI WKH SDFNDJH ERG\ LV H[SRVHG WR WHPSHUDWXUHV DERYH °& IRU SURORQJHG SHULRGV RI WLPH 9 S71WS-J_04A2 August 19, 2005 Preliminary Lookahead Connection Diagram Legend: A1 DNU B1 DNU A2 DNU B2 DNU C2 AVD# D2 F-WP# E2 A3 F2 A2 G2 A1 H2 A0 J2 F1-CE# K2 R1-CE1# L2 L2 R-VCC M2 A27 N1 F-DQS0 P1 DNU N2 DNU P2 DNU C3 VSS D3 A7 E3 A6 F3 A5 G3 A4 H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 A26 C4 CLK D4 C5 F2-CE# D5 C6 F-VCC D6 WE# E6 R1-CE2 F6 A20 G6 A23 H6 R2-CE2 J6 DQ4 K6 R1-VCC L6 A25 M6 F4-CE# C7 F-CLK D7 A8 E7 A19 F7 A9 G7 A10 H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 R-VCCQ C8 R-OE# D8 A11 E8 A12 F8 A13 G8 A14 H8 A24 J8 DQ15 K8 DQ7 L8 DQ14 M8 F-VCCQ A9 DNU B9 DNU C9 F2-OE# D9 F3-CE# E9 A15 F9 A21 G9 A22 H9 A16 2nd RAM Only J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS J5 DQ3 K5 K5 F-VCC L5 DQ11 M5 F-VCC J2 DNU K9 VSS L9 WP#/ACC M9 R-CLK N9 DNU P9 DNU N10 F-DQS-1 P10 DNU xRAM Shared Only 1st RAM Only Flash Only Flash/Data Shared Only A10 DNU B10 DNU MirrorBit Data-storage Only Shared or DNU (Do Not Use) R-LB# WP#/ACC E4 R-UB# F4 A18 G4 A17 H4 DQ1 E5 F-RST# F5 RDY G5 R2-CE1 H5 R2-VCC 1st Flash Only 1RWHV      ) DQG ) GHQRWH ;,3&RGH )ODVK ZKLOH ) DQG ) GHQRWH 'DWD&RPSDQLRQ )ODVK ,Q DGGLWLRQ WR EHLQJ GHILQHG DV )&(  %DOO & FDQ DOVR EH DVVLJQHG DV )&( IRU FRGH IODVK WKDW KDV WZR FKLS HQDEOH VLJQDOV )RU 0&3V UHTXLULQJ 9 9FF DQG 9 9LR XVH WKH 9 /RRNDKHDG 3LQRXW LQ RUGHU WR DFFRPPRGDWH H[WUD $9' 056 DQG &/. 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