S71WS512NE0BFWZZ
Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory and Pseudo-Static RAM
ADVANCE INFORMATION
DISTINCTIVE CHARACTERISTICS
MCP Features
Operating Voltage Range of 1.65 to 1.95 V High Performance — Speed: 54MHz Packages — 96-ball FBGA—9 x 12 mm Operating Temperatures — Wireless: –25°C to +85°C
GENERAL DESCRIPTION
The S71WS512 Series is a product line of stacked Multi-Chip Products (MCP) and consists of
One or more S29WS256N (Simultaneous Operation, Burst Mode) Flash Die pSRAM options — 128Mb pSRAM
The products covered by this document are listed below. For details about their specifications, please refer to the individual constituent data sheets for further details. Number of S29WSxxxN 2 Total Flash Density 512Mb pSRAM Density 256Mb
MCP S71WS512NE0
Notes: 1. This MCP is only guaranteed to operate @ 1.65 - 1.95 V regardless of component operating ranges.
Publication Number S71WS512NE0BFWZZ_00
Revision A
Amendment 1
Issue Date June 28, 2004
Advance
Information
Product Selector Guide
Device-Model # S71WS512NE0BFWZZ SRAM/pSRAM Density 256Mb SRAM/pSRAM Type pSRAM - x16 Supplier COSMORAM 1 Flash Access RAM Access Time (MHz) Time (MHz) 54 54 Packages TBD
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S71WS512NE0BFWZZ
S71WS512NE0BFWZZ_00_A1 June 28, 2004
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TABLE OF CONTENTS
S71WS512NE0BFWZZ
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram of S71WS512NE0BFWZZ ...........................................6 Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode .............................................................................................33 Lock Register ....................................................................................................... 34
Table 6. Lock Register ........................................................ 34
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagram of S71WS512NE0BFWZZ ..........................................7 Special Package Handling Instructions ........................................................8 Pin Description ..................................................................................................8 Logic Symbol .....................................................................................................9 Device Bus Operation ....................................................................................... 10
Table 1. Device Bus Operations ........................................... 10
Pin Capacitance ................................................................................................... 12
Physical Dimensions TBD . . . . . . . . . . . . . . . . . . 13
XXX .........................................................................................................................13
Hardware Data Protection Mode ................................................................. 34 Write Protect (WP#) ................................................................................... 34 Low VCC Write Inhibit ................................................................................. 34 Write Pulse “Glitch” Protection ............................................................... 35 Logical Inhibit ................................................................................................... 35 Power-Up Write Inhibit ............................................................................... 35 Standby Mode ...................................................................................................... 35 Automatic Sleep Mode ..................................................................................... 35 RESET#: Hardware Reset Input ................................................................ 35 Output Disable Mode ................................................................................... 36 SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 36 Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory ....................................................................................................... 36
Table 7. SecSiTM Sector Addresses ........................................ 37
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 14 General Description . . . . . . . . . . . . . . . . . . . . . . . . 16 Product Selector Guide . . . . . . . . . . . . . . . . . . . . 19
Block Diagram .................................................................................................... 19
Customer SecSi Sector ................................................................................. 37 SecSi Sector Protection Bit ......................................................................... 37
Common Flash Memory Interface (CFI) . . . . . . 37
Table 8. CFI Query Identification String ................................ 38 Table 9. System Interface String ......................................... 38 Table 10. Device Geometry Definition ................................... 39 Table 11. Primary Vendor-Specific Extended Query ................ 39 Table 12. Sector Address / Memory Address Map for the WS256N ........................................................................................ 41
Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 21 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. Device Bus Operations ........................................... 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 49
Reading Array Data ...........................................................................................49 Set Configuration Register Command Sequence .....................................49 Read Configuration Register Command Sequence ..................................50
Figure 1. Synchronous/Asynchronous State Diagram.............. 50
Requirements for Asynchronous Read Operation (Non-Burst) ..........23 Requirements for Synchronous (Burst) Read Operation ...................... 24
Table 3. Address Dependent Additional Latency ..................... 24
Read Mode Setting .........................................................................................50 Programmable Wait State Configuration ...............................................50
Table 13. Programmable Wait State Settings ......................... 51
Continuous Burst ........................................................................................... 24 8-, 16-, and 32-Word Linear Burst with Wrap Around ......................25
Table 4. Burst Address Groups ............................................ 25
Programmable Wait State ............................................................................ 51 Boundary Crossing Latency ......................................................................... 51 Set Internal Clock Frequency ...................................................................... 51
Table 14. Wait States for Handshaking ................................. 51
8-, 16-, and 32-Word Linear Burst without Wrap Around ................25 Configuration Register ......................................................................................25 Handshaking ..........................................................................................................25 Simultaneous Read/Write Operations with Zero Latency ................... 26 Writing Commands/Command Sequences ................................................ 26 Unlock Bypass Mode .................................................................................... 26 Accelerated Program/Erase Operations ..................................................... 26 Write Buffer Programming Operation .........................................................27 Autoselect Mode ................................................................................................ 28 Advanced Sector Protection and Unprotection ....................................... 29 Persistent Mode Lock Bit ............................................................................ 29 Password Mode Lock Bit ............................................................................. 30 Sector Protection ............................................................................................... 30 Persistent Sector Protection .......................................................................... 30 Persistent Protection Bit (PPB) ...................................................................31 Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode ..............................................................................................31 Dynamic Protection Bit (DYB) ....................................................................31
Table 5. Sector Protection Schemes ..................................... 32
Handshaking ...................................................................................................... 51 Burst Sequence ............................................................................................... 52 Burst Length Configuration ......................................................................... 52
Table 15. Burst Length Configuration ................................... 52
Burst Wrap Around ...................................................................................... 52 Burst Active Clock Edge Configuration .................................................. 52 RDY Configuration ........................................................................................ 52 RDY Polarity .................................................................................................... 52 Configuration Register ...................................................................................... 53
Table 16. Configuration Register .......................................... 53
Reset Command ................................................................................................. 53 Autoselect Command Sequence .................................................................... 54
Table 17. Autoselect Addresses ........................................... 54
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 55 Word Program Command Sequence ........................................................... 55 Write Buffer Programming Command Sequence ..................................... 56
Table 18. Write Buffer Command Sequence .......................... 56 Figure 2. Write Buffer Programming Operation ...................... 57
Password Sector Protection ............................................................................33 64-bit Password ...............................................................................................33
Unlock Bypass Command Sequence ........................................................ 57
Figure 3. Program Operation ............................................... 58
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Chip Erase Command Sequence ................................................................... 58 Sector Erase Command Sequence .................................................................59 Erase Suspend/Erase Resume Commands .................................................. 60
Figure 4. Erase Operation.................................................... 61
Program Suspend/Program Resume Commands ...................................... 61 Lock Register Command Set Definitions ................................................... 62 Password Protection Command Set Definitions ..................................... 62 Non-Volatile Sector Protection Command Set Definitions ..................63 Global Volatile Sector Protection Freeze Command Set ..................... 64 Volatile Sector Protection Command Set ...................................................65 SecSi Sector Entry Command .........................................................................65 Command Definition Summary ..................................................................... 66
Write Operation Status . . . . . . . . . . . . . . . . . . . . .69
DQ7: Data# Polling ........................................................................................... 69
Figure 5. Data# Polling Algorithm......................................... 70
Figure 22. Synchronous Program Operation Timings: CLK Latched Addresses......................................................................... 88 Figure 23. Accelerated Unlock Bypass Programming Timing..... 88 Figure 24. Data# Polling Timings (During Embedded Algorithm) ... ........................................................................................ 89 Figure 25. Toggle Bit Timings (During Embedded Algorithm) ... 89 Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings .. ........................................................................................ 90 Figure 27. DQ2 vs. DQ6 ..................................................... 90 Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................. 91 Figure 29. Latency with Boundary Crossing into Program/Erase Bank................................................................................ 91 Figure 30. Example of Wait States Insertion.......................... 92 Figure 31. Back-to-Back Read/Write Cycle Timings ................ 92
Erase and Programming Performance . . . . . . . . 93
RDY: Ready .......................................................................................................... 70 DQ6: Toggle Bit I ............................................................................................... 70
Figure 6. Toggle Bit Algorithm.............................................. 71
128Mb pSRAM
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 FUNCTION TRUTH TABLE . . . . . . . . . . . . . . . 95
Asynchronous Operation (Page Mode) ..................................................... 95
DQ2: Toggle Bit II ...............................................................................................72
Table 19. DQ6 and DQ2 Indications ..................................... 72
Reading Toggle Bits DQ6/DQ2 ......................................................................72 DQ5: Exceeded Timing Limits ........................................................................73 DQ3: Sector Erase Timer .................................................................................73 DQ1: Write to Buffer Abort ............................................................................73
Table 20. Write Operation Status ......................................... 74
FUNCTION TRUTH TABLE (Continued) . . . . 96
Synchronous Operation (Burst Mode) .......................................................96
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 75
Figure 7. Maximum Negative Overshoot Waveform................. 75 Figure 8. Maximum Positive Overshoot Waveform .................. 75
STATE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 97 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 98
Power-up ...............................................................................................................98 Configuration Register ......................................................................................98 CR Set Sequence ................................................................................................98
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76
CMOS Compatible .............................................................................................76 Test Conditions ...................................................................................................77
Figure 9. Test Setup ........................................................... 77 Table 21. Test Specifications ............................................... 77
FUNCTIONAL DESCRIPTION (Continued) . . 99
Address Key .........................................................................................................99
FUNCTIONAL DESCRIPTION (Continued) . 100
Power Down ...................................................................................................... 100
FUNCTIONAL DESCRIPTION (Continued) . . 101
Burst Read/Write Operation ..........................................................................101
Switching Waveforms ........................................................................................77
Table 22. Key to Switching Waveforms ................................. 77 Figure 10. Input Waveforms and Measurement Levels............. 77
FUNCTIONAL DESCRIPTION (Continued) . 102
CLK Input Function ..........................................................................................102 ADV# Input Function .......................................................................................102 WAIT# Output Function ................................................................................102
VCC Power-up ..................................................................................................... 78 Pin Capacitance .................................................................................................. 78
Figure 11. VCC Power-up Diagram ........................................ 78
AC Characteristics—Synchronous . . . . . . . . . . . 79
CLK Characterization ........................................................................................79
Figure 12. CLK Characterization ........................................... 79
FUNCTIONAL DESCRIPTION (Continued) . . 103
Latency ..................................................................................................................103
FUNCTIONAL DESCRIPTION (Continued) . 104
Address Latch by ADV# .................................................................................104 Burst Length ........................................................................................................104 Single Write .........................................................................................................104 Write Control ....................................................................................................105
Synchronous/Burst Read @ VIO = 1.8 V ..................................................... 80 Timing Diagrams .................................................................................................. 81
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK). ....................................................................................... 81 Figure 14. Synchronous Burst Mode Read.............................. 82 Figure 15. Eight-word Linear Burst with Wrap Around ............. 82 Figure 16. Eight-word Linear Burst without Wrap Around......... 83 Figure 17. Linear Burst with RDY Set One Cycle Before Data.... 83
FUNCTIONAL DESCRIPTION (Continued) . 106
Burst Read Suspend ..........................................................................................106 Burst Write Suspend ........................................................................................106
FUNCTIONAL DESCRIPTION (Continued) . . 107
Burst Read Termination ..................................................................................107 Burst Write Termination ................................................................................107
AC Characteristics—Asynchronous . . . . . . . . . . 84
Asynchronous Mode Read @ VIOpS = 1.8 V ............................................. 84 Timing Diagrams ................................................................................................. 84
Figure 18. Asynchronous Mode Read with Latched Addresses... 84 Figure 19. Asynchronous Mode Read..................................... 85
Hardware Reset (RESET#) .............................................................................. 85
Figure 20. Reset Timings..................................................... 85
ABSOLUTE MAXIMUM RATINGS (See WARNING below.) . . . . . . . . . . . . . . . . . . . . . . 108 RECOMMENDED OPERATING CONDITIONS (See WARNING below.) . . . . . . . . . . . . . . . . . . 108
(Referenced to VSS) ................................................................................... 108
Erase/Program Operations @ VIO = 1.8 V ................................................. 86
Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses ............................................................. 87
DC CHARACTERISTICS . . . . . (Under Recommended Operating Conditions unless otherwise noted) . . . . . . . . Note *1,*2,*3 109 S71WS512NE0BFWZZ_00_A1 June 28, 2004
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AC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 110
ASYNCHRONOUS READ OPERATION (PAGE MODE) ................110
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 124
Asynchronous Read / Write Timing #1-1 (CE#1 Control) ...................124 Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control) .................................................................................................................................. 124
AC CHARACTERISTICS (Continued) . . . . . . . . 111
ASYNCHRONOUS WRITE OPERATION ............................................. 111
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 125
Asynchronous Read / Write Timing #2 (OE#, WE# Control) ........125 Asynchronous Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) .................................................................................................................................. 125
AC CHARACTERISTICS (Continued) . . . . . . . . 112
SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE) .................................................................................................................................. 112 SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE) .................................................................................................................................. 112
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 126
Clock Input Timing ..........................................................................................126 Address Latch Timing (Synchronous Mode) ............................................126
AC CHARACTERISTICS (Continued) . . . . . . . . 113
SYNCHRONOUS READ OPERATION (BURST MODE) ................ 113
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 127
Synchronous Read Timing #1 (OE# Control) .........................................127
AC CHARACTERISTICS (Continued) . . . . . . . . 114
SYNCHRONOUS WRITE OPERATION (BURST MODE) .............. 114
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 128
Synchronous Read Timing #2 (CE#1 Control) ........................................128
AC CHARACTERISTICS (Continued) . . . . . . . . 115
POWER DOWN PARAMETERS ............................................................... 115 OTHER TIMING PARAMETERS ................................................................. 115
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 129
Synchronous Read Timing #3 (ADV# Control) .....................................129
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 130
Synchronous Write Timing #1 (WE# Level Control) ...........................130
AC CHARACTERISTICS (Continued) . . . . . . . . 116
AC TEST CONDITIONS ............................................................................... 116 AC MEASUREMENT OUTPUT LOAD CIRCUIT ................................. 116
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 131
Synchronous Write Timing #2 (WE# Single Clock Pulse Control) .. 131
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 117
Asynchronous Read Timing #1-1 (Basic Timing) ...................................... 117 Asynchronous Read Timing #1-2 (Basic Timing) ...................................... 117
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 132
Synchronous Write Timing #3 (ADV# Control) ...................................132
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 133
Synchronous Write Timing #4 (WE# Level Control, Single Write) 133
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 118
Asynchronous Read Timing #2 (OE# & Address Access) ...................118 Asynchronous Read Timing #3 (LB# / UB# Byte Access) ..................118
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 134
Synchronous Read to Write Timing #1(CE#1 Control) .......................134
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 119
Asynchronous Read Timing #4 (Page Address Access after CE#1 Control Access) .................................................................................................................. 119 Asynchronous Read Timing #5 (Random and Page Address Access) 119
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 135
Synchronous Read to Write Timing #2(ADV# Control) .................... 135
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 136
Synchronous Write to Read Timing #1 (CE#1 Control) ......................136
TIMING DIAGRAMS (Continued) . . . . . . . . . . 120
Asynchronous Write Timing #1-1 (Basic Timing) ...................................120 Asynchronous Write Timing #1-2 (Basic Timing) ...................................120
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 137
Synchronous Write to Read Timing #2 (ADV# Control) .................. 137
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 121
Asynchronous Write Timing #2 (WE# Control) ................................... 121 Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control) ........................................................................................................................ 121
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 138
POWER-UP Timing #1 ....................................................................................138 POWER-UP Timing #2 ...................................................................................138
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 139
POWER DOWN Entry and Exit Timing ..................................................139 Standby Entry Timing after Read or Write ..............................................139
TIMING DIAGRAMS (Continued) . . . . . . . . . . 122
Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 122 Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 122
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 140
Configuration Register Set Timing #1 (Asynchronous Operation) ...140
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 141
Configuration Register Set Timing #2 (Synchronous Operation) .....141
TIMING DIAGRAMS (Continued) . . . . . . . . . . 123
Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 123
Revision Summary
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Block Diagrams
MCP Block Diagram of S71WS512NE0BFWZZ
VCCf_1 A23 to A0 VSS
AVD# CLK WE# OE# RESET#
256 M bit Burst Flash Memory_1
RDY
CE#f1 VCCf_2 A23 to A0 VSS
256 M bit Burst Flash Memory_2 ACC WP# CE#f2 DQ15 to DQ0 VCCpS VSS VIOpS A22 to A0
128 M bit pSRAM_1 LB# UB# CE#1pS-1 CE2pS-1 VCCpS VSS VIOpS
128 M bit
pSRAM_2
CE#1pS-2 CE2pS-2
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Connection Diagrams
Connection Diagram of S71WS512NE0BFWZZ
96-Ball FBGA Top View
A1
NC
A2
NC
A9
NC
A10
NC
B1
NC
B2
NC
B9
NC
B10
NC
C2
AVD#
C3
VSS
C4
CLK
C5
CE#f2
C6
RFU
C7
RFU
C8
RFU
C9
RFU
D2
WP#
D3
A7
D4
LB#
D5
ACC
D6
WE#
D7
A8
D8
A11
D9
RFU
E2
A3
E3
A6
E4
UB#s
E5 F5
RDY
E6 F6
A20
E7
A19
E8
A12
E9
A15
RST#f CE2pS_1
F2
A2
F3
A5
F4
A18
F7
A9
F8
A13
F9
A21
G2
A1
G3
A4
G4
A17
G5
CE#1pS2
G6
A23
G7
A10
G8
A14
G9
A22
H2
A0
H3
VSS
H4
DQ1
H5 J5
DQ3
H6 J6
DQ4
H7
DQ6
H8
RFU
H9
A16
VCCpS CE2pS_2
J2
CE#f1
J3
OE#
J4
DQ9
J7
DQ13
J8
DQ15
J9
RFU
K2 L2
RFU
K3 L3
DQ8
K4
DQ10
K5
VCCf_1
K6
VIOpS
K7
DQ12
K8
DQ7
K9
VSS
CE#1pS_1 DQ0
L4
DQ2
L5
DQ11
L6
RFU
L7
DQ5
L8
DQ14
L9
RFU
M2
RFU
M3
RFU
M4
VSS
M5
VCC f_2
M6
RFU
M7
RFU
M8
RFU
M9
RFU
N1
NC
N2
NC
N9
NC
N10
NC
P1
NC
P2
NC
P9
NC
P10
NC
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Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (FBGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Pin Description
A22–A0 A23 DQ15–DQ0 CE#f CE#1pS CE#2pS OE# WE# RDY CLK AVD# UB# LB# RESET# WP# ACC VCCf VCCps VIOps Vss NC RFU = = = = = = = = = = = = = = = = = 23 Address Inputs (Common) 1 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable1 (pSRAM) Chip Enable2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready Output Clock Input Address Valid Input Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin, Active Low (Flash) Hardware Write Protect (Flash) Acceleration pin (Flash) Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply pSRAM Output buffer Power Supply Device Ground (Common) Pin Not Connected Internally Reserved for Future Use
= = = = =
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Logic Symbol
23 A22–A0
A23 CE#f CE1#pS CE2s OE# WE# WP#/ACC RESET# UB# LB# RDY DQ15–DQ0 16
NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline may vary. Any pinout in any MCP, however, will be a subset of the pinout above. In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat them as reserved and not connect them to any other signal. For any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or contact your sales office.
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Device Bus Operation
Table 1.
Operation (Asynchronous) - Flash
Read - Address Latched Read - Address Steady State Write Standby Reset Output Disable
Device Bus Operations
WE#
H H L X X H
CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE#
L H L H L H H X H H L H L H L H L H X H L H H H H H H H H X L H H L H L H L H H X H H H H H H H H H H X H H H L H L H L H H X H H H H L L H X X
Addr
Valid Valid Valid X X X
DQ15DQ0
Valid Valid Valid High-Z High-Z X
UB#
X X X X X X
LB#
X X X X X X
RESET# WP#
H H H H L H H H H H H H
ACC#
H H H H H H
CLK(See Note) AVD#
X X X X X X L L X X X
Operation(Synchronous) Flash CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE#
Load Starting Burst Adress Advance Burst Read to Next Address Terminate current Burst read cycle "Terminate current Burst read cycle via RESET#" "Terminate current Burst read cycle and start new Burst read cycle"
WE#
H H H H H
Addr
Valid X X X Valid
DQ15DQ0
Data Data High-Z High-Z Valid
UB#
X X X X X
LB#
X X X X X
RESET# WP#
H H H L H H H H H H
ACC#
H H H H H
CLK(See Note) AVD#
L H L H H X L H
H L H L H X H L
H H H H H X H H
L H L H H X L H
H H H H H X H H
L H L H H X L H
X L X X X
H X X X
Operation (Asyncronous) - pSRAM
Read Read (Page) Write
CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE#
H H H H H H H H H H H H H H H H H H H H L H L H L H L H L H H X L H H H H H H H H H H H L H H L H L H L H L H L H X L H H H H H H H H H H H H H H H H L H H X H H H H L L H
WE#
H H L
Addr
Valid Valid Valid
DQ15DQ0
Valid Valid Valid Invalid( DQ0-8) Valid(DQ 9-15) Valid(DQ 0-8) Invalid( DQ9-15) High-Z High-Z X
UB#
L H/L L
LB#
L H/L L
RESET# WP#
H H H H H H
ACC#
H H H
CLK(See Note) AVD#
X X X H/L H/L *note
Write(Upper Byte)
L
Valid
L
H
H
H
H
X
*note
Write(Lower Byte) Standby PowerDown Output Disable
L H X H
Valid X X X
H X X X
L X X X
H H H H
H H H H
H H H H
X X X X
*note *note X *note
Operation(Syncronous) pSRAM CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE#
Load Starting Burst Adress Advance Burst Read to Next Address Terminate current Burst read cycle "Terminate current Burst read cycle and start new Burst read cycle"
WE#
H H H H
Addr
Valid X X Valid
DQ15DQ0
Data Data High-Z Valid
UB#
X X X X
LB#
X X X X
RESET# WP#
H H H H H H H H
ACC#
H H H H
CLK(See Note) AVD#
H H H H H H H
H H H H H H H
H H H H H H H
L H L H H L H
H H H H H H H
H L H L H L H
X L X X
H X
Legend: L = Logic 0, H = Logic 1, X = Don’t Care. Note: Default active edge of CLK is the rising edge. Ordering Information
10
S71WS512NE0BFWZZ_00_A1 June 28, 2004
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Information
The order number (Valid Combination) is formed by the following: S 71 WS 512 NE 0 B F W ZZ 0
PACKING TYPE
0 2 3 = Tray = 7” Tape & Reel = 13” Tape & Reel
Additional ordering options
See Product Selector Guide
TEMPERATURE (and RELIABILITY) GRADE
E W I A F B 0 8 A B C E = Engineering Samples = Wireless (-25°C to +85°C) = Industrial (-40°C to +85°C) = Standard (Pb-free compliant) Package = Lead (Pb)-free Package = BGA Package = No second content = = = = = 8 Mb 16 Mb 32 Mb 64 Mb 256 Mb (two 128Mb)
PACKAGE MATERIAL SET (BGA Package Type)
PACKAGE TYPE CHIP CONTENTS—2 CHIP CONTENTS—1
Spansion FLASH MEMORY PROCESS TECHNOLOGY (Highest-density Flash described in Characters 4-8)
N 512 S = 110 nm MirrorBitTM Technology = two S29WS256N = 1.8-volt VCC
BASE NOR FLASH DENSITY BASE NOR FLASH CORE VOLTAGE BASE NOR FLASH INTERFACE and SIMULTANEOUS READ/ WRITE
W 71 S = Simultaneous Read/Write, Burst = Flash Base + xRAM. = Spansion
PRODUCT FAMILY PREFIX
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
June 28, 2004 S71WS512NE0BFWZZ_00_A1
11
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Information
Valid Combinations Order Number S71WS512NE0BFWZZ Package Marking 71WS512NE0BFWZZ
Flash Access Time (MHz) 54
(p)SRAM Access Time (MHz) 54
Temperature Range -25C to +85C
Supplier Supplier 1
Pin Capacitance
Symbol CIN1 CIN2 Cout Parameter Input Capacitance Output Capacitance Control Capacitance Test Condition VIN=0 Vout=0 VIN=0 Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF
12
S71WS512NE0BFWZZ_00_A1 June 28, 2004
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Information
Physical Dimensions TBD
XXX
June 28, 2004 S71WS512NE0BFWZZ_00_A1
13
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Information
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 110 nm MirrorBitTM process technology Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency between read and write operations — Sixteen bank architecture: Each bank consists of 16Mb (WS256N) Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 32, 16, and 8 words with or without wrap-around — Continuous Sequential Burst SecSiTM (Secured Silicon) Sector region — 256 words accessible through a command sequence, 128 words for the Factory SecSi Sector and 128 words for the Customer SecSi Sector. Sector Architecture — S29WS256N: Eight 16 Kword sectors and twohundred-fifty-four 64 Kword sectors — Banks 0 and 15 each contain 16 Kword sectors and 64 Kword sectors; Other banks each contain 64 Kword sectors — Eight 16 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range 100,000 erase cycles per sector typical 20-year data retention typical
S29WS256N 256 Megabit (16 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Power dissipation (typical values, CL = 30 pF) @ 66 MHz — Continuous Burst Mode Read:
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