CY2280PVC-21S

Y 2280 CY2280 100 MHz Pentium® II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Features • Mixed 2.5V and 3.3V operation • Clock solution for Pentium® II, and other similar processor-based motherboards — Four 2.5V CPU clocks up to 100 MHz — Eight 3.3V sync. PCI clocks, one free-running — Two 3.3V 48-MHz USB clocks — Three 3.3V Ref. clocks at 14.318 MHz — Two 2.5V APIC clocks at 14.318 MHz or PCI/2 • EMI control — Spread spectrum clocking — Factory-EPROM programmable spread spectrum margin — Factory-EPROM programmable output drive and slew rate • Factory-EPROM programmable CPU clock frequencies for custom configurations • Available in space-saving 48-pin SSOP package Table 1. Functional Description The CY2280 is a Spread Spectrum clock synthesizer/driver for a Pentium II, or other similar processor-based PC requiring 100-MHz support. All of the required system clocks are provided in a space-saving 48-pin SSOP package. The CY2280 can be used with the CY231x for a total solution for systems with SDRAM. The CY2280 provides the option of spread spectrum clocking on the CPU and PCI clocks for reduced EMI. A downspread percentage is introduced when the SEL_SS input is asserted. The device can be run without spread spectrum when the SEL_SS input is deasserted. The percentage of spreading is EPROM-programmable to optimize EMI-reduction. The CY2280 has power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. CY2280 Selector Guide. CY2280 Configuration Options Clock Outputs –1 4 8 2 2 — 3 1.5 4.0 ns — N/A -1 -2 CPU_STOP XTALIN XTALOUT 14.318 MHz OSC. CPU PLL Divider STOP LOGIC –11S 4 8 2 2 — 3 1.5 4.0 ns — 0.6% –21S 4 8 2 — 2 3 1.5 4.0 ns 2.0–4.5 ns 0.6% CPU (66.6, 100 MHz) PCI (CPU/2, CPU/3) USB (48 MHz) APIC (14.318 MHz) APIC (PCI/2) Reference (14.318 MHz) CPU-PCI delay CPU-APIC delay Spread Spectrum (Downspread) Logic Block Diagram APIC [0:1] VDDAPIC REF [0-2] VDDREF CPUCLK [0-3] VDDCPU PCICLK_F PWR_DWN SEL0 SEL1 SEL100 SEL_SS PCI_STOP SYS PLL Delay STOP LOGIC EPROM VDDPCI PCI [1-7] VDDPCI USBCLK [0:1] VDDUSB Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 11 www.SpectraLinear.com CY2280 Pin Configurations REF0 REF1 VSS XTALIN XTALOUT VSS PCICLK_F PCICLK1 VDDPCI PCICLK2 PCICLK3 VSS PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 VSS AVDD VSS VDDUSB USBCLK0 USBCLK1 VSS 1 2 3 4 5 6 7 48-pin SSOP (Top View) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF REF2 VDDAPIC APIC0 APIC1 VSS RESERVED VDDCPU CPUCLK0 CPUCLK1 VSS VDDCPU CPUCLK2 CPUCLK3 VSS AVDD VSS PCI_STOP CPU_STOP PWR_DWN N/C SEL0 SEL1 SEL100 REF0 REF1 VSS XTALIN XTALOUT VSS PCICLK_F PCICLK1 VDDPCI PCICLK2 PCICLK3 VSS PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 VSS AVDD VSS VDDUSB USBCLK0 USBCLK1 VSS 1 2 3 4 5 6 7 48-pin SSOP (Top View) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF REF2 VDDAPIC APIC0 APIC1 VSS RESERVED VDDCPU CPUCLK0 CPUCLK1 VSS VDDCPU CPUCLK2 CPUCLK3 VSS AVDD VSS PCI_STOP CPU_STOP PWR_DWN SEL_SS SEL0 SEL1 SEL100 CY2280-1 CY2280-11S CY2280-21S Pin Summary Name VDDPCI VDDUSB VDDREF VDDAPIC VDDCPU AVDD VSS XTALIN[1] XTALOUT[1] PCI_STOP CPU_STOP PWR_DWN SEL_SS N/C SEL0 SEL1 SEL100 CPUCLK[0:3] PCICLK[1:7] PCICLK_F APIC[0:1] REF[0:2] USBCLK[0:1] RESERVED Pins 15, 9 21 48 46 41, 37 33, 19 4 5 31 30 29 28 28 27 26 25 40, 39, 36, 35 8, 10, 11, 13, 14, 16, 17 7 45, 44 1, 2, 47 22, 23 42 Description 3.3V Digital voltage supply for PCI clocks 3.3V Digital voltage supply for USB clocks 3.3V Digital voltage supply for REF clocks 2.5V Digital voltage supply for APIC clocks 2.5V Digital voltage supply for CPU clocks Analog voltage supply, 3.3V Reference crystal input Reference crystal feedback Active LOW control input to stop PCI clocks Active LOW control input to stop CPU clocks Active LOW control input to power down device Spread spectrum select input (-11S and -21S options) Spread spectrum select input (-1 option) CPU frequency select input, bit 0 (see Function Table) CPU frequency select input, bit 1 (see Function Table) CPU frequency select input, selects between 100 MHz and 66.6 MHz (see Function Table) CPU clock outputs PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively Free-running PCI clock output APIC clock outputs 3.3V Reference clock outputs USB clock outputs Reserved Page 2 of 11 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 Ground Rev 1.0, November 25, 2006 Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. CY2280 Function Table (-11S Option) SEL100 SEL1 SEL0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 SEL_SS[2] N/A N/A N/A 0 (downspread) 1 (no spread) N/A N/A N/A 0 (downspread) 1 (no spread) CPU/PCI Ratio 2 2 2 2 2 3 3 3 3 3 CPUCLK Hi-Z Reserved Reserved PCICLK_F PCICLK Hi-Z Reserved Reserved Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK[3] 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz REF Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK[3] 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz APIC USBCLK Hi-Z 48 MHz 48 MHz 48 MHz 48 MHz TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz 66.66 MHz 33.33 MHz 66.66 MHz 33.33 MHz TCLK/2 Reserved Reserved 100 MHz 100 MHz TCLK/6 Reserved Reserved 33.33 MHz 33.33 MHz Function Table (-21S Option) SEL100 SEL1 SEL0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 0 1 1 SEL_SS[2] N/A N/A N/A 0 (downspread) 1 (no spread) N/A N/A N/A 0 (downspread) 1 (no spread) CPU/PCI Ratio 2 2 2 2 2 3 3 3 3 3 CPUCLK Hi-Z Reserved Reserved PCICLK_F PCICLK Hi-Z Reserved Reserved Hi-Z 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK[3] 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz REF Hi-Z Reserved Reserved 16.67 MHz 16.67 MHz TCLK/12[3] Reserved Reserved 16.67 MHz 16.67 MHz APIC USBCLK Hi-Z 48 MHz 48 MHz 48 MHz 48 MHz TCLK/2 48 MHz 48 MHz 48 MHz 48 MHz 66.66 MHz 33.33 MHz 66.66 MHz 33.33 MHz TCLK/2 Reserved Reserved 100 MHz 100 MHz TCLK/6 Reserved Reserved 33.33 MHz 33.33 MHz Actual Clock Frequency Values Clock Output CPUCLK CPUCLK USBCLK Target Frequency Actual Frequency (MHz) (MHz) 66.67 100 48.0 66.654 99.77 48.008 PPM –195 –2346 167 Power Management Logic CPU_STOP X 0 0 1 1 PCI_STOP X 0 1 0 1 0 1 1 1 1 PWR_DWN CPUCLK Low Low Low Running Running PCICLK Low Low Running Low Running PCICLK_F Low Running Running Running Running Other Clocks Low Running Running Running Running Osc. Off PLLs Off Running Running Running Running Running Running Running Running Notes: 2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0. 3. TCLK supplied on the XTALIN pin in Test Mode. Rev 1.0, November 25, 2006 Page 3 of 11 CY2280 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage.................................................–0.5 to + 7.0V Input Voltage............................................ –0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) ....–65 C to +150 C Junction Temperature................................................ +150 C Package Power Dissipation.............................................. 1W Static Discharge Voltage .......................................... > 2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Operating Conditions[4] Parameter AVDD, VDDPCI, VDDUSB, VDDREF VDDCPU VDDAPIC TA CL Description Analog and Digital Supply Voltage CPU Supply Voltage APIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK PCICLK APIC, REF USB Reference Frequency, Oscillator Nominal Value Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 14.318 0.05 Min. 3.135 2.375 2.375 0 Max. 3.465 2.625 2.625 70 20 30 20 20 14.318 50 MHz ms Unit V V V C pF f(REF) tPU Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Except Crystal Inputs [5] Test Conditions Except Crystal Inputs[5] IOH = 12 mA CPUCLK IOH = 18 mA APIC IOL = 12 mA IOL = 18 mA CPUCLK APIC Min. Max. Unit 2.0 0.8 2.0 0.4 2.4 V V V V V High-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V Low-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V High-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB = 3.135V IOH = 14.5 mA PCICLK IOH = 16 mA USBCLK IOH = 16 mA REF VOL Low-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB= 3.135V IOL = 9.4 mA PCICLK IOL = 9 mA IOL = 9 mA USBCLK REF –10 –10 0.4V V IIH IIL IOZ IDD25 IDD25 IDD33 IDDS Input High Current Input Low Current Output Leakage Current Power Supply Current for 2.5V Clocks[6] Power Supply Current for 2.5V Clocks[6] Power Supply Current for 3.3V Clocks[6] Power-down Current[6] VIH = VDD VIL = 0V Three-state VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs Current draw in power-down state +10 10 +10 70 100 170 500 A A A mA mA mA A Notes: 4. Electrical parameters are guaranteed with these operating conditions. 5. Crystal Inputs have CMOS thresholds. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev 1.0, November 25, 2006 Page 4 of 11 CY2280 Switching Characteristics[6, 7] Parameter t1 t2 Output All CPUCLK, APIC PCICLK USBCLK, REF CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK PCICLK, PCICLK CPUCLK, APIC APIC CPUCLK PCICLK CPUCLK, PCICLK Description Output Duty Cycle[8] CPU and APIC Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate USB, REF Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew [9] Test Conditions t1 = t1A t1B -1,-11S, -21S -1,-11S, -21S Between 0.4V and 2.0V Min. 45 1.0 Typ. 50 Max. 55 4.0 Unit % V/ns t2 t2 t3 t4 t5 t6 Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 2.0V and 0.4V Measured at 1.25V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.25V for 2.5V clocks Measured at 1.25V Measured at 1.25V Measured at 1.5V CPU, PCI clock stabilization from power-up 1.0 0.5 4.0 2.0 1.6 1.6 100 175 4.0 V/ns V/ns ns ns ps ns -1,-11S, -21S -1,-11S, -21S -1,-11S, -21S 0.4 0.4 1.5 t7 t8 t9 t10 t11 t12 PCI-PCI Clock Skew CPU-APIC Clock Skew[10] APIC-APIC Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time 250 -21S 2.0 100 -1,-11S, -21S 200 250 4.5 175 250 500 3 ps ns ps ps ps ms Notes: 7. All parameters specified with loaded outputs. 8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 9. PCI lags CPU for -11S and -21S options. 10. APIC lags CPU for -21S option. Rev 1.0, November 25, 2006 Page 5 of 11 CY2280 Switching Waveforms Duty Cycle Timing t1A OUTPUT t1B All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 t2 t4 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t7 CPU-APIC Clock Skew (-21S only) CPUCLK APIC t8 Rev 1.0, November 25, 2006 Page 6 of 11 CY2280 Switching Waveforms (continued) APIC-APIC Clock Skew APIC APIC t9 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Rev 1.0, November 25, 2006 Page 7 of 11 CY2280 Spread Spectrum Clocking Spread Spectrum Disabled Spread Spectrum Enabled Amplitude (dB) Frequency (MHz) Table 2. Description Modulation Frequency Down Spread Margin at the Fundamental Frequency Down Spread Margin at the Fundamental Frequency Configuration All (except -1) -11S -21S CPU, PCI CPU, PCI, APIC Outputs Min. 30.0 0.0 0.0 Max. 33.0 –0.6 –0.6 Unit kHz % % Rev 1.0, November 25, 2006 Page 8 of 11 CY2280 Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 F–22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Rev 1.0, November 25, 2006 Page 9 of 11 CY2280 Test Circuit VDDPCI, VDDCORE, VDDUSB, VDDREF 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 9, 15, 19, 21, 33, 48 0.1 F CY2280 VDDCPU, VDDAPIC 37, 41, 46 0.1 F OUTPUTS CLOAD Notes: Each supply pin must have an individual decoupling capacitor. All capacitors must be placed as close to the pins as is possible. Rev 1.0, November 25, 2006 Page 10 of 11 CY2280 Ordering Information Ordering Code CY2280PVC-1 CY2280PVC-11S CY2280PVC-21S Package Name O48 O48 O48 Package Type 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP Operating Range Commercial Commercial Commercial Package Diagram 48-Lead Shrunk Small Outline Package O48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 25, 2006 Page 11 of 11